JPH0744582B2 - Bus control circuit - Google Patents

Description

The present invention relates to a bus control circuit that transmits an acknowledge when data is received from a data bus system to transfer the data, and reduces the processing of the microprocessor and effectively sends the acknowledge data. A transmission buffer that stores at least one piece of data to be transmitted in a system that transmits and receives data by a bus and transmits an acknowledge signal to a transmitting device when the data is received for the purpose of providing a bus control circuit, and an acknowledge signal. And an selector for switching the selection of the output of the transmission buffer to the output of the acknowledge buffer when a signal for detecting the timing of sending the acknowledge signal is added.

[Industrial application field]

The present invention relates to a data bus system that transmits and receives data with a single bus, and more particularly, to a bus control circuit that transmits an acknowledge to transfer data when data is received from the data bus system.

[Conventional technology]

In a device connected to a data bus system, for example, a home bus system, a reception buffer for receiving data to be transmitted, a transmission / reception address, an acknowledge, and the like, and data temporarily addressed to itself via the data bus And a buffer. In addition to this, a control circuit and a processor are provided, and the procedure of the read hierarchy is controlled by these control circuits, and further, the procedure of the soft hierarchy is controlled by the microprocessor.

When transferring data to a target device in such a bus system, the transmitting device first has its own address (the address of the transmitting device), the other party's address (the address of the receiving device), the control data, and the data length. Further, the data and the like are sequentially transmitted to the bus line, and the device corresponding to the partner address fetches the control data, data length and data after the partner address from the bus line.
Then, when all the data is received, the acknowledge data indicating that the data has been received is sent to the transmitting side device,
The transmitting side device is characterized in that the data transfer is normally completed by receiving the acknowledge data.

This acknowledge data is sent after being stored in the above-mentioned transmission buffer under the control of, for example, a microprocessor.

[Problems to be solved by the invention]

In the system as described above, the device for receiving the data has to send the acknowledge data within a specific time in packet units consisting of a plurality of codes having the data after receiving the data. Therefore, for example, a microprocessor or the like detects this time, and at that time, acknowledge data is stored in the transmission buffer and then transmitted.

Since there is such a time control at the time of sending, the microprocessor has a problem that it must always detect the time.

There is also a method in which this time is detected by hardware, and when detected, the microprocessor is interrupted and the acknowledge data is stored in the transmission buffer. This reduces the processing of the microprocessor, but has a problem that an error occurs in a state where an interrupt does not occur such as during DMA transfer.

The present invention has been made in view of the above-mentioned conventional drawbacks, and an object of the present invention is to provide a bus control circuit which reduces the processing of a microprocessor and effectively sends out acknowledge data.

[Means for solving problems]

FIG. 1 is a block diagram of the present invention. The transmission buffer 1 is connected to a microprocessor or the like, and temporarily stores transmission data. The acknowledge buffer 2 is a register for temporarily storing data such as acknowledge data or a response to a transfer such as a knot acknowledge. The selector 3 is the transmission buffer 1 and the acknowledge buffer. The output of the acknowledge buffer 2 is selected by detecting the time when the acknowledge or the like is transmitted by adding the output of 2 to the output of the acknowledge buffer 2.

[Action]

In a system that transmits / receives data via a bus and sends an acknowledge signal to a transmitter when the data is received, in order to send the data, the data sent to the send buffer 1 is stored, and the data output from there is selected by a selector. 3 selects and outputs. The output of the selector 3 is converted into, for example, serial data and sent to the bus line.

On the other hand, when converting data from another device and sending acknowledge data, regardless of the sending timing,
Acknowledge data is stored in acknowledge buffer 2.

When the selector 3 detects the timing of sending the acknowledge signal, that is, the timing, the selector 3 selects the acknowledge buffer and outputs the acknowledge data. Similar to the transmission data, this acknowledge data is converted into, for example, serial data and output to the bus line.

As a result, acknowledge data is automatically transmitted.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a system configuration diagram of an embodiment of the present invention. The microprocessor 11 and the bus control circuit 12 are connected to the data bus (DATA
(D0 to D7) line, address bus (A _{0 to} A ₂ ) line, chip select (▲ ▼) line, write signal (▲ ▼) line, read signal (▲ ▼) line, reset signal (▲)
▼) line and interrupt signal (▲ ▼) line. The terminals of the bus control circuit 12 connected to these signal lines are terminals for the following respectively. Address bus A ₀ ~
The terminal connected to A ₂ is a terminal for selecting an internal register (the bus control circuit 12 in the embodiment of the present invention has eight registers, which will be described later).
The A ₀ to A _2, register TXDR, RXDR, AKR, CCR, STR1,
One of STR2, MDR, MLC is selected. The chip select signal terminal is a terminal that is added to the bus control circuit 12 when the microprocessor 11 selects it, and is selected when "L".
It is possible to write to and read from each register of the bus control circuit 12. The write signal terminal is a terminal that adds an "L" signal when writing data to each register, and the read signal terminal is a terminal that adds "L" when reading data from each register. When "L" is applied to the write signal terminal, the address value applied from the address signal terminal, that is, the data applied from the data bus is stored in the register designated by the register indication value, and when "L" is applied to the read signal terminal, The contents of the register designated by the register designation value added from the address signal terminal are output to the data bus.

The reset terminal is a terminal for resetting the bus control circuit 12, and when "L" is added, the bus control circuit 12 initializes the value of each register.

The interrupt signal terminal is a terminal output by the bus control circuit 12, and, for example, when one byte of data is received, "L" is output from the terminal.

Although not shown, ROM, RAM, etc. are connected to the microprocessor 11, which executes a program stored in the ROM and sends control data to a control channel (CH) of a home bus described later via the bus control circuit 12. Etc. are sent and received. still,
The microprocessor 11 has the upper bits of the address bus, for example, A _{15 to} A ₃ in addition to the address buses A _{0 to} A ₂ , and the ROM and RAM are connected to these address buses A _{15 to} A ₀ . Then, it operates as a processor circuit.

On the other hand, the bus control circuit 12 is connected to the home bus driver / receiver 13 in addition to the above-mentioned terminals (HB data (▲ ▼) input terminal, HB data (+) direction output terminal, HB data (-) direction) And a clock input terminal to which the clock signal CLK is applied from the basic frequency generator 14. Basic frequency generator 14 is 4.9 MHz or 614.4 KHz
The bus control circuit 12 outputs the clock signal of
Has a clock select terminal to which a clock select signal (CSEL) indicating the frequency is added when a signal of one of these two frequencies is applied.

FIG. 3 is a circuit configuration diagram of the bus control circuit 12. The above-mentioned data (DATA), address signals A _{0 to} A ₂ , write signal ▲
▼, read signal ▲ ▼, chip select signal ▲
▼, reset signal ▲ ▼, clock signal CLK,
The interrupt signal ▲ ▼ and the clock select signal CSEL are added to the buffer circuit 15 (CPU-I / O), and the buffer circuit 1
The 5 adds these signals to each circuit of interest.

The clock signal CLK is applied to the clock generation circuit 16 and the edge detection circuit 17 as a master clock. Clock generation circuit
16 generates a clock for each circuit described later and adds it to each.

The edge detection circuit 17 receives the received data, that is, the HB data (▲
▼) is added, and when the edge detection circuit 17 detects a data edge from the master clock, it outputs a data edge detected, that is, the start of data reception, to a pause counter 18 and a status counter (MDR) 19 described later. To do.

The HB data (▲ ▼) is added to the sampling circuit 20, the competition loss detection circuit 21, and the short message interruption detection circuit 22 in addition to the edge detection circuit 17. The HB data is, for example, 9600 bps serial data, and the sampling circuit 20 sequentially reads the serial data bit by bit and adds the serial data to the RX shift register 23.

The home bus HB in FIG. 2 is, for example, two twisted wires. The home bus driver / receiver 13 sends a signal to the home bus HB or receives a signal from another device. The signal output to the baume bus HB consists of 11 bits per data. FIG. 4 is a data configuration diagram. One data is 1 start bit ST, 8
Bit transfer information (transfer data B0 to B7), 1-bit parity bit (PA), and 1-bit stop bit (SP). In home bus HB, "L"
When it represents (“0”), there is a positive or negative pulse, and when it represents “H” (“1”), there is no pulse. The start bit is always "L"("0"), the stop bit is always "H"("1"), and the data B0 to B7 in FIG. Such data is converted to 0, 1 signals,
The received data ▲ ▼ is added to the bus control circuit 12. The sampling circuit 20 is a circuit that sequentially samples signals of 0 and 1. The RX shift register 23 receives each bit B0 to B7 of one transfer information added in 1-bit units from the sampling circuit 20 and shifts. At this time, each time the RX shift register 23 shifts the data, the data is also output to the parity check circuit 24, and the parity check circuit 24 counts the number of bits of 0 or 1 in one transfer information and outputs 1 bit. Compare with the parity added after the transfer information.
This parity is even parity or odd parity as in the past, and it is determined whether or not the data is normal each time one transfer information is received, and if it is not normal, for example, when the number of 0 bits is not even, a data error is detected. Store in the status register (STR2) 29.

The RX shift register 23 is a serial-in / parallel-out shift register, and each time one transfer information is received,
The 8-bit information is stored in the reception data register (RXDR) 30. As will be described later, when one transfer information is stored in the reception data register (RXDR) 30, the microprocessor 11 adds a signal for turning on a flag capable of reading this data to the status register (STR1) 31. By this storage, for example, the processor can read this status register (STR1) 31 and recognize that one byte of information is transferred to the reception data register when the reception flag is on.

Each circuit described above can receive data from the home bus HB.

The register (TXDR / AKR) 28 is a transmission buffer when transmitting transfer information and the like to another device via the home bus HB.
When the microprocessor 11 selects this register (TXDR / AKR) 28 and stores transfer information etc., the TX shift register
25 reads it, adds a start bit, and sequentially outputs it as 1-bit serial data SO to the AMI circuit 26 and the competition loss detection circuit 21. It should be noted that 8-bit data to be transferred is added to the parity generation circuit 27 via the TX shift register 25, a parity is generated corresponding to the data to be transferred, and the parity is added to the TX shift register 25. This parity is set to 1 as shown in the data structure diagram of FIG.
After the transfer information B0 to B7 is inserted at the parity bit position, the TX shift register 25 outputs the parity bit PA. Then, the TX shift register 25 inserts a stop bit SP after this parity bit PA and finishes sending one data.

A control signal is added from the control code register (CCR) 32 to the transmission control unit 33, and the transmission control unit 33 receives the data from the register (TXDR / AKR) 28 by the signal.
A signal for reading out to the TX shift register 25 and sequentially controlling transmission in 1-bit units is added to the TX shift register 25. By this control, the serial data SO described above is TX
It is output from the shift register 25. In the home bus HB, positive and negative pulses as shown in FIG. 4 are repeatedly generated when the data is "0" in order to eliminate the direct current component of the current in the transfer of serial data. The AMI circuit 26 controls this repetition and generates a control signal for outputting positive and negative pulses. This AMI circuit
Serial data SO is added to 26. For example, when the serial data is "00000000001" as shown in FIG. 4, the transmission data signals ▲ ▼ and ▲ ▼ are ▲ ▼ and ▲ ▼ sequentially as shown in FIG. Positive or negative pulses are generated to indicate "0".

FIG. 6 is a transmission circuit diagram of the home bus driver / receiver 13. The transmission data ▲ ▼ and ▲ ▼ are applied to the bases of the transistors Tr ₁ and Tr ₂ via inverters 11 and 12 and resistors R1 and R2, respectively. Transistor Tr
The emitters of ₁ and Tr ₂ are grounded, and the collectors are connected to both ends of the primary side of a transformer L whose middle point on the primary side is connected to a power supply V ₈ . Both ends of the secondary side of the transformer L are connected to the home bus HB via capacitors C1 and C2.
Since the transmission data ▲ ▼ is added to the inverter 11, in the case of the configuration shown in FIG. 6, bits ST0, B1, B
The transistor Tr ₁ is turned on at 3, B5, and B7. In addition, since the transmission data ▲ ▼ is added to the inverter 12, the transistor Tr is set for bits B0, B2, B4, B6, and PA.
₂ is turned on.

When the transistor Tr ₁ is turned on, from the power supply V ₈ ,
A current flows to the side to which the transistor Tr ₁ is connected via the intermediate point on the primary side, and as a result, a positive pulse is output to the home bus HB. In contrast, the transistor
When Tr ₂ is turned on, the opposite is true and a negative pulse is output to home bus HB. Incidentally, the capacitor C1,
C2 is an element for setting the DC setting and low frequency band. Since the home bus HB may supply electric power via the bus in some cases, this capacitor cuts off the direct current component.

Ac signal AC is used to transmit each information on the home bus HB.
K or Knack (Not Acknowledge) signal NAK is sent to determine whether or not the other device that sent the data has received the data. The ACK signal ACK and the NACK signal NAK are generally treated as data to be transmitted, that is, one information. For this reason, the number of registers for storing data to be transmitted is one in the past, but two are provided in the present invention and are divided into one for data and one for ACK. FIG. 7 is a configuration diagram of the register (TXDR / AKR) 28.

The 8-bit data from the buffer circuit 15 is divided and stored in the data register 28-1 and the ACK / NAK register 28-2. As will be described later, this data register (TXDR) 28-1 and AC
The K / NAK register 28-2 stores the data separately via the buffer circuit 15. The transmission control unit 33 adds a selection signal for selecting these registers to the register (TXDR / AKR) 28, and this selection signal is the selector 28 in FIG.
Enter in -3. The selector 28-3 is a circuit that selects one of the data in the data register 28-1 or the ACK / NAK register 28-2 with this selection signal.
Join the shift register 25. Conventionally, as described above, the data of one register is transmitted, but as in the configuration of FIG. 7, the data which is the information to be transmitted is stored in two registers and is required. At that time, the register is selected and transmitted. The selection of this register is made for the purpose of sending information or sending an ACK signal, and writing from the microprocessor 11 to the register is not limited to conversion of writing depending on these applications, but also data and ACK signals. The program can be created without detecting the procedure.

The embodiment of the present invention shown in FIG. 3 has eight registers, which are read or written via the buffer circuit 15. Write to registers CCR, TXDR /
AKR, which is written in a target register according to an instruction from the buffer circuit 15, that is, a write instruction from the microprocessor 11. Read from register RXD
R, CCR, STR1, STR2, MDR, MLC, address signal A ₀
The data select circuit 34 selects the output according to the values of A ₂ to A _{2 and} the microprocessor 11 is selected via the buffer circuit 15.
Output to the data bus of (DATA).

The transmission data register TXDR is a write-only 8-bit register. Data sent to the bus is written in this register by the microprocessor 11 except for ACK / NAK. A series of data transmission operations are started by writing data in this register. Receive data register
RXDR is an 8-bit register dedicated to reading home bus data. Register AKR (ACK / NAK transmission register) is ACK /
This is a write-only 8-bit register for NAK transmission.
When a value is written to this register, data will be sent during the next ACK / NAK transmittable period. However, if transmission is unnecessary due to broadcast, short message interrupt, or error (data reception error, write lost data error), do not transmit. Moreover, it is not transmitted over the next packet. The control code register CCR is a readable / writable flag register for control. The upper 4 bits are 0H (16
Mode 1 is selected by setting it to "advance" and mode 2 is selected by setting it to 6H. When releasing the reset, the flags of CCR other than the RES flag are ignored.

FIG. 8 is a bit configuration diagram of the register CCR in mode 1. Bits bit7 to bit4 are areas for instructing mode 1, and writing 0H in this area sets mode 1. Bit bit3 is a short message interrupt flag SMI, and when this flag is "1", a short message interrupt is generated in a section in which a short message interrupt is possible (long message MDR = 8). In addition, it is possible to interrupt the long telegram that is being transmitted, and the short telegram interrupt operation can be operated regardless of the transmission. This flag becomes "0" when the status counter (MDR) becomes "1" or when the status counter (MDR) becomes "2" during the synchronization recovery period.

Bit bit2 is a reset flag RES. When this flag becomes "0", all the states are returned to the initial state and the operation is stopped. If this flag becomes "0" during transmission, the transmission is aborted at that point, and if there are bits left behind, those bits are not transmitted. Further, when this flag becomes "1", the operation is started (in the synchronization recovery period). When the reset terminal is reset or when the power is turned on
To start the operation of the IC, it is necessary to set "1" from the microprocessor 11.

Bit bit1 is the reception interrupt mask flag RIM, and when this flag is "0", it is received in one packet,
Stops short message interrupt, data reception error, read lost data, framing error, parity error, and ACK / NAK error interrupts. However, this flag is ▲
▼ The INTR flag itself operates normally only by masking the output of the pin. When it is "1", an interrupt is normally generated. This flag is 10ms + when the status counter (MDR) becomes "1" or when there is no data on the bus.
It becomes "1" when the sync recovery period is canceled for 22 bits. However, an interrupt can be generated by writing "1" to this flag even during the synchronization recovery period.

Bit bit0 is a transmission interrupt mask flag TIM. When this flag is "0", transmission within one packet,
Do not lose contention and generate write lost data interrupt. However, this flag only masks the output of the ▲ ▼ pin, and the INTR flag operates normally. Also, "1"
When, the interrupt is generated normally. This flag becomes "1" when the status counter (MDR) becomes "1" or when there is no data on the bus for 10 ms + 22 bits and the synchronization recovery period is released. However, an interrupt can be generated by writing "1" to this flag even during the synchronization recovery period.

FIG. 9 is a bit configuration diagram of the register CCR in mode 2. Mode 2 is set when bits 7 to 4 are 0H.
In this mode, bit bit1 is a broadcast WBRC, and when this flag is set to "1", the packet currently being transmitted / received thereafter operates as a broadcast packet. If "0" is set, it operates as an individual packet.

Bit bit0 is a long message text flag LMES. When this flag is set to "1", the packet currently being transmitted / received thereafter operates as a long message packet. If "0" is set, it operates as a short message packet on the contrary.

The status register (STR1) 31 is a read-only flag register that indicates the status of the bus and packets. First
FIG. 10 is a bit configuration diagram of the status register (STR1) 31.

Bit bit7 is the interrupt flag INTR. This flag is ▲
The signal is the same as that of the ▼ terminal, and becomes "1" when an interrupt such as data input / output is necessary, and interrupts the CPU, that is, the microprocessor 11. When the microprocessor 11 reads the status register (STR1) 31, the ▲ ▼ terminal becomes "H" and this flag becomes "0". This flag becomes "1" when the status counter (MDR) becomes "1" or when the status counter (MDR) becomes "2" during the synchronization recovery period.

Bit bit6 is a short message interrupt flag RSMI. It becomes "1" when a short message interrupt is detected (when the stop bit becomes "0" in the data part of the long message). Further, this flag becomes "0" when the state counter (MDR) becomes "1" or when the state counter (MDR) becomes "2" during the synchronization recovery period. The judgment of the long message is performed by the "priority code", and when this flag becomes "1" (when a short message interrupt occurs), the FE (framing error) flag is not set.

Bit bit5 is the competition loss flag CD. Although the competitive loss will be described later, if the transmitted data and the received data are different in the "priority code" and the "self address", this flag is "competitive loss", and this flag is "1". Therefore, even if the parity bit and the stop bit are different, the competition will be lost.

Bit bit4 is a transmission flag TX and is set to "1" at the time of data transmission. Also, this flag is a status counter (MDR).
Becomes "1" or during the synchronization recovery period, the status counter (MD
When R) becomes "2", it becomes "0". Also, it is set to "0" when the contention is lost (when the CD flag is set) and when the short message interrupt (MDR is 0 → 1 after the short message interrupt occurs). However, it is not set to "1" at ACK / NAK transmission after data reception (initial value: 0).

Bit bit3 is the error flag ERR and the error flag (RDE, WLD, RLD, FE, P of the status register (STR2) 29.
This flag is set to "1" when any of (E, AKE) becomes "1".
become. This flag is the OR of the error flags of STR2. Also, it reads "0" when the status register (STR2) 29 is read or when the status counter (MDR) becomes "1" or when the status counter (MDR) becomes "2" during the synchronization recovery period.
become.

Bit bit2 is a broadcast flag BRC. This flag is "1"
When it is, it indicates that the telegram being received is a "broadcast" packet, and when it is "0", it indicates an "individual" packet.
This flag is set to the value of bit 6 of the priority code when the status counter (MDR) becomes "4". Also, it becomes "0" when the status counter (MDR) becomes "1" or when the status counter (MDR) becomes "2" during the synchronization recovery period.

Bit bit1 is a data reception completion flag RXRDY. It becomes "1" when data can be passed to the microprocessor 11. It becomes "0" when the microprocessor 11 receives the data, and "0" when the status counter (MDR) becomes "1" or when the status counter (MDR) becomes "2" during the synchronization recovery period. "become.

Bit bit0 is a transmission completion flag TXRDY. It becomes "1" when data can be received from the microprocessor 11, and becomes "0" when data is received from the microprocessor 11 (initial value: 1).

The status register (STR2) 29 is a read-only flag register that indicates errors on the bus and packets.
FIG. 11 is a bit configuration diagram of the status register (STR2) 29. Bits bit7 to bit2 are error flags and are set when an error occurs.

RDE and WLD read this register or become "0" when the status counter (MDR) becomes "2" during the synchronization recovery period, and RLD, FE, PE and AKE read this register or read status counter (MDR). It becomes "0" when MDR) becomes "1" or when the status counter (MDR) becomes "2" during the synchronization recovery period.

Bit bit7 is a data reception error flag RDE, and in the embodiment of the present invention, synchronization is achieved with a start bit for each character during reception. At this time, if the start bit cannot be detected normally, this flag becomes "1".
It also becomes "1" when more data is received than the message length code. However, this flag does not work for ACK / NAK reception errors. When this flag becomes "1", the synchronization recovery period starts.

Bit bit6 is a write lost data flag WLD. If character data has not been written in the transmission data register (TXDR) by the start of transmission of the next character, this flag becomes "1". When this error occurs,
The transmission stops and the synchronization recovery period starts.

Bit bit5 is the read lost data flag RLD, and when there is data in the receive data register (RXDR),
When the next data is input from the bus (at this time,
RXDR value changes to new data) becomes "1". However, if the status register (STR2) 29 is read and set to "0" without reading RXDR, the cause of the error has not been cleared and this flag is set again when the next interrupt occurs. The cause of the error is cleared by reading RXDR (initial value: 0).

Bit bit4 is a framing error flag FE, which becomes "1" when the stop bit becomes "1" other than the data part of the long telegram.

Bit bit3 is a parity error flag PE, which becomes "1" when the above-mentioned parity check circuit 24 detects a parity error. In the embodiment of the present invention, the parity is even parity.

Bit bit2 is ACK / NAK error flag AKE, ACK / NAK
When the start bit of is not detected within the range of ± 13μs, it becomes "1".

Bit bit0 is a synchronization recovery period flag DRE. This flag becomes "1" immediately after reset or when a data reception error (RDE) or a write lost data error (WLD) occurs, and the synchronization recovery period starts. When the synchronization recovery period ends, this flag becomes "0" and the normal mode is entered.

Register 19 (status counter) MDR indicates the status of the packet being received on the bus. This is a read-only register that takes values from 0 (00H) to 11 (0BH). In the embodiment of the present invention, information data is transmitted / received in units of packets including a plurality of codes, and the state counter MDR also indicates the transmission / reception state of these codes. Fig. 12 ~
FIG. 15 is an explanatory diagram of states of the state counter. Each figure is INTR
It shows the value of the status counter and the status of the bus data when the flag is raised. The value of the previous state counter continues during the start bit.

The status counter, or bit counter in register 19
35, the edge detection circuit 17, the pause counter 18, and the short telegram interrupt detection circuit 22 are connected. Although not shown, the bit counter 35 is added with signals from the sampling circuit 20 and the RX shift register 23 to obtain the bit position currently received. The bit detection signal of the received data from the bit counter 35 is used to determine the current state. FIG. 16 is a state counter value and its state chart, and FIG. 17 is a state transition diagram. When the state counter value is 0, that is, the state S0 is reset release, data exists on the bus,
It is the bus availability detection period for the subsequent 22-bit and 44-bit periods. In that state S0, 10
msec-22-bit time-208 μsec is a rest period (state S1)
Then, after this period, the state becomes the state S2.

The pause counter 18 includes a bit counter 35 and an edge detection circuit.
17, the output of each of the packet status registers 39 is added, and the pause counter 18 obtains the pause time from these outputs.

In the first half of the pause time, when the state counter (MDR) 19 is "0", even if there is data on the bus, it is not recognized as a packet. Normally 22 bits when there is no data, 44 bits when broadcasting
If it continues for a minute, it changes to the next state. This is because the packet in which the "telegram length code" does not match the actual data length, or the synchronization adjustment immediately after resetting.

At the time of transmission, the transmission is started after the rest time is over. However, when another device starts transmission during the contention monitoring period, the transmission is performed accordingly.

When the state counter 19 receives data at "0", a data reception error occurs and the synchronization recovery period starts. After that, the state counter 19 becomes "2".

When a transmission request is added from the home bus HB when the state counter 19 is "2", the state becomes S2 '. At this time, the value of the state counter 19 does not change. State S2 is a contention monitoring period and is in a data input waiting state. When data is present on the bus, the states S3, S4, S5, S6, and S7 are sequentially passed, that is, the value of the state counter 19 is sequentially advanced to 3 to 7, and the state is S8.

The states S3, S4, S5, S6, and S7 are the priority code, self address code, partner address code, control code, priority code period corresponding to the message length code, self address period, partner address period, control code period, respectively. It is a message length code period. The states S2 to S8 are states in which data is received, and when the self address is received in the partner address period, the data is received.

State 8 is a data period. In this state, the state counter 19 becomes 0 when there is a short message interrupt in the data, that is, the information. That is, the state becomes S0.

As shown in FIG. 30, the short message interrupt detection circuit 22 is added with the output of the state S8 of the state counter 19, the received data ▲ ▼ and the output of the stop bit signal detection of the bit counter 35. , If the value of the status counter 19 is 8 and the received data at that time is “0” (it becomes “1” because it is inverted) at the stop bit position, “1” is output and the status register (STR1) 31 Join in. As a result, the short message interruption can be detected.

In the home bus HB system, it is possible to generate a short telegram interrupt from a device connected to the home bus. In the home bus system, the short telegram interrupt can be performed when the device that interrupts the stop bit SP outputs "0", that is, generates a pulse. The short message interruption detection circuit 22 detects the interruption of this short message. That is, when the short telegram interrupt detection circuit 22 detects an interrupt, the detection signal is added and the state counter 19 is reset to 0 (state S0). Further, at this time, an interrupt detection signal is output to the transmission control unit 33 to stop the subsequent transmission control. At the same time, the short message telegram interrupt detection signal is also applied to the status register (STR1) 31 to turn on the bit 6 short message telegram interrupt flag RSMI.

When the data period (reception of data if reception) ends, the state moves to state S9. State 9 is the check code period, and after receiving the check code, the state becomes S10,
It is a dummy code period. In addition, at the time of broadcasting, the state 0, that is, the state counter value is set to 0. After the dummy code, there is an ACK / NAK period, and the ACK / NAK signal is sent during this period. Then, the state becomes S0.

On the other hand, when there is a transmission request in the state S2, the state becomes S2 '(the value of the state counter does not change) as described above, and then the state becomes S3' (priority code period).

When transmission requests are simultaneously issued to a plurality of devices and data and the like are sent at the same time, a conflict occurs. On the home bus HB,
When the contention state occurs, the priority is set for each device, and when the contention occurs, the device having the highest priority among the competing devices is prioritized. The priority is determined by the priority code. The priority consists of a total of 8 bits of D0 to D7, "00000000" is the highest and "11111111" is the lowest. When high priority and low priority send the priority code at the same time within the priority code period, each bit is output on the bus at the same time. Although each bit is output at the same time, as described above, in the home bus, the pulse is output at "0" and the pulse is not output at "1", so the device that outputs "0" is forced. Set the home bus bit to "0". On the other hand, a device with a low priority level sends out "1" instead of "0", which is different from the data on the bus line. The competition loss detection circuit 21 detects this change in data. The serial output SO of the TX shift register 25 and the reception signal ▲ ▼ of the home bus driver / receiver 13 are added to the competition loss detection circuit 21. The competition loss detection circuit 21 compares these two signals, that is, the reception signal ▲ ▼ with the serial output SO, and when SO and the reception signal ▲ ▼ match, the priority is high or there is no competition. Yes, there is no competition loss. However, when the priority code of the other device is high, the code with the higher priority code is added as the received signal ▲ ▼, so the conflict loss detection circuit 21 detects a mismatch and the high level of the priority code is transmitted. It detects that there is a discrepancy and adds a mismatch signal to the transmission control unit 33. As a result, the transmission control unit 33 stops the transmission of the priority code currently being transmitted. At the same time, the status register (STR1) 31
Notify the competitor of losing. That is, the competition loss flag CD of bit 5 of the status register (STR1) 31 is turned on ("1"). FIG. 18 is an explanatory diagram of competition. When another device (IFU) sends a high-level priority code and this device (IFU) outputs a low-level priority code, this device does not output "0" at D0 of the code. You will lose. This loss of contention causes the device's INTR flag to turn on again at the next start bit. Also, the transmission flag is turned off at the next start bit after the time when the competition is lost. Further, the above-mentioned CD flag is turned on at the next start bit. For example, if the interrupt is released, the interrupt ▲ ▼ is added to the microprocessor 11.

The flag information of the register CCR32 is added to the interrupt control unit 36,
The flag information of the status register (STR1) 31 is also added to the control unit 36. The interrupt control unit 36 outputs this information to the microprocessor 11 and the buffer circuit 15 via the buffer circuit 15.

Returning to FIG. 17, description will be continued. In the state S3 ', if a competitive loss occurs, the next transmission cannot be performed, so that the competitive loss occurs and the state shifts to the state S3 in the receiving state described above, and then the receiving state starts.

FIG. 29 is a logic circuit diagram of the competition loss detection circuit 21. H during transmission and when the value of status counter 19 is 3 or 4
The (“1”) signal is applied to the AND circuit. The received data ▲ ▼ and the received data SO are added to the EOR circuit, and the output is added to the AND circuit. When the transmission is in progress, the state counter 19 is 3 or 4, and the received data and the transmitted data are different, a competing loss signal is added to the status register (STR1) 31 from the AND circuit and stored. While the competition is detected by such an operation, on the other hand, when the competition loss does not occur, the state shifts to the state S4 ', and the self-address period starts. In the self-address period, the self-address of the apparatus is transmitted when the self-address to be transmitted, for example, the circuit of FIG. 3 transmits. Even during the self-address period, the same contention loss as described above may occur. For example, if a plurality of devices having the same level of priority code are present in one home bus, they compete with each other during the priority code period, but each device does not lose the competition. Therefore, the conflict must be detected again in the self-address period. Since there are no two identical addresses on one home bus, this self-address detection can completely detect the conflict. The detection of this competition is similar to the operation described above, and is performed by the competition loss detection circuit 21. When a competition loss occurs in this state S4 ', the state S4 of the reception state described above is obtained.

On the other hand, when no contention loss is detected, the next state is the state S5 'in which the partner address to be transferred is sent, that is, the partner address period. When the transmission of the other party's address is completed, the control code and the message length code are sequentially sent in the control code period (state S6 ') and the message length code period (state S7'). After that, the data, that is, the information is transmitted. This data is sent during the data period (state S8 '). The data transmission (state S8 ') is the same as the data reception (state S8), and a short message interruption may occur from another device. When this short telegram interrupt occurs, the short telegram interrupt detection circuit 22 detects it as in the reception state, and the state counter 19 is set to zero. That is, at this time, the state becomes S0. When the data ends in the data period (state S8 '), the check code period (state 9') comes next and the check code is sent. Then, after the dummy code period (state S10 '), the ACK / NAK period starts, and the ACK or NAK signal from the receiving device is received, and the state becomes S0.

All the changes in the count value of the state counter 19 described above are made by the data edge signal from the edge detection circuit 17.

If the conditions are not satisfied, it may not change.
For example, in the data period (states S8, S8 '), there is no change until all the data is completed or a short message interruption occurs. Further, the period of the state 1 is detected by the timer 38, and when the time-over signal is applied to the state counter 19, the state counter 19 changes. The timer 38 is added to the transmission control unit 33, and the transmission control unit 33 starts transmission control by the time-out signal input from the timer 38.

The packet status register 39 is a circuit to which the parallel output of the RX shift register 23 is added, and is a circuit for detecting what kind of packet status is being transmitted / received, and there are individual, broadcast, short message, synchronization recovery, etc. states, This state is the sleep counter
It joins the state counter 19 via 18, and the state counter 19 changes corresponding to this state. 12 to 15 are operation explanatory diagrams of the state counter at the time of individual, broadcast, synchronization recovery period, and ACK / NAK error. The state counter 19 sequentially changes to 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 at any time. In each of FIGS. 3 to 9, the bus data sequentially changes to a priority code, a self address partner address, a control code message length code, data (information), and a check code. When the synchronization recovery period is individual, there are dummy code periods and ACK / NAK periods at 10 and 11. The synchronization recovery period is a period during which the device of this embodiment is performing synchronization recovery. During this period, the bus data changes sequentially, and this bus data is, for example, data transfer between other devices. Incidentally, there is no transfer between other devices, no data is transferred, and the bus data may not change. On the other hand, at the time of broadcasting, it is “0” after the check code period. This is ACK /
This is because it is not necessary to send the NAK signal. At this time, there is no dummy code period and ACK / NAK period, and the value after 9 is 0. When an error occurs during the ACK / NAK signal, the state of the state counter 19 does not change from 10 but directly changes from 10 to 0.

The parallel output of the RX shift register 23 is added to the message length counter (MLC) 50, and the status register is displayed in the receiving state.
It is a counter that takes in the parallel output of the RX shift register 23 when 19 is 7 (state S7) and decrements every time one data, that is, information is received by the device S8. For example, this message length counter (ML
C) By reading the contents of 50, you can see how many more received data should be received. FIG. 28 is an operation explanatory diagram of the bus data and the message length counter (MLC) 50.
When n is received in the message length data, the message length counter (ML
C) 50 is loaded with n, and thereafter, in state S9, it is decremented by -1 each time data is sequentially received, and becomes 0 when this code is received.

In the transmit operation, the microprocessor 11 writes data to the transmit data register (TXDR)
RDY falls and preparations for transmission are completed (Fig. 19). At this time, if the SMI flag is set, long telegrams can be transmitted sequentially by interruption. Then, when the transmission becomes possible, the transmission is automatically started (No. 19
Figure). After that, TXRDY flag and INTR flag are "1".
Then, an interrupt is generated to request the next transmission data (self address) from the microprocessor 11 (Fig. 19).
After that, writing of transmission data is repeated in the same manner. When the data being transmitted becomes a check code, transmission / reception for the next one character (dummy code) is stopped (Fig. 19) ACK / NA
Send and receive K. The delivery of the transmission data to the microprocessor 11 ends when the last character in the data section is transmitted (FIG. 19). When data is written to TXDR after this, it becomes the first character (priority code) of the next packet.

Since the receiving operation is performed at the same time as the transmitting operation, an interrupt due to input may occur after transmitting the "priority code" (Fig. 19).

On the other hand, as shown in FIG. 20, the transmission operation in the synchronous communication is the same as that in FIG. 19 except that ACK / NAK is not received separately from the individual transmission. The reception operation starts when data is received. After receiving one character, RXRDY flag and INTR flag become "1" and interrupt I
RQ is generated to prompt the microprocessor 11 to input data. Since the received data is passed to the microprocessor 11 after receiving one character, the first character (priority code) is received by the microprocessor when MDR = 4 (FIG. 21). Then, the last data will be received when MDR = 0 (Fig. 21). Also, although ACK / NAK is transmitted using AKR, no special register is prepared for reception and RXDR is used like other data. In addition, the judgment of the broadcast and long telegram is made by the "priority code" as shown in Fig. 22.
Done by. As shown in FIG. 23, the receiving operation in the broadcast communication is the same as that in FIG. 21, except that the ACK / NAK transmission is eliminated from the individual reception.

For ACK / NAK transmission operation, the output of ACK / NAK is provided with a dedicated register as described above, and normally ACK / NAK is output after inputting the check code.
This is done by setting data in the NAK transmission register (AKR) (Fig. 21). Also, if data is being sent or received, it will be sent no matter which time it is set. (However, in the case of broadcast and short message interruption, it is not sent even if data is set in advance.

During the operation during the sync recovery period, the sync recovery period starts when the reset flag (RES) is changed from "0" to "1" (when reset is released) and when a data reception error or write lost data error occurs. At this time, the transmission / reception interrupt mask flag is set to "0", and no interrupt is generated for the mimlo processor 11. These flags become "1" at the end of the synchronization recovery period and generate an interrupt. Also, transmission is not performed during the synchronization recovery period.

Also, the status counter (MDR) is "0" →
Operates as “2” (When data comes in when the status counter (MDR) is “0”, the data is received but not recognized as a packet and a data reception error (RDE) occurs. The status counter (MDR) When data comes in at the time of "2", the data is received and the synchronization recovery operation is performed.)
(1) The synchronization recovery period ends when one packet of a normal packet (parity error (PE) is not generated) is received or (2) there is no data on the bus for 10 ms + 22 bits. However, if a parity error (PE) occurs in (1), the packet is treated as being out of synchronization, and the synchronization recovery period continues (1),
This period continues until either of the two conditions of (2) is satisfied. In the embodiment of the present invention, data reception error (RDE), write lost data error (WLD), read lost data error (RLD), framing error (F
E), parity error (PE), ACK / NAK error (AKE) 6
Is being detected. When a framing error (FE) or parity error (PE) occurs, the flag is set to "1" to notify the error to the microprocessor 11 by an interrupt. Then, the receiving operation continues as it is.

The write lost data error (WLD) and the read lost data error (RLD) are checked at the time of transmitting / receiving the next data, and the flag is set to "1" to notify the microprocessor 11 of the error by an interrupt. In the case of a read lost data error (RLD), the receiving operation continues, but in the case of a write lost data error (WLD), the transmitting operation is stopped and the above-mentioned synchronization recovery period starts.

When a data reception error (RDE) occurs, set the flag to "1" to generate an interrupt and at the same time set the status counter (MDR) to "0".
The sync recovery flag (DRE) is set to "1" to enter the sync recovery period.

When an ACK / NAK error occurs, set the flag to "1" to generate an interrupt. When this error occurs, the status counter (MD
R) changes from “10” → “10” → “0”. Ie ACK / NAK
When is not detected, the period of MDR = 10 becomes 22 bits.

In either case of error flag, it is read when the status register (STR2) 29 is read or when the status counter (MDR) becomes "1" or when the status counter (MDR) becomes "2" during the synchronization recovery period. It becomes 0 ".

On the other hand, factors of interruption to the microprocessor 11 include input of transmission data, output of reception data, short message interruption, loss of contention, and error.

The detection of the interrupt factor can be judged by the TXRDY flag, the RXRDY flag, the short message interrupt flag, the contention loss flag, the error flag, or the status register (STR2) 29. Further, the interrupt reset can be reset by reading the interrupt flag by any factor.

In the embodiment of the present invention shown in FIG. 3, the edge detection circuit 17 is a circuit for detecting a data edge, that is, a start bit. This circuit defines the start bit detection range and its width to remove noise and indicates a data reception error for an erroneous message.
FIG. 24 is a circuit diagram of the start bit detecting circuit, that is, the data edge detecting circuit 17. If this circuit is divided by function, the position detection range of the start bit and the width detection range of the start bit are respectively determined, and it is determined whether the start bit is within the range. The received signal ▲ ▼ is added to the fall detection circuit 40 and the rise detection circuit 41. Fall detection circuit 40 and rise detection circuit
The output of 41 is added to the pulse width detection counter 43, and the pulse width detection counter 43 starts the counting operation from the fall of the received signal to the rise thereof and counts the number of master clocks. Then, the count number in the meantime is added to the range / pulse width comparison circuit 42. FIG. 25 is an explanatory diagram of the start bit width detection range. The start bit is defined as a range of 52 μsec + 39 μsec, −11.2 μsec after the fall, and the range / pulse width comparison circuit 42 sets the start bit to fall within this range. Then, the start bit is valid, that is, output as a data edge detection signal. The start bit valid signal is also added to the start bit detection range count 44.When the start bit becomes valid, the count operation is started, and when the count value of the specific range is reached, the signal indicating that range Width comparison circuit
Add to 42. The detection output of the fall detection circuit 40 is applied to the range / pulse width comparison circuit 42, and the range / pulse width comparison circuit 42 outputs the detection signal from the fall detection circuit 40 from the start bit detection range counter 44. It is detected whether the range is the range indicated by the start bit valid range indication signal. If instructed, the pulse when the fall is detected from the fall detection circuit 40 is added as H, and if the signal that becomes H at the time indicating the range is added from the start bit detection range counter 44, the range / pulse The width comparison circuit 42 calculates the AND logic of the two signals, and outputs the start bit valid signal when the result is "H" and the pulse width is within the specified value. The start bit valid range described above defines the range of the position where the start bit falls, and as shown in Fig. 26, the start bit falls within ± 13 μsec from the position where it should be input. It is valid. Further, the detection of the start bit is not all data, but is in the range of X1 to X9 as shown in FIG.

By the above start bit detection circuit, noise is prevented and the data reception error flag is turned on for an erroneous message, thereby improving the effectiveness of the data.

〔The invention's effect〕

As described above, according to the present invention, since the time to send the acknowledge data is obtained, and the acknowledge data is selected and sent, the processing of the microprocessor is small, and the DMA
Acknowledgment data can be transmitted even during processing such as. Further, since it is an acknowledge buffer, if it is the same as the time of transmitting the acknowledge data, not acknowledge or other information can be automatically transmitted as well, and the same effect can be obtained.

[Brief description of drawings]

1 is a block diagram of the present invention, FIG. 2 is a system configuration diagram of the present invention, FIG. 3 is a bus control circuit, FIG. 4 is a data configuration diagram, FIG. 5 is ▲ ▼, ▲ ▼ data, and 6th. Fig. 7 is a transmitter circuit diagram, Fig. 7 is a register (TXDR / AKR) configuration diagram, Fig. 8 is a register CCR (mode 1) bit configuration diagram, and Fig. 9 is a register CCR (mode 2) bit configuration diagram. FIG. 10 is a bit configuration diagram of the status register STR1, FIG. 11 is a bit configuration diagram of the status register STR2, FIG. 12 is an explanatory diagram of the operation of the status counter at the time of individual, and FIG. 13 is an operation of the status counter at the time of broadcasting. Explanatory diagram, FIG. 14 is an explanatory diagram of the operation of the state counter during the synchronization recovery period, FIG. 15 is an explanatory diagram of the operation of the state counter at the time of an ACK / NAK error, FIG. 16 is the state counter value and its state chart, and FIG. Fig. Is a state transition diagram, Fig. 18 is an explanatory diagram of competition, Fig. 19 is a data transmission operation chart, Figure 20 is data transmission operation (broadcast), Figure 21 is data reception operation, Figure 22 is long telegram, broadcast condition chart, Figure 23 is data reception operation (broadcast), Figure 24 is start Bit detection circuit diagram, Fig. 25 is an explanatory diagram of the start bit width detection range, Fig. 26 is an explanatory diagram of the start bit position detection range, Fig. 27 is an explanatory diagram of the start bit position detection range, and Fig. 28 is a telegram. FIG. 29 is a diagram illustrating the operation of the long counter, FIG. 29 is a logic circuit diagram for losing competition, and FIG. 30 is a logic circuit diagram for interrupting a short message. 1 ... Transmission buffer, 2 ... Acknowledge buffer, 3
……selector.

Claims (1)

[Claims] 1. In a system for transmitting / receiving data via a bus and transmitting an acknowledge signal to a transmitter when the data is received, a transmission buffer (1) for storing at least one data to be transmitted, and an acknowledge signal An acknowledge buffer (2) for storing, and a selector (3) for switching the selection of the output of the transmission buffer (1) to the output of the acknowledge buffer (2) when a signal for detecting the timing of transmitting the acknowledge signal is added. A bus control circuit comprising: