JPH0746121B2 - Skiyan test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to an LSI including a plurality of scan chains and a combinational circuit connected and arranged in each of the scan chains or between adjacent scan chains. By having the scan chain switching means at the adjacent points of, one scan chain and a part of another scan chain are connected to each other to form a new scan chain, so that only scan-in / scan-out for one scan chain is required. , A scan test device that enables testing of combinational circuits connected and arranged between adjacent scan chains.

[Industrial application field]

The present invention relates to a scan test method for an LSI including a plurality of scan chains and a combinational circuit.

[Prior Art] A circuit (sequential circuit) forming an LSI is usually composed of a delay circuit composed of a flip-flop circuit and a combinational circuit connected thereto.
There is a configuration in which a plurality of flip-flop circuits are cascaded in a chain form, and the input / output terminals of each flip-flop circuit are connected to a combinational circuit. The above chain is called a scan chain, but as the number of LSI gates increases, the number of flip-flop circuits also inevitably increases. Therefore, when there is only one scan chain for one LSI, it takes a long time to set a predetermined value in all the flip-flop circuits connected in cascade, and the flip-flop circuits at positions that are not necessary need to be set. Had to set a value, and there was redundancy.

Therefore, a method has been proposed in which the above waste is eliminated by dividing the scan chain into a plurality and reducing the number of flip-flop circuits per chain.
FIG. 4 shows a conventional example of the above method. That is, LSI1
A plurality of flip-flop circuits FF1 ', FF2', FF3 ', ...
.. and a plurality of scan chains 2 to 5, each of which is connected to the input / output terminal of the flip-flop circuit of each scan chain
9 are arranged, and the combinational circuits 10 to 14 are similarly connected and arranged between adjacent scan chains. And
By inputting a predetermined signal from each of the scan-in terminals 15 to 18, a predetermined operation is performed in each of the above circuits, and an output signal is output from each of the scan-out terminals 19 to 22.

Now, in the case of testing the LSI 1 having the above configuration, if it is desired to test the combinational circuits 6 to 9 in each scan chain, a predetermined test signal sequence is input to the scan-in terminal of the corresponding scan chain to scan. The test is performed by observing the signal train output from the OUT terminal. For example, in FIG. 4, when it is desired to test the combinational circuit 6, a predetermined test signal sequence is input to the scan-in terminal 15 of the scan chain 2 and the signal sequence output from the scan-out terminal 19 is observed. Good.

[Problems to be solved by the invention]

However, in the above conventional method, a combinational circuit (10 to 14 in FIG. 4) connected and arranged between adjacent scan chains.
When performing the above test, scan-in / scan-out must be performed on at least two scan chains. For example, since the combinational circuit 12 shown in FIG. 4 is connected across four scan chains 2 to 5, scan in / scan out are performed on each of the four scan chains 2 to 5, and each result is The test cannot be done without complicated comparison. As described above, in the above-mentioned conventional method, there is a problem that the test of all combinational circuits cannot be performed only by scan-in / scan-out for one scan chain, and the test processing operation becomes complicated. Was.

In order to solve the above-mentioned problems, the present invention has scan chain switching means at adjacent points of different scan chains, thereby forming a new scan chain surrounding a combinational circuit at an arbitrary position. Therefore, it is an object of the present invention to provide a scan test apparatus that enables all combinational circuits to be tested only by scan-in / scan-out for one scan chain.

[Means for solving problems]

The present invention has a basic configuration shown in FIG. 1 in order to solve the above problems. That is, a plurality of scan chains 24 to 27 composed of a plurality of flip-flop circuits FF1, FF2, FF3, ... Arranged in a chain and connected and arranged in each scan chain or between adjacent scan chains. The LSI 23 constituted by the combinational circuits 28 to 36 has scan chain switching means 37 to 40 between adjacent scan chains. Each scan chain has scan-in terminals 41 to 44 and scan-out terminals 45 to 48.

[Action]

In each of the above means, during normal operation, the scan chain switching means 37-40 are switched so that the scan chains 24-27 are independently connected. In contrast, LSI2
When performing the test of 3, the combinational circuit 28 that constitutes the LSI 23
Of the scan-in terminals 41 to 44, the scan chain switching means 37 to 40 are switched so that a new scan chain surrounding the combinational circuit to be tested is formed. A test signal string is input from the terminal and the signal string output from the corresponding scan-out terminal among the scan-out terminals 45 to 48 is observed. As a result, it becomes possible to form one scan chain surrounding all the combinational circuits 28 to 36, and the test of each combinational circuit 28 to 36 is performed by the corresponding 1
It can be performed only by scan-in / scan-out for one scan chain.

〔Example〕

 Hereinafter, examples of the present invention will be described in detail.

{Structure of Embodiment of the Present Invention (FIGS. 1 and 2)} First, the basic structure of the embodiment of the present invention is the same as that described with reference to FIG. FIG. 2 is a specific circuit configuration diagram of the scan chain switching means 37-40 of FIG. In FIG. 2, 49 corresponds to 37 to 40 in FIG. 1, and the first scan chain 59 and the second scan chain 60 are the scan chains in the scan chain switching circuit 37 of FIG.
24 corresponds to 24 and 25, 38 also corresponds to 24 and 26, 39 corresponds to 26 and 27, and 40 corresponds to 25 and 27.

In FIG. 2, the positive logic of the switching signal 58 is input to the AND circuits 50 and 51, and the negative logic of the switching signal 58 is input to the AND circuits 52 to 55. Then, by applying a high level signal as the switching signal 58, the AND circuit 5
0 and 51 are turned on, AND circuits 52 to 55 are turned off, the input side of the first scan chain 59 is connected to the output side of the first scan chain 59 via the AND circuit 50 and the OR circuit 56, and The input side of the second scan chain 60 is connected to the output side of the second scan chain 60 via the AND circuit 51 and the OR circuit 57. Conversely, by applying a low level signal as the switching signal 58, the AND circuits 50 and 51 are turned off and the AND circuits 52 to 55 are turned on, and the input side of the first scan chain 59 is connected to the AND circuits 55, 54 and OR. Contrary to the above, it is switch-connected to the output side of the second scan chain 60 via the circuit 57, and the input side of the second scan chain 60 is different from the above via the AND circuits 53 and 52 and the OR circuit 56. Conversely, it is switched and connected to the output side of the first scan chain 59.

The switching signal 58 can be input from the outside of the LSI 23 for each scan chain switching means, which is not particularly shown in FIG.

{Operation of the Embodiment of the Present Invention (FIG. 3)} Next, the operation of the above embodiment will be described. First, the first
Of the tests of the combinational circuits 28 to 36 of the LSI 23 in the figure, when performing the tests of the combinational circuits 28 to 31, a high level signal is used as the switching signal 58 (FIG. 2) in the scan chain switching means 37 to 40. Input. As a result, the respective scan chains are connected as shown by the solid line in FIG. And, corresponding to each combinational circuit 28, 29, 30, 31,
Scan in / out terminals 41 and 45, 42 and 46, 43 and 47,
And 44 and 48 may be used to perform each test.

On the other hand, when each test of the combinational circuits 32 to 36 in FIG. 1 is performed, a low level signal is input as the switching signal 58 (FIG. 2) in the scan chain switching means 37, 38 and 40, and scanning is performed. The switching signal 58 of only the chain switching means 39 is set to the high level. As a result, a new scan chain shown by the solid line in FIG. 3B is formed. Then, corresponding to each combinational circuit 32, 33, 34 (36), 35, each test is performed by using each scan-in / out terminal 41 and 46, 43 and 45, 44 and 47, and 42 and 48. Good.

In the above case, the combinational circuits 34 and 36 are tested at the same time, so if you want to test only the combinational circuit 36,
Switching signal 58 in the scan chain switching means 39
By setting (FIG. 2) to the low level, the scan chain shown by the solid line in FIG. 3 (c) is formed, and the test can be performed using the scan-in / out terminals 44 and 47.

〔The invention's effect〕

According to the present invention, by having the scan chain switching means, it becomes possible to form a new scan chain surrounding all combinational circuits.
This makes it possible to test all the combinational circuits only by scanning in / out with respect to one scan chain. As a result, the number of patterns of the test signal sequence for testing the combinational circuit can be significantly reduced, and the LSI test time can be shortened and omitted.

[Brief description of drawings]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a circuit configuration diagram of scan chain switching means, and FIGS. 3 (a), (b), and (c) are operation explanations of an embodiment of the present invention. FIG. 4 and FIG. 4 are configuration diagrams of a conventional example. 23 ... Large-scale integrated circuit (LSI), 24-27 ... scan chain, 28-36 ... combinational circuit, 37-40 ... scan chain switching means.

Claims (1)

[Claims] 1. A flip-flop circuit (FF1, FF2, FF3, ...) Arranged in a chain form, comprising scan-in terminals (41-44) and scan-out terminals (45-4).
8) each with multiple scan chains (24-2
7) and a combinational circuit (28 to 36) connected and arranged in each scan chain or between adjacent scan chains
A scan chain that is arranged between adjacent scan chains in a large-scale integrated circuit (23) configured by and connects a part of the first scan chain and a part of the second scan chain to form a new scan chain. A scan test apparatus having switching means (37-40).