JPH0746336B2 - Change detection circuit for multiple channels - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-channel data change detection circuit for detecting whether or not a change has occurred in each input data of a large number of data channels.

B. Summary of the Invention The present invention is a circuit for detecting a change in each input data of a large number of data channels, in which input data of each data channel is alternately written to two memories provided in parallel to input all channels. By reading the data stored in the two memories and comparing them with each other after the writing of the data is completed, the wasteful processing time of the data processing means such as the computer is saved and the reduction of the efficiency is prevented.

C. Conventional technology Conventionally, a data processing system equipped with a large number of slave stations or terminal devices sequentially captures input data from each terminal, and if there is a change in this input data, sends a control signal to the corresponding terminal to perform the required control. There are some that are designed to do.

Specifically, each terminal captures, transfers this data to the memory by direct memory access (DMA), sequentially compares the previously captured data with the data processing means, and finds that the mismatched data If there is a mismatch, it is detected that the terminal of the data that has not matched is changed, and the required control is performed for this terminal.

D. Problems to be solved by the invention However, in the case where the input data previously captured by the data processing means and the input data newly captured this time are sequentially compared by each terminal as described above, Since the data processing means is occupied for this simple data comparison, there is a problem that the efficiency of data processing is reduced.

E. Means for Solving the Problems In the present invention, a first memory and a second memory having addresses respectively corresponding to a plurality of data channels, and respective addresses of the first memory and the second memory are sequentially and cyclically designated. A channel counter, and a data selector which selects the input data of the data channel corresponding to the content of the channel signal by the channel signal output from the channel counter and supplies it to the data inputs of the first memory and the second memory. A cycle counter that counts the number of repetitive operations of the channel counter and outputs a write signal for alternately writing input data to the first memory and the second memory, and data to the first memory or the second memory. Each channel read from these memories after writing is completed Comparing the data in the same channel each other, and mismatch detection circuit for detecting data to be mismatched, and a multiplexer for selectively outputting the latest input data of the mismatch and Natsuta data,
A buffer circuit for storing the output data of the multiplexer together with the signal indicating the unmatched channel is provided.

F. Operation Input data of all channels are written alternately in the first and second memories. After the writing is completed, the stored data of each channel are sequentially read and compared with each other in the same channel. As a result, if there is a mismatch, the latest input data among the data that causes this mismatch is stored in the buffer circuit together with the data indicating the channel.

G. Embodiment FIGS. 1A and 1B are circuit diagrams showing an embodiment of the present invention, in which two random access memories (hereinafter, RA) are shown.
M) 1 and 2 are provided in parallel. The RAMs 1 and 2 have addresses equal to the number of data channels, and the addresses corresponding to the respective data channels are sequentially designated by the cyclic channel signal CH output from the channel counter 3, and in the write mode. Input data Din is written to the specified address. Further, the stored data at the designated address is read in the read mode.

The channel signal CH of the channel counter 3 designating each channel of the data channel is input to the cycle counter 4, and the number of repetitions is counted from the first channel to the k-th channel as one channel cycle. The channel signal CH is also input as a select control signal of the data selector 5 of FIG. 1 (B), and the k-channel input data Dk input to the data selector 5 is sequentially selected for each channel, and the RAM1 , 2 is supplied as input data Din.

Here, the cycle counter 4 writes the write signal WR only to the RAM 1 when the count value q of the channel signal CH is q = m.
1 is output, the write signal WR2 is output only to the RAM2 when q = m + 2, and the read enable signal REB is output when q = m + 1.

Therefore, n- of the addresses for k channels of RAM1 and 2
Considering 1 to n + 2 addresses, the channel signal
In the mth cycle of CH, the input data Dk of each channel is written in RAM1 as shown in FIG. 2 (A), and in the m + 2th cycle, it is written in RAM2 as shown in FIG. 2 (B). . Then, at the next m + 1 cycle after the writing of the input data Dk to BAM1 is completed, as shown in FIG.
And the data stored in RAM2 are simultaneously read in the same address unit. That is, the input data Dk of all channels are alternately written to the RAMs 1 and 2 in each cycle of the channel signal CH, and in the next cycle after the end of writing (the cycle in which the channel signal CH makes a cycle), the data of RAM1 and RAM2 Stored data is read simultaneously in the same address unit (that is, in the same channel unit).

In this way, the data Dk of each channel read out from the RAM1 and RAM2 in a time division manner is latched to the latches 6A and 6B by the read enable signal REB, and then the mismatch detection circuit 7 of FIG. Are input in parallel to the multiplexer 8. At this time, the mismatch detection timing signal DET obtained by delaying the read enable signal REB by the delay circuit 11 by the predetermined time τ is input to the mismatch detection circuit 7. As a result, the mismatch detection circuit 7 compares the input data Dk of the mth cycle and the input data Dk of the mth-2th cycle, which are input from the latches 6A and 6B, with respect to the same channel, at the input timing of the signal DET. , It is detected whether the two do not match. As a result of this detection, if there is a mismatch, the detection circuit 7 outputs a mismatch detection signal NEQ.

The non-coincidence detection signal NEQ is input to the interrupt control circuit 9 and also to the buffer 10 formed of the FIFO as a write signal.

The buffer 10 receives the output data Dk of the latch 6A or the latch 6B via the multiplexer 8 and the channel signal CH from the channel counter.

At this time, the latest input data is input to the multiplexer 8.
Selection signal S for selecting read data Dk of RAM in which Dk is written
EL is given from the cycle counter 4. Figure 2 (A)
In the example, the latest input data Dk was written to RAM1, so RA
A selection signal SEL for selecting the read data Dk of M1 is given to the multiplexer 8.

Therefore, when the non-coincidence detection signal NEQ is output from the non-coincidence detection circuit 7, the latest input data Dk of the non-coincidence channel is written in the buffer 10 together with the channel signal CH indicating the channel number.

As a result, the latest input data Dk of the channel in which the previously input input data Dk ₁ out of the input data Dk of the k channel and the newly input input data Dk do not match in the buffer 10 are the channel signal CH. Will be stored with.

On the other hand, the interrupt control circuit 9 sends the mismatch detection signal NEQ.
Is input, an interrupt request INT / RQ is sent to the external device.
To supply. Then, the read signal RD is input from the external device to read the data Dk and the channel signal CH written in the buffer 10, and the data Dk and the channel signal CH are transferred from the buffer 10 to the external device.

The buffer 10 outputs the signal RDOK for prohibiting the reading of data to the external device after the mismatch detection signal NEQ is input and until the writing of the data is completed, and releases the signal RDOK when the writing is completed. .

In the time chart of FIG. 2 (A), a new input data D is input to the RAM1 by the write signal WR1 in the mth cycle.
It shows that k is written, and that the input data Dk written in the (m−2) th cycle is held as it is in the RAM2. Further, in the time chart of FIG. 2C, the data stored in RAM1 and RAM2 are simultaneously read in the (m + 1) th cycle, the input data of the nth channel among the read data do not match, and the buffer 10 is written. It is rare. The time chart of FIG. 2B shows that the latest input data Dk is written in the RAM2.

Since the buffer 10 is composed of a FIFO, if there are many mismatched channels of the input data Dk, the latest input data Dk of the channels that do not match are stored in order,
It is sequentially read by an external device.

H. Effect of the Invention As is apparent from the above description, according to the present invention, after writing data of a large number of channels alternately in two RAMs, data of the same channel are compared with each other, and if there is a discrepancy, Since this is transmitted to the external device, it is not necessary for the data processing means such as the computer to perform a simple data collating process, and the efficiency of the data processing means can be prevented from being lowered. The present invention becomes more effective as the number of channels increases.

[Brief description of drawings]

1 (A) and 1 (B) are circuit diagrams showing an embodiment of the present invention, and FIGS. 2 (A) to 2 (C) are time charts for explaining the operation of the embodiment. 1,2 ... RAM, 3 ... Channel counter, 4 ... Cycle counter, 5 ... Data selector, 6A, 6B ... Latch, 7 ... Mismatch detection circuit, 8 ... Multiplexer, 9
...... Interrupt control circuit, 10 ... buffer.

Claims (1)

[Claims] 1. A first memory and a second memory having addresses respectively corresponding to a plurality of data channels, a channel counter for sequentially and cyclically designating each address of the first memory and the second memory, and the channel counter. A data selector for selecting input data of a data channel corresponding to the contents of the channel signal by the channel signal output from the data selector and supplying the data input to the first memory and the second memory, and a channel signal of the channel counter At the same time, the number of repetitions from the first channel to the kth channel as one channel cycle is counted, and at the mth cycle of the channel signal, a signal for writing the input data of each channel to the first memory is output, M +
A cycle counter that outputs a signal for writing the input data of each channel to the second memory in the second cycle and a read enable signal in the next m + 1 cycle after writing the input data to the first memory, and When the cycle counter outputs the read enable signal, the first and second latch units in which the stored data in the first memory and the second memory are simultaneously read and latched in the same address unit, and the cycle counter outputs the read enable signal. Is supplied to the output, and a delay circuit for sending a mismatch detection timing signal obtained by delaying the signal by a predetermined time, and a mismatch detection timing signal sent from the delay circuit are provided. The second related to the same channel output from the 2 latch section When the mismatch detection circuit that compares the data of the cycle and the data of the (m−2) th cycle and detects whether or not the two data do not match and the mismatch detection signal sent from this mismatch detection circuit are given, a mismatch occurs. A change detection circuit for multi-channel data, comprising a buffer for storing the latest input data of the selected channel via a multiplexer together with a channel signal indicating the channel number.