JPH0746477B2 - Synchronous circuit - Google Patents

Description

The present invention relates to a PCM signal reproducing apparatus, and more particularly to a digital signal processing circuit suitable for use in a synchronizing circuit.

[Prior art]

In the conventional synchronizing circuit, as described in JP-A-58-139311, when a detection signal of a synchronizing signal is synchronized with a master clock generated inside the signal processing circuit, and this signal is detected within the detection window. With the detection signal of 1, the flag processing inside the synchronizing circuit and the synchronization or correction of each counter are performed.

However, for high-density recording, for example, in a system in which an 8-bit signal pattern is code-converted (digitally modulated) into a 10-bit signal pattern and then recorded, a predetermined 8 bits are counted during reproduction and 1 word Until the above, a counter that operates by the reproduced clock is required, and the correction process performed when the sync signal is lost or erroneously detected must be operated by the master clock inside the signal processing. Thus, no consideration was given to the case where it is necessary to simultaneously control the circuits operating with different clocks from one reference signal.

[Problems to be solved by the invention]

In the above-mentioned prior art, when a counter operating by a reproduction clock and a master clock generated in the signal processing circuit coexist in the synchronous circuit, each counter and a flag processing circuit for discriminating and selecting synchronization with these counters and correction processing are selected. No consideration has been given to the fact that the processing operation timing is asynchronous, and when performing the processing operation to each counter and flag processing circuit with the signal obtained by synchronizing the detection signal of the synchronization signal synchronized with the reproduction clock with the master clock. Due to the asynchronous timing, there is a problem that the processing for each counter does not correspond to the processing of the flag processing circuit, or a malfunction occurs such that the processing operation for all counters is not performed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronous circuit which solves the above problems and provides more faithful detection protection of a synchronous signal without malfunction.

[Means for solving problems]

The above-mentioned object is to control each circuit which operates by the reproduction clock by the detection signal of the synchronization signal detected in the detection window, and which is a signal which synchronizes this detection signal with the master clock and which operates by the master clock. And by controlling the flag processing circuit.

[Action]

Synchronized to the respective clocks only by the detection signal of the synchronization signal detected in the detection window, under the control of the counters and flag processing circuits that operate by the reproduction clock generated from the master clock and the reproduction signal inside the signal processing. There is no malfunction because it is controlled at the timing.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a circuit block diagram of a PCM reproducing device using a rotary head, and FIG. 2 is a recording signal format showing a structure of a data signal generated at the time of recording. In FIG. 2, 2 is a recording tape, and 24 is a track format diagram showing a signal structure of one track recorded during 90 ° when the rotary head contacts the tape. This one
The track configuration is such that the signal to be recorded is divided into a PCM area and subcode areas (SUB-1, SUB-2) as shown in (a), and is composed of signals ATF1 and ATF2 for tracking servo. In addition, the PCM area has 128 blocks, SUB1, SUB
Each 2 consists of 8 blocks. As shown in (b), the structure of one block consists of a sync signal S1 word, an information code ID 1 word, a block address BA 1 word, a parity code P 1 word and data W _{0 to} W ₃₁ 32 words in total of 36 words. Here, the ID is an information code provided for reproducing the recording mode such as the sampling frequency, the number of quantization bits, the tape speed, etc. at the time of reproduction. The block address BA is an address signal assigned to each block, and is assigned as "0 to 7F" in the PCM area, "80 to 87" in the SUB1 area, "88 to 8F" in the SUB2 area, and the highest order. The bit of "0" becomes the PCM area and "1" becomes the subcode area. Also, the parity code P is 2 of the above-mentioned ID and BA.
It is a simple parity code generated by adding modulo 2 to each bit of a word. The data W _{0 to} W ₃₁ is composed of a PCM signal input during recording or a code for error correction. The configuration and operation of this embodiment for reproducing the signal thus recorded will be described below.

FIG. 1 shows a rotary cylinder 2 with a magnetic head attached.
Is a magnetic tape, 22 is a reproduction amplifier, 21 is a rotation system, a tape traveling system and a servo circuit for tracking, 10 is a circuit for generating timing necessary for operating each circuit of the reproduction system, and 23 is an oscillator. . The reproduction signal read from the magnetic tape is synchronized in word units by the synchronization circuit 3 by detecting the synchronization signal and protection when the synchronization signal is lost, and is demodulated by the demodulation circuit 4. The parity added at the time of recording is checked from the demodulated data by the parity check circuit 5, and the block address and the ID code are latched by the address latch circuit 6 and the ID code latch circuit 7.
The reliability of the latched ID code is further checked by the ID code detection circuit 8, and the required timing is changed by discriminating the current reproduction mode such as sampling frequency or tape speed. The result of the parity check is used as one factor for evaluating the reliability of the detected sync signal and the block address for the detection protection of the sync signal and is one condition for the block address detection protection in the address circuit 9. Further, by comparing the size of the fetched block address BA with a memory access address CA for error detection and correction processing, which will be described later, control is performed so that the corrected data on the memory is not rewritten due to erroneous detection of the address. Further, when the beginning of the data is dropped due to dropout or the like, the data to be written in the memory is set in order to suppress the probability of erroneous detection and erroneous correction in the error detection and correction processing (PRSET output). An address for writing the detected and protected block address in the memory is generated by the reproduction address generation circuit 17, and is written in the memory 12 (for example, RAM) via the interfaces 11 and 16 together with the demodulated data. The data written in the memory is then read by the correction address generation circuit 18, the correction circuit 13 detects and corrects an error and interpolates the data, and the data is written again in the memory. The output address generation circuit 19 reads the corrected data. The D / A conversion circuit 14 converts the analog signal and outputs the analog signal.

An embodiment of the synchronizing circuit according to the present invention will be described with reference to FIG. In the figure, the same reference numerals as in FIG. 1 have the same contents and the same functions. The synchronizing circuit is composed of 31 to 39 in the figure, 31 is a synchronizing signal detecting circuit for detecting a synchronizing pattern from a reproduced signal, 35 is various counters for generating and processing various flags for detecting and protecting the synchronizing signal, various counters 33, Flag processing circuit for synchronizing and correcting 34, 36, 38, 32 is a synchronizing circuit for synchronizing the sync signal detected by the reproduction clock with the master clock MCK by the internal crystal, 33 is one word by the reproduction clock, for example 10 bits A bit counter that divides by frequency, 34 is a word counter that counts the number of data extracted from the reproduction signal in word units, 36 is a window counter for generating a synchronization signal detection window and various timing clocks, and 37 is the timing Decoder circuit for clock generation, 38 is 1 to protect the sync signal detection cycle
A block, for example, a counter for dividing and counting every 360 bits, 39 is a decoder circuit for generating a protected clock PCK. Further, in the figure, 41 is a conversion circuit for converting a serial signal reproduced at the time of reproduction into a parallel signal and a parallel signal modulated at the time of recording into a serial signal, 42
Is a latch circuit for fetching a reproduced signal in word units, 43 is a demodulation circuit, 45 is a latch circuit for latching demodulated data, and 44 is a demodulation error detection circuit for detecting a signal other than predetermined data as an error during demodulation. The sync signal DSYNC detected from the reproduction signal by the sync signal detection circuit 31 is compared with the detection window generated at a predetermined timing by the flag processing circuit 35, and the signal detected in the detection window is used as the BSYNC signal. Word synchronization is applied to the bit counter 33 and the word counter 34 that operate according to the reproduction clock. This BSYNC signal is synchronized with the reproduction clock, and a signal CSYNC is obtained by further synchronizing this with the master clock MCK by the internal crystal by the synchronization circuit 32.
To generate. Master clock MCK by this CSYNC signal
The window counter 36 and the protection counter 38 operated by the above are set to predetermined values. (SET0, SET1, SET3 signals) Further, the flag processing circuit outputs, for example, an error flag (EF signal) at the time of demodulation, a parity flag (P signal) which is a check result of a parity code added at the time of recording, and a detected block address value. An address flag (AD which is a comparison result of whether or not there is an appropriate value preceding the address for accessing the memory for performing the error correction processing shown in FIG. 1)
It is determined whether the BSYNC signal detected by a determination signal such as RF signal) is correct or erroneous, and only when it is correct, the counters 36 and 38 are set to predetermined values again (SET2 signal). In this way, the window counter 36 corrected on the basis of the detection synchronization signal DSYNC is decoded by the decoder circuit 37 to generate the ID code shown in FIG. 2 and the latch clocks IDCK and ADRCK of the block address BADR, and check the parity. The clock PTCK is generated at a predetermined timing, and the signal WD0 for opening the detection window, the signal WD1 for closing the window, and the NSYNC signal when the DSYNC signal is not detected in the detection window are generated by decoding. As shown in FIG. 2, this window counter divides the frequency by 360 or more, for example, 370 at the maximum when DSYNC is detected in a cycle consisting of 360 bits per block, and the detection window is ± 3. It has a bit length and when normal, DSYN at its center
The WD0 signal is set to 357 of the window counter to detect C.
Position is decoded and generated, and WD1 decodes and generates 363. Originally, BSYNC is detected at the position of 360, and CSYNC is further delayed by one clock in the synchronizing circuit, so 2 is loaded by the SET1 signal and the detection window is closed. Also
When BSYNC is not detected, the window counter does not receive the SET1 signal, and when it reaches 364 to continue counting, the WD1 signal is generated, the detection window closes, and when it reaches 367, for example, the NSYNC signal is generated. Then, the window counter keeps dividing by 360 by loading 8. In addition, the protection counter steadily keeps the frequency division of 360, which is the length of one block, and the flag processing determines the reliable detection synchronization signal and applies correction (SET0, S
ET2, SET3). Further, by decoding from this protection counter, a clock PCK in which the cycle of one block and its timing are protected is generated.

The feature of the present invention is that DSYNC is conventionally synchronized with the master clock MCK, and the window counter and protection counter are corrected or synchronized by BSYNC synchronized with MCK, and the bit counter and word counter are synchronized by other methods and circuits. Compare the DSYNC to the detection window as described above,
BSYNC which is synchronized with the reproduction clock is generated to synchronize the bit counter 33 and the word counter 34 which operate with the reproduction clock and to synchronize or correct the window counter 36 and the protection counter 38 which operate with MCK. Therefore, the synchronization circuit generates CSYNC that synchronizes BSYNC with MCK and controls the window counter and protection counter. That is, the bit counter, the word counter, the window counter, and the protection counter are simultaneously controlled for synchronization and correction depending on whether or not the BSYNC signal is detected. As a result, it is possible to reliably perform the synchronization processing for each counter by the detection of the synchronization signal and the flag processing operation of the flag processing circuit.

Next, a peripheral circuit diagram including an embodiment of the synchronizing signal detecting circuit and the synchronizing circuit of the synchronizing circuit according to the present invention is shown in FIG. 4, and its operation will be described in detail with reference to the timing chart of FIG. In the figure, the same signal names as in FIG. 3 are the same signals having the same functions, and 413 is the serial-parallel conversion circuit 4 in FIG.
1 is a shift register, 421 is a latch circuit,
The sync signal detection circuit includes gates 311 to 315 and a latch circuit 31.
6, the synchronizing circuit is composed of gates 321, 322, 324, 325, a shift register 323, and a latch circuit 326. Further, the gate 3571 and the latch circuit 3672 are a BSYNC detection circuit forming a part of the flag processing circuit 35 in FIG.
12 and the shift register 411 are part of a demodulation circuit that converts the NRZI-modulated reproduction signal into an NRZ signal. First, the reproduction signal (C) synchronized with the reproduction clock (B) is input from the input terminal 41A, and the NRZ-converted output signal of the gate 412 is sequentially captured in the shift register 413 (D). At this time, the reproduction signal is obtained by modulating 8-bit data into a 10-bit code. The sync signal "1100010001" or "0100010001" pattern is decoded and detected by the gates 311 to 315 (F) and latched (DSYNC ). This DSY
The gate 3571 compares the NC timing with the detection window, detects DSYNC generated in the detection window, and generates BSYNC. The BSYNC generated here is a signal synchronized with the reproduction clock, and by this, the bit counter 33 and the word counter 34 are synchronized ((P), BSET). This BSY
A set-reset flip-flop circuit composed of gates 321 and 322 is set by the NC (J), and this output is input to the shift register 323 whose shift clock is MCK and shifted (K) and (L). As a result, CSYNC synchronized with MCK is generated only when BSYNC is detected by the gates 324 and 325 and the latch circuit 326 operating with MCK (M),
(N). The window counter and the protection counter are synchronized or corrected by this CSYNC (SET1, SET3), and the latch clock SCK (Q) generated by decoding the bit counter synchronized in word units is used to further output 1 bit of (D). The reproduced data (E) thus shifted is latched in units of a predetermined 1 word and 10 bits shown in FIG. 2B (LT
H).

Here, the detection window is opened for 6 clocks from 357 to 362 of the window counter because the detection error of 1 clock due to synchronization and the DSYNC detection position due to timing jitter are about ± 0.5% of the normal position. This is to enable detection of misalignment of the
Open the window so that is detected in the center of the detection window. As a result, DS at the position shown in FIG.
BSYNC is generated only when YNC is detected, and synchronized CSYNC is delayed by one clock. Therefore, the SET1 and SET3 signals that synchronize and correct the window counter and the protection counter are delayed by one clock with respect to the signal BSET that synchronizes the bit counter. This signal is independent of whether CSYNC is inside or outside the detection window.
Set the window counter or protection counter to "2". If DSYNC is not detected in the detection window, BSYNC, CSYNC
Is not generated, and the SET1 and SET3 signals are not generated. Therefore, the window counter counts 363 or more, and when it reaches 367,
Generate NSYNC signal and load "8" (NSET). As a result, the 360-bit cycle, which is the length of one block, is maintained even when DSYNC is missing.

From the above, the recovered clock waits for timing jitter,
Even if the duty ratio is not guaranteed, each counter that operates with MCK and the recovered clock is reliably controlled only by BSYNC detected in the detection window, and whether BSYNC is detected or not Since they completely coincide with each other, the processing operation of the flag processing circuit controlled by CSYNC and the control of each counter can be completely corresponded to each other, and a more faithful detection protection of the sync signal without malfunction can be performed.

In FIG. 4, the serial-parallel conversion circuit 413
Input the serial-parallel control signal S / P from the input terminal 41C to serially input at the time of reproduction and parallel load the modulated data at a predetermined 10-bit cycle at the time of recording, and to load 9 bits until the next loading. By shifting and serially outputting the recording signal, it is possible to use it for both recording and reproduction.

〔The invention's effect〕

According to the present invention, the detection synchronization signal (BSYNC) detected within the detection window for controlling the plurality of counters and flag processing circuits inside the synchronization circuit that operates by the master clock inside the signal processing and the reproduction clock generated from the reproduction signal. Since it is possible to reliably control the timing at a timing synchronized with each clock by using only, it is possible to perform more faithful detection protection of the synchronization signal without malfunction.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment according to the present invention,
2 is a data format diagram of a recording signal, FIG. 3 is a circuit block diagram showing an embodiment of a synchronizing circuit according to the present invention,
FIG. 4 is a circuit diagram of an embodiment of the synchronizing circuit of the synchronizing circuit according to the present invention, and FIG. 5 is a timing chart showing the operation of the synchronizing circuit according to the present invention. 31 …… sync signal detection circuit, 32 …… synchronization circuit, 33 …… bit counter, 34 …… word counter, 35 …… flag processing circuit, 36 …… window counter, 38 …… flag processing circuit, DSYNC …… A signal that indicates the state where the sync signal is detected from the playback signal, BSYNC ... A signal that indicates the state that DSYNC is detected in the detection window, CSYNC ... A signal that synchronizes BSYNC with the master clock inside the signal processing circuit.

Claims (1)

[Claims] 1. Data comprising one word consisting of a plurality of bits is divided into units of a predetermined number of words, and a block synchronization signal is added to the predetermined number of words of data to form one block.
In reproducing a data recorded in the block unit, in a synchronizing circuit for detecting data in synchronization with the synchronization signal from a reproduction signal, a word of the data is generated by using a first clock synchronized with the reproduction signal. For generating a timing signal synchronized with
And a second timing signal generation circuit for generating a detection window signal that opens and closes near a predetermined timing at which the block synchronization signal should be detected using a second clock having a predetermined cycle, A detection circuit that detects the block synchronization signal by the first clock and generates a first synchronization detection signal when the detection window signal is open; and a detection circuit that converts the first synchronization detection signal into the second clock. A synchronization circuit that generates a synchronized second synchronization detection signal, wherein the first timing generation circuit generates timing based on the first synchronization detection signal, and the second timing generation circuit Is a synchronization circuit which generates timing with reference to the second synchronization detection signal.