JPH0746503B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a sense amplifier circuit therein.

(Prior Art and Problems Thereof) A typical well-known sense amplifier circuit is described in, for example, Nikkei Electronics (Jan. 8, 1979, pp.110-133). There is something. As shown in FIG. 3, this is composed of a precharge circuit composed of two field effect transistors (hereinafter simply referred to as transistors) T1 and T2 and a flip-flop circuit composed of two transistors T3 and T4. . In FIG. 3, B0 and B1 are bit lines, P0 is a precharge signal, PS is a clock signal, and CB is a parasitic capacitance of the bit line. Further, MC is a memory cell, which is composed of a transistor T00 and a cell capacitance CS as shown in FIG. 4, and w is a word line. Further, DC is a dummy cell, which is composed of transistors T10 and T11 and a dummy capacitor CR as shown in FIG. 5, and DW is a dummy word line. The operation of the conventional sense amplifier circuit will be described below by taking the case of using an N-channel MOSFET as a transistor as an example.

First, set the precharge signal P0 to high level and set the bit line B
0 and B1 are set to the power supply potential VD, and the node NR in the dummy cell DC is set to the reference potential.

Further, the clock signal PS is set to a high level in order to bring the transistors T3 and T4 forming the flip-flop circuit responsible for sensing and amplifying the minute signal into the non-conducting state. Next, the precharge signal P0 is set to low level and the bit lines B0, B
When the word line W and the dummy word line DW are set to the high level after the 1 and the node NR are set in the floating state, the transistors T00 and T10 become conductive, and the signals are read from the memory cells MC and the dummy cells DC to the bit lines B0 and B1. Be done. At this time, charge is distributed between the node NR set to the reference potential and the bit line B1 set to the power supply potential VD, and the bit line B1
Potential changes from VD to VD / (1 + CR / CB). Similarly, if the node NS of the memory cell MC is the reference potential, the potential of the bit line B0 changes from VD by VD / (1 + CS / CB), but if the node NS is the power supply potential VD, the memory cell MC is selected. Even if it is done, the potential of the bit line B0 is kept at VD and does not change. Here, in the normal dummy capacitor CR, VD / (1 + CR / CB) is VD and VD /
It is designed to have an intermediate potential of (1 + CS / CB). Further, since the cell capacitance CS and the dummy capacitance CR are much smaller than the parasitic capacitance CB of the bit line, the potential difference generated between the bit lines B0 and B1 is a minute potential difference of several hundred mV or less. A sense amplifier circuit amplifies the minute potential difference on the bit lines B0 and B1.

As described above, when the clock signal PS is set to the low level after the minute potential difference is applied to the bit lines B0 and B1, the bit line B0
The charge on the bit line is discharged through one of the transistors T3 and T4 so that the lower potential of 0 and B1 becomes lower and lower, and the minute potential difference between the bit lines B0 and B1 expands to a large amplitude signal. Become. For example, the internal node NS of the memory cell MC
Assuming that the potential of the power source potential is VD, the bit line B0
In addition, the bit line B1 is kept at the reference potential (0V). But,
Actually, the transistor T3 connected to the bit line B0 also becomes conductive for a moment during operation, so that some electric charge is discharged through the transistor T3. Further, due to the coupling between the bit lines B0 and B1 via the transistors T3 and T4 in the flip-flop section, the potential of the bit line B0 on the high potential side becomes lower than VD which is the precharge potential. For this reason, the voltage level at the time of rewriting the signal to the memory cell becomes insufficient, which causes a decrease in the operation margin and a malfunction.

Further, a circuit system as shown in FIG. 6 which is devised to compensate for the above-mentioned drawbacks is also considered (described in the conventional example of Japanese Patent Application Laid-Open No. 59-132492 (Japanese Patent Application No. 58-006002)). ing). This method uses bit line B0, B1 and coupling capacitor CC for boosting.
By inserting transistors T5 and T6 between the two, and controlling the conduction / non-conduction of the transistors T5 and T6 by the clock signal P2, the internal information is read from the memory cell MC onto the bit line and amplified by the sense amplifier circuit. Until then, the coupling capacitance CC is separated from the bit lines B0 and B1.

FIG. 7 shows the operation waveform.

As shown in FIG. 7, before the word line W and the dummy word line DW are set to the high level (time t1), the clock signal P2 is set to the low level to make the transistors T5 and T6 non-conductive, and the coupling capacitance CC
Is disconnected from the bit lines B0 and B1. Then, after the small signal read out on the bit line has a large amplitude (time t2), the clock signal P2 is set to the high level again to connect the coupling capacitance CC to the bit lines B0 and B1, and further lower the clock signal P1. By changing the level from the high level, the levels of the bit lines B0 and B1 are boosted and rewriting to the memory cell is performed.

If the level amplitude of the clock signal P1 is V1, the bit line capacity is CB, and the cell capacity is CS, the boosted level ΔV of the bit line obtained at this time is Becomes However, for this purpose, change the bit line level at time t2
When VT is the threshold voltage of VB and transistors T5 and T6,
As the high level potential V2 of the clock signal P2 (VB + ΔV + V
Level T or higher is required. This is because the bit line level is limited by (V2-VT).

As described above, in the second conventional example shown in FIG. 6, the coupling capacitance CC can be separated from the bit line when the information is read from the memory cell, and the level of the bit line can be boosted. Is limited by the high level potential V2 of the clock signal P2, and this level V2 is (VB +
There is a serious drawback that level boosting by coupling of the clock signal P1 via the coupling capacitance CC cannot be sufficiently performed unless it is equal to or more than ΔV + VT).

(Object of the Invention) An object of the present invention is to solve the above-mentioned drawbacks of the conventional example, and it is possible to rewrite the bit in the memory cell without increasing the capacitance on the bit line when reading the memory cell information. Provided is a semiconductor memory device which compensates for a drop in the voltage level of a line and does not require a special constraint such as the high level of the clock signal P2 shown in the second conventional example in the control signal therefor. There is a thing.

(Structure of the Invention) The present invention relates to bit lines forming rows, word lines forming columns, and
A memory cell selected by the word line to transfer information to and from the bit line, a sense amplifier having the bit line as an input / output signal line, and a coupling capacitor having one electrode connected to the bit line. A field effect transistor having a source electrode connected to the other electrode of the coupling capacitance, a first signal line connected to the drain electrode, and a second signal line connected to the gate electrode. Is turned on when the bit line is charged, turned off when information is read from the memory cell, and turned on again when information is rewritten to the memory cell, and the first signal line is turned on during this information rewriting operation. A semiconductor memory device characterized in that it is displaced from a first level to a second level, and is set to the first level again after completion of this information rewriting operation. That.

(Embodiment) FIG. 1 is a circuit diagram of a sense amplifier circuit showing an embodiment of the present invention, and the same reference numerals are used for the same portions as those of the conventional example of FIGS. 3 and 6 for convenience of explanation. . The difference between FIG. 1 and the above-mentioned conventional example, FIG. 3 and FIG.
The clock signal P1 is applied to each coupling capacitance CC through the transistors T5 and T6 whose conduction state is controlled by P2. All transistors are n-channel
It is a MOS transistor.

Next, the operation of the embodiment will be described. FIG. 2 is a timing chart of each signal for explaining the operation of this embodiment.

First, the precharge signal P0 and the clock signals P2 and PS are set to the high level, and the clock signal P1 is set to the first level, that is, the low level to set the bit lines B0 and B1 and the coupling capacitance CC to the power supply potential VD by the precharge transistors T1 and T2. , Transistors T5, T6
Charges nodes N1 and N2 to a low level. Next, the precharge signal P0 and the clock signal P2 are set to the low level to separate the bit lines B0 and B1 from the power supply to bring them into a floating state, and at the same time,
The connection points N1 and N2 of the coupling capacitance CC with the transistors T5 and T6 are also in a floating state. After that, as in the conventional example described above, the word line W and the dummy word line DW are changed from the low level to the high level, the minute potential difference is read from the memory cell MC and the dummy cell DC onto the bit lines B0 and B1, and the clock signal PS To low level and sense amplifier circuit (flip-flop circuit)
To amplify the minute potential difference to a large amplitude signal. During this period, the clock signals P1 and P2 are kept at low level. Next, when the sense amplifier circuit has finished operating sufficiently, first the clock signal P2 is set to high level and the transistor
The clock signal P1 is brought into conduction with T5 and T6, and the clock signal P1 is changed from the low level which is the first level to the high level which is the second level. As a result, the potential of the floating bit line on the high potential side is boosted via the coupling capacitance CC.

The boosted amount ΔV of the bit line level is VC, where VC is the level amplitude of the nodes N1 and N2. Becomes Thus, the level boosted amount ΔV is proportional to VC. Further, VC is limited by the high level potential V10 of the clock signal P1 and the high level potential V20 of the clock signal P2. That is, in the case of V20> V10 + VT (3), the transistors T5 and T6 maintain the conductive state even when the clock signal P1 is at a high level, so the level amplitude VC of the nodes N1 and N2 is equal to the level amplitude V1 of the clock signal P1. Will be equal. However, in the case of V20 <V10 + VT (4), when the clock signal P1 goes high, the transistors T5 and T6 become non-conductive, and the level amplitude VC of the nodes N1 and N2 becomes smaller accordingly. That is, assuming that the low-level potential of the clock signal P1 is the ground potential, VC = V1− {V10− (V20−VT)} = V20−VT (5), but by setting V20> VT The level amplitudes of N1 and N2 can be obtained, and this decrease in VC can be compensated by increasing the coupling capacitance CC, as can be seen from equation (2). For this reason, the high level of the clock signal P2 is (VB +
There is no restriction that it must be above (V + VT). Moreover, bit line B when the sense amplifier is operating
It does not increase the capacity of 0 and B1. Because the electrodes (nodes N1, N2) of the coupling capacitance CC at this time, which are connected to the transistors T5, T6, are in a floating state, and therefore the coupling capacitance CC of the coupling capacitance CC seen from the bit lines B0, B1 is This is because the size is very small and can be ignored.

In order to rewrite the boosted bit line potential (VB + ΔV) into the memory cell, it is necessary to set the high level of the word line W to (VB + ΔV + VT) or higher.

Further, the present invention is directed to the N-channel MOSFET used in the description herein.
However, p-channel MOSFETs and any other type of transistors are essentially applicable as well.

(Effect of the Invention) As described above, according to the present invention, it is possible to compensate for the decrease in the voltage level of the bit line at the time of rewriting without increasing the capacitance on the bit line, so that stable operation of the semiconductor memory device is possible. Becomes

[Brief description of drawings]

FIG. 1 is a sense amplifier circuit diagram showing an embodiment of the present invention,
FIG. 2 is a timing chart of each signal in the circuit shown in FIG. 1, FIGS. 3 and 6 are conventional sense amplifier circuit diagrams, FIG. 4 is a memory cell circuit diagram, and FIG. 5 is a dummy cell circuit. A circuit diagram, FIG. 7 is a timing diagram of each signal in the circuit shown in FIG. In the figure, MC is a memory cell, DC is a dummy cell, B0, B1
Is a bit line, W is a word line, DW is a dummy word line, CB is a parasitic capacitance attached to a bit line, CC is a coupling capacitance, CS is a cell capacitance, CR is a dummy capacitance, T1 to T6, T00, T10, T11 are MOSFETs. , P0
Indicates a precharge signal, and P1, P2, and PS indicate clock signals.

Claims (1)

[Claims] 1. A bit line forming a row, a word line forming a column, a memory cell selected by the word line for transferring information in and out of the bit line, and the bit line being an input / output signal line. , A coupling capacitor having one electrode connected to the bit line, a source electrode connected to the other electrode of the coupling capacitor, a first signal line connected to the drain electrode, and a gate electrode connected to the gate electrode. A field effect transistor to which a second signal line is connected, the field effect transistor being conductive when the bit line is charged, non-conductive when information is read from the memory cell, and rewriting information to the memory cell. At the time of operation, it is brought into a conducting state again, the first signal line is displaced from the first level to the second level at the time of this information rewriting operation, and again after this information rewriting operation is completed. The semiconductor memory device which is characterized in that the serial first level.