JPH0746504B2 - Semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device that stores information in the form of charges in a capacitor, and more particularly to improvement of a bit line precharge circuit section thereof.

[Technical background of the invention and its problems]

As the degree of integration of semiconductor devices has advanced, the chip size has increased, and the wiring such as Al has become longer and thinner. Therefore, the inductance of the wiring tends to increase, and the resulting power supply noise is a problem that cannot be ignored. In particular, a MOS dynamic RAM that constitutes a memory cell with one MOSFET and one capacitor
In (dRAM), there is a big problem because high integration is remarkable. For dRAM, the design rule is 0.7-0.5 μm
With the miniaturization of the element, it is inevitable to decrease the power supply voltage Vcc from the conventional 5V to, for example, about 3.3V. Then, in order to keep the access time to the same level as the conventional dRAM, the peak current increases accordingly. As a result,
The current fluctuation dI / dt in the wiring increases.

The above problem will be specifically described by taking the precharge operation of the 1 Mbit dRAM as an example. During the dRAM precharge period,
Bit lines, address buffers, decoders, peripheral clock generators, etc. are precharged, but the bit line precharge consumes the most current. Now
It is assumed that 128 memory cells are connected to one bit line, and the chip adopts the split operation type. The divided operation type is a method in which the memory array area of the chip is divided into a plurality of pieces in order to reduce the peak current and the current consumption at the time of access, and only the memory array area selected at the time of active is operated. For example, in a 4-array chip, 2 of them
Control is performed so that the array region is selectively activated. In this case, the number of bit lines charged during the precharge is 2048. The capacity of one bit line is about 500fF, and if the power supply voltage V _CC = 5V is charged in 50ns, the average current Im at that time is Im = (2048 × 500 × 10 ^-15 F × 5V) / 50ns = 102.4 (mA). This is the average current, peak current is 200mA
As described above, if the peak current is reached in a short time of 10 ns, the current change dI / dt is dI / dt = 200mA / 10ns = 20 (MA / s). If the wiring inductance of the source current voltage V _SS (= 0V) is L = 30nH, the floating of the Vss potential is L · dI / dt = 30nH × 20MA / s = 0.6V. In reality, in addition to the bit lines, the address buffer, the decoder, the peripheral clock generator, and the like are overlapped and charged as described above, so that dI / dt becomes extremely large depending on the timing.

Next, a specific problem when dI / dt during precharging becomes large and noise occurs on the V _SS wiring will be described with reference to FIG. There is a hidden refresh mode in the specifications of 1Mbit dRAM, and refresh can be performed while reading or writing. For example, as shown in FIG. 5, when the data out Dout is read with "1" or "0" and toggled with ▲ ▼, the address counter in the chip operates and the chip refresh is performed. is there. Of course, during this refreshing, the bit lines are charged and discharged. The noise when the bit line is discharged is not so large, but the noise when the bit line is charged is large, especially when the output level of the data-out Dout when reading "0" exceeds the value V _OL = 0.4V specified in the specifications. There is a problem that it ends up.

In addition, in the specification of 1 Mbit dRAM, when entering the precharge cycle, it is decided that the data out Dout is set to Hi-z after t _OFF = 10 ns has elapsed from the start of ▲ ▼. 6 as shown in FIG, ▲ ▼ the ▲ ▼ performed precharge launched earlier than, again without satisfying t _OFF Again, "0" is read when the data out Dout of the output level Exceeds V _OL = 0.4V.

In order to solve such a problem, a method of dispersing the precharge of each part has been conventionally considered. However, dI / dt
In particular, the bit line precharge, which has a particularly large influence, has not been sufficiently improved.

[Object of the Invention]

The present invention has been made in view of the above points, and provides a semiconductor memory device capable of reducing dI / dt at the time of precharging a bit line, suppressing power supply noise, and increasing a margin of circuit operation. To aim.

[Outline of Invention]

The present invention divides a bit line to be charged at the time of precharging into at least two first and second bit line groups, and sets the gate of the precharge MOSFET of the bit line group to the first bit line group for the first bit line group. Precharge to the power supply voltage by the first clock generated from the second clock generator, and delay the second bit line group by a predetermined time to the power supply voltage by the second clock generated from the second clock generator. The bit line precharge is performed by performing clock control such that the gate of each of the precharge MOSFETs is boosted above the power supply voltage by the third clock generated by the third clock generator after being charged for a predetermined time. It is characterized in that it is done.

〔The invention's effect〕

According to the present invention, since the bit lines are divided into a plurality of groups and dispersed to perform the precharge, dI / dt at the time of charging the bit lines can be reduced. Therefore, at the time of a hidden refresh or when reading ▲ ▼ earlier than ▲ ▼ to perform precharge, read out the data out "L" level
The rise of Vout can be suppressed and the specifications such as 1Mbit dRAM can be easily satisfied. Further, according to the present invention, noise generated not only in the source power supply but also in the drain power supply wiring is suppressed, and the dRAM circuit operation margin is improved.

Further, in the present invention, the distributed control of the bit line precharge is performed by the clock generator. In this case, the delay time between the clocks can be easily set by the combination of the unit clock generators, and the controllability can be improved. Is excellent.

Example of Invention

 Examples of the present invention will be described below.

FIG. 1 shows a schematic structure of a dRAM of one embodiment. The memory array is formed by arranging memory cells, which are composed of capacitors and MOSFETs, in a matrix on a semiconductor substrate by a known method. In this example the memory array has two blocks MA ₁ ,
It shows the case of being divided into MA ₂ . WL ₁ , ..., WLn are word lines that selectively drive the memory cells, and BL ₁ , ▲
▼, BL ₁ ′, ▲ ▼ ′, ... Are bit lines for exchanging information charges with the memory cells. SA is a sense amplifier,
RD ₁ and RD ₂ are row decoders.

FIG. 2 shows a schematic configuration of the bit line precharge circuit section. In this example, the bit lines are divided into a first bit line group 1 and a second bit line group 2. For example, the first bit line group 1 is the bit line group on the side of the memory array block MA 1 in FIG. ₁ , and the second bit line group 2 is the bit line group on the side of the memory array block MA ₂ as well. . T
₁ (T ₁₁ , T ₁₂ , ..., T _1N ) is a precharge MOSFET of the first bit line group 1, and T ₂ (T ₂₁ , T ₂₂ , ..., T _2N ) is the second bit line group 1. 2 are MOSFETs for precharge, the drains of which are both connected to the power supply V _CC . Gate node N ₁ of the MOSFET-T ₁ of the first bit line group 1 side is charged by the first clock from the first clock generator CG _1, the second bit line group 2 side MOSFET- gate node N ₂ of T ₂ are adapted to be charged by the second second clock from the clock generator CG _2.
The gate nodes N ₁ and N ₂ are connected to the node N ₃ via MOSFETs-T ₃ and T ₄ , respectively. CG ₃ is a third clock generator that generates a third clock, and boost capacitors C ₁ and C ₂ , between the output terminal and the node N ₃ and the gates of MOSFETs T ₃ , T ₄ . C ₃ is provided. The gates of the node N ₃ and the MOSFETs-T ₃ , T ₄ are provided with MOSFETs-T ₅ , T ₆ , T ₇ for precharging them.

The operation of bit line precharge in the precharge circuit configured as described above will be described. First, a clock boosted to about 1.5 times the power supply voltage V _CC is input to the gate of the MOSFET-T ₅ , and the node N ₃ is precharged to the power supply voltage V _CC . In this state, the first clock generator CG ₁
Generates the first clock, and the gate node N _{1 of the} precharge MOSFET-T ₁ of the first bit line group 1 is charged to V _CC . As a result, charging of the first bit line group 1 is started via the MOSFET-T ₁ . At this time, MOSFET-T ₁ is 5
The charging speed is not so high because it becomes conductive in the pole operating region. Then, after a predetermined time delay, a second clock is generated from the second clock generator CG ₂ , the gate node N ₂ on the second bit line group 2 side is charged to V _CC , and the second bit line Charging for group 2 is started. The delay time from the first clock to the second clock is 4ns, for example.
It is set to about ec, and the charging of the second bit line group 2 is started before the first bit line group 1 is charged to V _CC -Vth. On the other hand, each MOSFET-T _3, the gate of T _4, the first clock, the second clock MOSFET-
Precharged by driving T ₆ and T ₇ . Then, for example, after a lapse of 4 n sec from the second clock, the third clock generator CG ₃ generates a third clock, which causes the node N to pass through the boosting capacitors C ₁ and C _2.
3 and MOSFET-T ₃ , T ₄ gates are boosted above V _CC ,
Therefore, the nodes N ₁ and N ₂ are simultaneously boosted above V _CC . As a result, the precharge MOSFETs -T ₁ and T ₂ enter the triode operating region, and the first and second bit line groups 1 and 2 are set to V
It will be precharged to _CC .

FIG. 3 shows a more specific circuit configuration of the circuit of FIG. In FIG. 3, CG _B1 is the first clock of FIG.
Corresponding to the generator CG ₁ , CG _B2 also corresponds to the second clock generator CG ₂ , and CG ₂₀ also corresponds to the third clock generator CG ₃ . Unit clock generators CG ₁₁ , CG ₁₂ , ... in order to add the above-mentioned delay to the output clocks of these clock generators.
The circuit is connected in cascade. The clock generators CG _B1 , CG _B2, etc. are well known and will not be described in detail. At the output stages of the clock generators CG _B1 and CG _B2 , respective output clocks, that is, a first clock φ _B1 and a second clock φ _B2 for precharging the first and second bit line groups, A booster circuit for boosting by the third clock generator CG ₂₀ is added. The correspondence relationship between the booster circuit portion and FIG. 2 will be described below. That is, the boosting capacitor of FIG.
The capacitors corresponding to C ₁ are M ₃ and M ₇ , and the capacitors corresponding to boosting capacitors C ₂ and C ₃ are M ₂ and M ₆ , respectively.
And the MOSFET corresponding to MOSFET-T ₃ , T ₄ in FIG.
Are Q ₂₅ and Q ₄₅ respectively, and the MOSFE corresponding to MOSFET-T ₅
MOSFE with T corresponding to Q ₂₆ and Q ₄₆ , MOSFETs − T ₆ and T _7.
T is Q ₂₂ and Q ₄₂ , respectively.

The operation of the precharge circuit thus configured will be described below. FIG. 4 shows the time chart. Before entering the precharge period, the clocks φ _P1 and φ _P2 are at “H” level. During this time, node through respective MOSFET-Q ₂₆ and Q ₄₆ capacitors M ₃ and M ₇ are precharged to V _CC. The nodes of capacitors M ₂ and M ₆ , that is, the gates of MOSFETs −Q ₂₅ and Q ₄₅ , are respectively
It is short-circuited by the MOSFET-Q _23, Q ₂₄ and Q _43, Q _44.
The clocks φ _P1 and φ _P2 go to “L” level, the output clock φ ₁ of the clock generator CG ₁ drives the first clock generator CG _B1, and the first clock φ _B1 rises to V _CC . At this time, the MOSFET-Q ₂₄ is off, and the node of the capacitor M ₂ is precharged via the MOSFET-Q ₂₂ . After a delay time of 5 stages of the unit clock generator, the second clock generator is output by the output clock φ ₅ of the clock generator CG _15.
CG _B2 is driven and the second clock φ _B2 rises to V _CC . At this time, the node of the capacitor M ₆ is precharged to V _CC via MOSFET-Q ₄₂ . After this, after a predetermined delay time, the output clock φ _{9 of the} clock generator CG ₁₉
Drives the third clock generator CG ₂₀ ,
The output clock φ ₁₀ simultaneously boosts the first and second clocks φ _B1 and φ _B2 to V _CC or higher via MOSFETs-Q ₂₅ and Q ₄₅ .

As described above, according to this embodiment, by distributing the bit line precharge,
The dI / dt can be reduced, and the operation margin of the dRAM can be greatly improved.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be carried out without departing from the spirit of the present invention. For example, the bit lines to be divided are not limited to two groups, but may be divided into three or more groups.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a dRAM according to an embodiment of the present invention,
FIG. 2 is a diagram showing a configuration of the bit line precharge circuit section, FIG. 3 is a diagram showing a circuit configuration in which the bit line precharge circuit section is more concrete, and FIG. 4 is a diagram for explaining its operation. Time charts, FIG. 5 and FIG. 6 are waveform charts for explaining the conventional problems. MA ₁ , MA ₂ ...... Memory array block, BL, BL ...... bit line, WL ...... word line, 1 ...... first bit line group, 2 ......
Second bit line group, T ₁ (T ₁₁ , T ₁₂ , ...), T ₂ (T ₂₁ , T ₂₂ ,
…） …… Precharge MOSFET, CG ₁ …… First clock generator, CG ₂ …… Second clock generator, CG ₃ …… Third clock generator, CG _B1 …
… First clock generator, CG _B2 …… Second clock generator, CG ₂₀ …… Third clock generator, φ _B1 …… First clock, φ _B2 …… Second clock, φ ₁₀ ...... Third clock.

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP 62-6489 (JP, A) JP 60-29998 (JP, A) JP 59-160888 (JP, A)

Claims (2)

[Claims] 1. A memory array in which a plurality of memory cells having capacitors for accumulating information charges are formed in a matrix on a semiconductor substrate, and a plurality of word lines for selectively driving the memory cells are selected. In a semiconductor memory device in which a memory cell and a plurality of bit lines for exchanging information charges are integrated and formed, the plurality of bit lines are divided into at least two first and second bit line groups, The precharge circuit generates a first clock that precharges the gates of the precharge MOSFETs of the first bit line group to the power supply voltage.
Generator and for each precharge of the second bit line group
A second clock generator for precharging the gate of the MOSFET to the power supply voltage and generating a second clock delayed by a predetermined time from the first clock, and for precharging each of the first and second bit line groups A third clock for boosting the gate of the MOSFET to a power supply voltage or higher, and generating a third clock delayed by a predetermined time from the second clock.
A semiconductor memory device having a generator. 2. The first to third clock generators are composed of circuits in which unit clock generators are cascade-connected, and the output stage thereof is selected to select one of the first clock and the second clock. 2. The semiconductor memory device according to claim 1, wherein the delay time between the second clock and the third clock is set to a predetermined value.