JPH0746900B2 - Charge pump circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit, and more particularly to a charge pump circuit suitable for use in a DC-DC converter.

[Conventional technology]

Conventionally, this type of charge pump circuit has a clock oscillation circuit that generates a clock signal composed of a high-level and low-level boosted potential (V _DD , GND ′ in the figure) and a low level of the clock signal up to the V _SS potential. It had a level shift circuit for shifting (Fig. 4). Timings of clocks A'to D ', etc. for operating the charge pump circuit are as shown in FIG.

[Problems to be Solved by the Invention]

In the conventional charge pump circuit described above, the boosted V _DD potential is applied to the back gate (substrate),
When the high side of the clock oscillator circuit is also set to V _DD , the threshold value of the transistor forming the oscillator circuit does not substantially change, and the oscillation frequency does not decrease. Since the oscillation frequency does not decrease, there is a drawback that the leak current, that is, the through current is large.

Further, the clock A'to operate the charge pump circuit
Depending on the timing of D '(Fig. 4), there is a moment when all the transistors N _C , P _D , P _A , N _B (see Fig. 1) in the charge pump circuit are in the ON state, and the capacitor is charged. There is a drawback that the generated charges flow out and the potential is lost.

[Means for Solving the Problems]

A charge pump circuit of the present invention is connected between a first power supply line of a first potential, a second power supply line of a second potential, and the first and second power supply lines, and has an amplitude from the first potential. A clock oscillation circuit that outputs a clock that changes to the second potential, and a third potential that is higher than the first potential
Power supply line and a fourth potential higher than the second potential.
Level shifter connected between the third power supply line and the third and fourth power supply lines and inputting the clock, and level-shifting the clock so that the amplitude of the clock changes from the third potential to the fourth potential. A circuit, wherein the level shift circuit changes the time for the level-shifted clock to change from the third potential to the fourth potential and the time for the fourth potential to change to the third potential. Characterize.

Further, the level shift circuit includes a first transistor of one conductivity type connected between the third power supply line and the first node and having a gate connected to the second node; and the third power supply line. And a second transistor of the one conductivity type having a gate connected to the first node and a gate connected to the first node, and a gate connected to the first node and the second power supply line. The second conductivity type third transistor having the gate to which the inverted signal of the clock is inputted, and the second conductivity type having the gate to which the clock is inputted and connected between the second node and the second power supply line. -Type fourth transistor, the one-conductivity-type fifth transistor connected between the third power supply line and the third node, and the gate connected to the first node, and the third transistor Node and the fourth A sixth transistor of the second conductivity type connected between the source line and the gate connected to the fourth node; and a gate connected between the third power supply line and the fourth node and the gate connected to the fourth node. The seventh transistor of one conductivity type connected to the second node, and the second conductivity type connected between the fourth node and the fourth power supply line and having the gate connected to the third node. And an inversion signal of the level-shifted clock and the level-shifted clock from the third node and the fourth node.

In contrast to the conventional clock oscillation circuit that generates a clock signal composed of a boosted potential and the charge pump circuit that has a level shift circuit that only boosts the clock signal, the present invention provides , High level and low level reference potentials are used. In the level shift circuit, the capacitors in the charge pump circuit are all independent "off (OF
F) The timing when "time" exists is also generated.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is an equivalent circuit diagram of the first embodiment of the present invention.
FIG. 2 is a timing chart of the clock input and each contact of a, b, A, B, C and D of the embodiment shown in FIG.

The circuit of the present embodiment is composed of an oscillator circuit for generating a clock signal of a reference potential V _CC , GND level, a potential V boosted from V _CC , GND.
_It consists of a level shifter circuit that converts to _DD and V _SS , an inverter circuit that generates independent 4-phase signals, and a charge pump circuit.

The frequency of the clock signal generated by the oscillator circuit is that the back gate of the P-channel (Pch) transistor is V _DD while its source is V _CC , so when the potential of V _DD is stable, use V _DD as the source. Since the execution threshold of the transistor is higher than that in the case where the frequency is low, the frequency thereof is low. Get lower. As a result, the leak current of the DC-DC converter circuit can be suppressed.

In the level shifter circuit, assuming that the gate widths of P1 and N1 in FIG. 1 are P1 >> N1, contact points a and
The waveform of b has a gentle slope only at the falling edge as shown in FIG. Due to this difference between the rising and falling slopes, from the state in which the transistors N _C and P _D are ON and P _A and N _B are OFF,
While transistor N _C, is P _D converting OFF, P _A, is N _B to the state ON, the transistor _{N C, P D, P A} , all N _B can make OFF time turned OFF.

FIG. 3 is an equivalent circuit diagram of the level shifter circuit used in the second embodiment of the present invention. First embodiment (see FIG. 1)
Between the N-channel (Nch) transistor N1 and the P-channel (Pch) transistor P1 of the level shifter circuit in FIG. 1, an N-channel (Nch) transistor N1 'whose gate width is fixed to V _CC and whose gate width is equal to that of the transistor N1 is inserted.

As a result, in this embodiment, there is an advantage in that the falling slope of the signal at the contact points a and b can be made gentler, and as a result, the off time can be extended.

〔The invention's effect〕

As described above, according to the present invention, in the oscillation circuit, the reference potentials V _CC and GND are provided on the high side and the low side instead of V _DD and V _SS.
By using, it is possible to suppress the oscillation frequency of the clock and thus reduce the leak current.

Also, in the level shifter circuit, when the connection of the capacitor in the charge pump circuit is converted by making a difference between the rising and falling slopes of the clock signal,
It is possible to provide an independent off time for all capacitors, thus preventing the charge from flowing out and eliminating the voltage loss.

[Brief description of drawings]

1 is an equivalent circuit diagram of the first embodiment of the present invention, FIG. 2 is a timing chart diagram of the circuit shown in FIG. 1, and FIG. 3 is an equivalent circuit diagram of the second embodiment of the present invention. 4 and 5 are an equivalent circuit diagram and a timing chart diagram of the prior art, P1, P2, P _A , P _D ... P-channel transistors, N1, N2, N, respectively.
1 ', N2', N3, N B, N C ...... N -channel transistor, CK,
CKB ... clock input signal, C1, C2, C3, C4 ... capacitor, V _CC ... power supply voltage, V _DD ... voltage generated from V _CC , V _SS ... voltage generated from V _CC (= −V _DD ), 1,2,
3,4 …… Inverter circuit, CK ′, CKB ′ …… Clock input signal.

Claims (2)

[Claims] 1. A first power source line having a first potential, a second power source line having a second potential, and a first power source line connected between the first and second power source lines, and having an amplitude from the first potential to the second power source line. A clock oscillation circuit that outputs a clock that changes to a potential, a third power supply line having a third potential higher than the first potential, a fourth power supply line having a fourth potential higher than the second potential, and the third power supply line. And a level shift circuit that is connected between a fourth power supply line and receives the clock, and outputs a clock whose level is shifted so that the amplitude of the clock changes from the third potential to the fourth potential. The circuit is characterized in that the level-shifted clock is changed from the third potential to the fourth potential at a different time from the fourth potential to the third potential. Road. 2. The level shift circuit includes a first-conductivity-type transistor connected between the third power supply line and a first node and having a gate connected to a second node, and the third transistor. Between the first power supply line and the second node and the gate connected to the first node and the first conductivity type second transistor, and the first power line and the second power line. A third transistor of the second conductivity type, which is connected to the second gate and receives the inverted signal of the clock at its gate,
The fourth transistor of the second conductivity type, which is connected between the second node and the second power supply line and receives the clock at its gate, the third power supply line and the third transistor.
And a gate connected to the first node and a gate connected to the first node, and a gate connected to the third node and the fourth power supply line. A second transistor of the second conductivity type connected to a node of the second conductivity type, and the first conductivity type of a transistor connected between the third power supply line and the fourth node and having a gate connected to the second node A seventh transistor and an eighth transistor of the second conductivity type, which is connected between the fourth node and the fourth power line and has a gate connected to the third node, 2. The charge pump circuit according to claim 1, wherein the level-shifted clock and an inverted signal of the level-shifted clock are output from the third node and the fourth node.