JPH0748189B2 - Data processing device - Google Patents

Description

The present invention relates to a data processing device having a cache memory, and more particularly to a data processing device suitable for a real-time multitasking system having a plurality of cache memories.

[Conventional technology]

FIG. 3 is an example of a block diagram showing a configuration of a main part of a conventional general data processing device having a plurality of cache memories.

In the figure, reference numeral 1 denotes a data processing unit, which includes a plurality of cache memories to be described later, that is, first, second, third and fourth cache memories 2,
Data is accessed to 3, 4, 5 or the main memory 7. In addition, the data processing unit 1 uses each cache memory 2,
When accessing data in the area (non-cacheable area) of the main memory 7 that should not be held in 3, 4 or 5, the low active second signal S2 given to the bus driver circuit 6 to be described later is applied. Make it active (low level).

Each of the cache memories 2, 3, 4, and 5 adopts the 4-way set associative method and the write-through method, and always keeps the data coincident with the main memory 7.

When each of the cache memories 2, 3, 4, and 5 is accessed by the data processing unit 1, if it does not hold the data to be accessed, it activates the low-active first signal S1. The first signal S1 output from each of the cache memories 2, 3, 4, 5 is an input signal of the 4-input logic circuit 8.

The logic circuit 8 has at least one of the four inputs.
If the input is active, the low active output signal is activated.

The cache memories 2, 3, 4, and the data processing unit 1 are connected to the system bus SB via the data bus DB, but the data bus DB has a bus at the connection point with the system bus SB. The driver circuit 6 is interposed.

The bus driver circuit 6 is controlled by the first signal S1 output from the data processing unit 1 and the output signal of the logic circuit 8 to open / close the data bus DB, and the data processing unit 1 and each cache memory 2, 3 Connect between 4, 5 and system bus SB and disconnect. More specifically, the data processing unit 1
If either one of the first signal S1 output from the logic circuit 8 and the signal output from the logic circuit 8 is active, the bus driver circuit 6 causes the data processing unit 1 and each cache memory 2, 3, 4, 5, And system bus SB are connected so that data can be sent and received.

The above-mentioned data bus DB is connected to the system bus SB via the bus driver circuit 6, and the main memory 7 is also connected to the system bus SB.

The main memory 7 stores various data to be accessed by the data processing unit 1.

The operation of the data processing device having such a conventional cache memory is as follows.

When the data processing unit 1 makes a read access to data, each of the cache memories 2, 3, 4, and 5 determines whether or not the data itself to be accessed is held. When the data to be accessed is held, it is called a cache hit,
The data to be accessed is sent to the data processing unit 1 via the data bus DB from any of the cache memories 2, 3, 4, and 5 in which it is held.

The data to be accessed is cache memory 2,3,
A case where the data is not held in 4,5 is called a cache miss, and 4-word data (corresponding to the number of lines of each cache memory 2, 3, 4, 5) including the data to be accessed is output from the main memory 7. It is sent to the cache memories 2, 3, 4, 5 and the data processing unit 1 via the system bus SB and the data bus DB. The data processing unit 1 takes in the 4-word data sent from the main memory 7. In each cache memory 2, 3, 4 and 5, an address area that can be held within the address of the main memory 7 is set in advance as a cacheable area, and the data sent from the main memory 7 has the address. Is held in any of the cache memories 2, 3, 4, and 5 in which the cacheable area including is set.

By the way, when the data processing unit 1 performs a data read operation or a data write operation, first, the cache memories 2, 3, 4,
Access 5. At this time, if the access signal output from the data processing unit 1 is directly applied to the main memory 7, the data is read from the main memory 7 and output. On the other hand, if a cache hit occurs in any of the cache memories 2, 3, 4, and 5 at the same time, the data is also output from that cache memory. Therefore, the cache memory 2,3,
The data output from any one of 4 and 5 and the data output from the main memory 7 will collide on the data bus DB, and in order to avoid this, between the main memory 7 and the data processing unit 1. Can be cut off by the bus driver circuit 6.

When the data processing unit 1 makes a cache miss, it is necessary to transfer the data to be accessed from the main memory 7 to the data processing unit 1. Therefore, each cache memory 2,3,4,5
Activates a signal indicating that it has made a cache miss, that is, each first signal S1 and supplies it to the bus driver circuit 6. As a result, the bus driver circuit 6 is opened to drive the data bus DB, and the data processing unit 1 and the main memory 7 are
It becomes possible to send and receive data between and.

Further, when the data processing unit 1 accesses an area such as an I / O area in the memory area of the main memory 7 that should not be cached, the non-cacher output from the data processing unit 1 is used. The bull signal, that is, the second signal S2 becomes active. This second signal S2 is the bus driver circuit 6
When the second signal S2 becomes active, the bus driver circuit 6 drives the data bus DB to enable the data transfer between the data processing unit 1 and the main memory 3. . As a result, the data processing unit 1 can directly access the main memory 7.

As described above, the data bus DB must be driven to make the main memory 7 accessible from the data processing unit 1 except when any one of the cache memories 2, 3, 4, and 5 has a cache hit. .

Each of the cache memories 2, 3, 4, and 5 has an address comparator of the upper 4 bits of the address in which the upper 4 bits of the address of the access target are compared. This address comparator is composed of the upper 4 bits of the address set as a cacheable area in each of the cache memories 2, 3, 4, and the upper address of the data to be accessed given from the data processing unit 1 at the time of data access. It is possible to compare four bits and set either a mode for caching when they match or a mode for caching when they do not match.

Now, for example, the setting value of the address comparator of the first cache memory 2 is "0000", the second cache memory 3
The address comparator setting value of "0100", the address comparator setting value of the third cache memory 4 is "10"
00 ", the setting value of the address comparator of the fourth cache memory 5 is" 1100 ", and the mode for caching when the addresses match is set. This state is the memory space as shown in FIG. It can be represented schematically above.

For example, when the data processing unit 1 accesses with the upper 4 bits of the address being “0100”, the second cache memory 3
If only one caches and a cache miss occurs, the first signal S1 is activated and given to the bus driver circuit 6. The other first, third, and fourth cache memories 2, 4, and 5 do not perform caching because the upper 4 bits of the address set in each do not match.

If the upper 4 bits of the address to be accessed by the data processing unit 1 is, for example, “0010”, this address is not set as the cacheable area of any of the cache memories 2, 3, 4, and 5. , Neither of the cache memories 2, 3, 4, 5 is cached. Therefore, in this case, none of the cache memories 2, 3, 4 and 5 activates the first signal S1 and the data processing unit 1 does not activate the second signal S2. It does not drive the bus DB.

On the other hand, when the mode that does not perform caching when the upper 4 bits of the address match is set, the data bus DB is driven when at least one of the cache memories 2, 3, 4, and 5 causes a cache miss. Therefore, if any of the other cache memories 2, 3, 4, 5 hits the cache at the same time, the data output from the cache memory and the data output from the main memory 7 collide.

For example, when the set values of the internal address comparators of the cache memories 2, 3, 4, and 5 are as shown in the schematic diagram of FIG. 2, the upper 4 bits of the address of the data to be accessed by the data processing unit 1 are If "0100", only the second cache memory 3 does not perform caching,
The third and fourth cache memories 2, 4, 5 cache. At this time, for example, if the fourth cache memory 5 has a cache hit and the other first and third cache memories 2 and 4 have cache misses, the fourth cache memory 5 outputs the data to be accessed and at the same time the other cache memory From the first cache memory to the bus driver circuit 6
Signal S1 becomes active. Therefore, the data bus DB is driven, the data to be accessed is output from the main memory 7, and data collision occurs. The same data collision also occurs when the data processing unit 1 accesses data whose upper 4 bits of the address are "0010".

[Problems to be Solved by the Invention]

As described above, in the conventional data processing device having a plurality of cache memories, when an area other than the cacheable area set in at least one cache memory is accessed, the access target data is cached. Output from both memory and main memory,
There is the problem that they collide on the data bus.

The present invention has been made in view of such circumstances,
An object of the present invention is to provide a data processing device configured such that each of a plurality of cache memories detects whether an address of data to be accessed is a cacheable area and avoids data collision according to the result.

[Means for Solving the Problems]

The data processor of the present invention comprises means for detecting whether or not an address of an area other than the cacheable area set in each of the plurality of cache memories has been accessed, and each of the plurality of cache memories is capable of caching. The configuration is such that the data processing unit and the main memory are connected when it is detected that an area other than the area is accessed.

[Action]

In the data processing device of the present invention, the data processing unit and the main memory are connected when it is detected that all areas other than the respective cacheable areas are accessed in all of the plurality of cache memories, so that data collision is avoided. To be done.

Example of Invention

Hereinafter, the present invention will be described in detail with reference to the drawings showing an embodiment thereof.

FIG. 1 is a block diagram showing a configuration of a main part of a data processing device according to the present invention. The same or corresponding parts as those of the conventional example shown in FIG. 3 are designated by the same reference numerals.

In the figure, reference numeral 1 denotes a data processing unit, which includes a plurality of cache memories to be described later, that is, first, second, third and fourth cache memories 2,
Data is accessed to 3, 4, 5 or the main memory 7. In addition, the data processing unit 1 uses each cache memory 2,
When accessing data in the area (non-cacheable area) of the main memory 7 that should not be held in 3, 4 or 5, the low active second signal S2 given to the bus driver circuit 6 to be described later is applied. Make it active (low level).

Each of the cache memories 2, 3, 4, and 5 adopts the 4-way set associative method and the write-through method, and always keeps the data coincident with the main memory 7.

When each of the cache memories 2, 3, 4, and 5 is accessed by the data processing unit 1, if it does not hold the data to be accessed, it activates the low-active first signal S1. The first signal S1 output from each of the cache memories 2, 3, 4, 5 is an input signal of the 4-input logic circuit 8.

The logic circuit 8 has at least one of the four inputs.
If the input is active, the low active output signal is activated.

The cache memories 2, 3, 4, and the data processing unit 1 are connected to the system bus SB via the data bus DB, but the data bus DB has a bus at the connection point with the system bus SB. The driver circuit 6 is interposed.

Further, each cache memory 2, 3, 4, 5 has a main memory 7 in advance.
The address area that can be held is set as a cacheable area, and the data sent from the main memory 7 has a cacheable area that matches the address.
It is held at 2,3,4,5.

Specifically, each of the cache memories 2, 3, 4, and 5 has an address comparator inside which the upper 4 bits of the target address are compared. This address comparator is composed of the upper 4 bits of the address set as a cacheable area in each of the cache memories 2, 3, 4, and the upper address of the data to be accessed given from the data processing unit 1 at the time of data access. Four
It is possible to compare the bits with each other, and set either the mode in which caching is performed when they match or the mode in which caching is performed when they do not match.

Further, the low-active third signal S3 is applied to the 4-input logic circuit 9 from each of the cache memories 2, 3, 4, and 5.
This third signal S3 is applied to each of the cache memories 2, 3, 4,
In 5, when the comparison result by the above-mentioned internal address comparator does not match, in other words, it becomes active when an address other than the cacheable area of each cache memory 2, 3, 4, 5 is accessed. Then, the logic circuit 9 outputs the fourth signal S4 which is a low active output signal only when all four inputs are active.
To activate. The fourth signal S4 is given to the bus driver circuit 6.

The bus driver circuit 6 includes the first signal S1, the output signal of the logic circuit 8 and the logic circuit 9 provided from the data processing unit 1.
The data bus DB is opened / closed by being controlled by the fourth signal S4 given from the. More specifically, if at least one of the first signal S1, the output signal of the logic circuit 8 and the fourth signal S4 output from the logic circuit 9 provided from the data processing unit 1 is active, the bus driver The circuit 6 connects the data processing unit 1 and the cache memories 2, 3, 4, and 5 to the system bus SB so that data can be transmitted and received.

The above-mentioned data bus DB is connected to the system bus SB via the bus driver circuit 6, and the main memory 7 is also connected to the system bus SB.

The main memory 7 stores various data to be accessed by the data processing unit 1.

The operation of the data processing device having such a conventional cache memory is as follows.

When the data processing unit 1 makes a read access to data, each of the cache memories 2, 3, 4, and 5 determines whether or not the data to be accessed is held by itself. The case where the data to be accessed is held is referred to as a cache hit, and the data to be accessed is from the cache memory 2, 3, 4, or 5 where it is held via the data bus DB to the data processing unit 1. Sent to.

The data to be accessed is cache memory 2,3,
The case where the data is not held in 4,5 is called a cache miss, and the data of 4 words (corresponding to the number of lines of each cache memory 2, 3, 4, 5) including the data to be accessed from the main memory 7 is the system. It is sent to the cache memories 2, 3, 4, 5 and the data processing unit 1 via the bus SB and the data bus DB. The data processing unit 1 sends the data from the main memory 7
Capture word data. In addition, each cache memory 2,3,
4,5 are held in any of the cache memories 2, 3, 4, 5 in which a cacheable area that matches the address is set.

By the way, when the data processing unit 1 performs a data read operation or a data write operation, first, the cache memories 2, 3, 4,
Access 5. At this time, if the access signal output from the data processing unit 1 is directly applied to the main memory 7, the data is read from the main memory 7 and output. On the other hand, if a cache hit occurs in any of the cache memories 2, 3, 4, and 5 at the same time, the data is also output from that cache memory. Therefore, the cache memory 2,3,
The data output from 4,5 and the data output from the main memory 7 collide with each other on the data bus DB. To avoid this, a bus driver is provided between the main memory 7 and the data processing unit 1. It is possible to cut off by the circuit 6.

When the data processing unit 1 makes a cache miss, it is necessary to transfer the data to be accessed from the main memory 7 to the data processing unit 1. Therefore, each cache memory 2,3,4,5
Is a signal indicating that it has made a cache miss, that is, the first
The signal S1 is supplied to the bus driver circuit 6 as active. As a result, the bus driver circuit 6 is opened and the data bus DB is driven, so that data can be sent and received between the data processing unit 1 and the main memory 7.

Further, when the data processing unit 1 accesses an area (non-cacheable signal) that should not be cached, such as an I / O area in the memory area of the main memory 7, the data processing unit 1 The non-cacheable signal that is output, that is, the second signal S2 becomes active. The second signal S2 is given to the bus driver circuit 6, and when the second signal S2 becomes active, the bus driver circuit 6
Drives the data bus DB, the data processing unit 1 and the main memory 3
It is possible to send and receive data between and. As a result, the data processing unit 1 can directly access the main memory 7.

As described above, it is necessary to drive the data bus DB so that the data processing unit 1 can access the main memory 7 except when one of the cache memories 2, 3, 4, and 5 has a cache hit.

Now, for example, the setting value of the address comparator of the first cache memory 2 is "0000", the second cache memory 3
The address comparator setting value of "0100", the address comparator setting value of the third cache memory 4 is "10"
00 ", the setting value of the address comparator of the fourth cache memory 5 is" 1100 ", and the mode for caching when the addresses match is set. This state is the memory space as shown in FIG. Can be schematically represented by.

For example, when the upper 4 bits of the address to be accessed by the data processing unit 1 are "0100", only the second cache memory 3 caches and the third signal S3 is made inactive. Other first, third, fourth cache memory 2,4,5
Does not perform caching because the upper 4 bits of the address, which is the cacheable area set for each, do not match, and activates the respective third signal S3.

As described above, the fourth signal S4, which is an output signal from the logic circuit 9, becomes active, and the bus driver circuit 6 does not drive the data bus DB. At this time, only when the cached second cache memory 3 has a cache miss and when the access target is a non-cacheable area, the data is supplied from the second cache memory 3 and the data processing unit 1 to the bus driver circuit 6, respectively. The first signal S1 and the second signal S2 are activated and the bus driver circuit 6 drives the data bus DB. Therefore, the data output from the second cache memory 3 does not collide with the data output from the main memory 7.

If the upper 4 bits of the address to be accessed by the data processing unit 1 is “0010”, this address is not set as the cacheable area of any of the cache memories 2, 3, 4, and 5, The third signal S3 of all the cache memories 2, 3, 4, 5 becomes active. Therefore, the fourth signal S4, which is the output signal of the logic circuit 9, becomes active, and the bus driver circuit 6 drives the data bus DB. This allows the data processing unit 1 to access the main memory 7.

On the other hand, when the mode that does not perform caching when the upper 4 bits of the address match is set, the following is performed.

For example, when the set values of the internal address comparators of the cache memories 2, 3, 4, and 5 are as shown in FIG.
If the upper 4 bits of the address of the data to be accessed by the data processing unit 1 are “0100”, only the second cache memory 3 does not cache, and the other first, third, fourth cache memories 2, 4, 5 is caching. That is, the third signal S3 of the second cache memory 3 becomes active, and the third signal S3 of the other 1,3,4 cache memories 2,4,5 becomes non-active. Therefore, the fourth signal S4 which is the output signal of the logic circuit 9 becomes non-active, and the bus driver circuit 6 does not drive the data bus DB.

At this time, the data bus DB is driven when the first, third, fourth cache memories 2, 4, 5 other than the second cache memory 3 cause a cache miss, and when the access target by the data processing unit 1 is a non-cacher. Only in the case of the bull area, data collision does not occur.

Further, when the upper 4 bits of the address to be accessed by the data processing unit 1 are “0010”, all the cache memories 2, 3, 4 and 5 are cached and the respective third signal S.
3 becomes inactive. Therefore, the fourth signal S4, which is the output signal of the logic circuit 9, becomes non-active and the bus driver circuit 6 does not drive the data bus DB, so that no data collision occurs.

〔The invention's effect〕

As described in detail above, in the data processing of the present invention, when a plurality of cache memories are provided, if it is detected that all cache memories other than the respective cacheable areas are accessed. Since the data processing unit and the main memory are connected so that the data processing unit can access the data processing unit, data collision can be avoided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a data processing apparatus of the present invention, FIG. 2 is a schematic diagram showing a cacheable area of each of a plurality of cache memories, and FIG. 3 is a data having a conventional cache memory. It is a block diagram which shows the structure of the principal part of a processing apparatus. 1 ... Data processing unit, 2,3,4,5 ... Cache memory,
6 ... Bus driver circuit, 7 ... Main memory, DB ... Data bus, SB ... System bus, S1 ... First signal, S2 ...
2nd signal, S3 ... 3rd signal In addition, the same code | symbol shows the same or corresponding part in each figure.

Claims (1)

[Claims] 1. A data processing unit, a main memory connected to a system bus and accessed by the data processing unit, and a predetermined area of the main memory is set as a holdable area. A plurality of cache memories that hold a part of the stored contents and output a predetermined signal when the data to be accessed is not held at the time of data access by the data processing unit, and a case where the predetermined signal is given. A data processing device comprising a bus driver circuit that connects the data processing unit and the system bus to enable the data processing unit to access the main memory, wherein each of the cache memories includes the data processing unit. Outputs a predetermined signal when the data to be accessed by is outside the holdable area set for each The bus driver circuit is configured to connect the data processing unit and the system bus when the predetermined signal is output from all the cache memories. Processing equipment.