JPH0748298B2 - FIFO circuit - Google Patents

Description

The present invention relates to a FIFO circuit, and more particularly to a FIFO circuit whose delay stage number can be controlled and which is suitable for high-speed operation LSI.

[Conventional technology]

 FIG. 6 is a block diagram showing a first conventional example.

The FIFO circuit shown in FIG. 6 uses the input data 602 as a clock 601.
The data flip-flops 607, 608, 609, 610, 611, 612, 613 for the purpose of sequentially fetching and shifting in accordance with the above, and a multiplexer 614 which selects only one of these outputs by the selection signals 603, 604, 605 and outputs it to the output 606.

FIGS. 7 and 8 are a timing chart and a truth table showing the operation of the conventional circuit of FIG. 6, respectively.
The operation will be described based on these.

In the timing chart of FIG. 7, input data 602
Are fetched and shifted every clock in accordance with the clock 601. Here, in this operation, the selection signals 603, 604, and 605 to the multiplexer 614 are SEL0 =
Assuming that “1”, SEL1 = “0”, SEL2 = “1”, the output of the data flip-flop 611 is selected as the output 606 according to the truth table of FIG. Is output as shown in the timing chart. Thus, according to the truth table of FIG. 8, the conventional circuit of FIG.
The 604 and 605 operate as a FIFO circuit having a variable number of delay stages.

FIG. 9 is a block diagram showing a second conventional example.

In the FIFO circuit shown in FIG. 9, the input data 901 is input to the input gate 9
It is provided to the data input / output via 12 and is also connected to the data input of the output data flip-flop 904.
Bits × n words of RAM 909 and clock 903
Counter 905 that operates as an up-counter for the remainder system of
And the value of the counter 905 and the output of the logic gate 906 that generates the delay amount d indicated by the selection signal 902, and the adder 907 that adds the remainder system of n and the control signal from the control circuit 910. It is configured to include a multiplexer 908 which switches between the 905 and the adder 907 and supplies an address to the RAM 909.

FIG. 10 is a timing chart showing the operation of the conventional circuit of FIG. 9, and the operation will be described below based on this. First
As for the address of the RAM 909, the write data address is accessed by the output of the adder 907 via the multiplexer 908 during the period of the clock 903 being “1”, and during the period of the clock 903 being “0”, Similarly, an address for read data is accessed by the output of the counter 905 via the multiplexer 908. Further, the counter 905 is counted up at the rising edge of the clock 903.

Further, the control signal from the control circuit 910 causes the input data 901 to be input to the input gate 912 while the clock 903 is “1”.
It is given to the data input / output of RAM909 via
A write pulse is applied to 09 from the control circuit 910.

The final output data 904 is obtained by latching read data obtained from the data input / output of the RAM 909 by the data flip-flop 911 at the rising edge of the clock 903 while the clock 903 is “0”.

If one cycle of operation is from the rising edge of the clock 903 to the next rising edge, the above description is summarized as follows.
It looks like this: First, the input data 901 is written to an address relatively offset by + d from the read data address of the RAM 909 while the clock 903 is "1", and then from the RAM 909 while the clock 903 is "0". The read data is latched in the data flip-flop 911 at the next rising edge of the clock 903, the output data 904 is output, and at the same time, the counter 905 is counted up, so that the next read address is set to +1. Becomes

As is clear from the above, the input data 901 written at a certain timing is output data 904 after d + 1 clocks.
Therefore, the conventional circuit of FIG. 9 also operates as a FIFO circuit having a variable number of delay stages. Note that the counter
905 and the adder 907 operate as a remainder system of n means that the up-count result of the counter 905 or the adder 9
If the addition result of 07 is more than n, it indicates that the value of the remainder system of n from 0 to n-1 is retaken.
This means accessing addresses 0 to n-1 of the RAM 909.

[Problems to be Solved by the Invention]

Of the conventional FIFO circuits shown in FIG. 6 and FIG.
The circuit shown in the figure has a relatively simple circuit configuration, and since the operation speed itself is almost determined only by the propagation delay time per data flip-flop, it is fast, but on the other hand, the data bit width m, When the maximum number of data delays is n, there is a drawback that the wiring and the area occupied by the multiplexer 614 become large when integrated into an LSI because only one word is selected from m bits × n words of data and output.

Next, in the conventional circuit of FIG. 9, although the memory cells of the RAM 909 can be highly integrated into an LSI, the counter 905, the adder 907,
As is clear from the timing chart of FIG. 10 and the scale of peripheral circuits such as the multiplexer 908,
Since it is necessary to generate an address for each of the writing and reading of the RAM 909 within one clock and execute the address once, there is a drawback that it is not suitable for high-speed operation.

[Means for Solving the Problems]

In the FIFO of the present invention, master / slave type data flip-flops for inputting the first and second clocks are arranged in m bits × n stages (m and n are both positive integers), and the first stage m bits are arranged. Connect the data input to the m-bit input terminal,
The m-bit data input of the second and subsequent stages is connected to the m-bit data output of the preceding stage, the m-bit data output of the n-th stage is connected to the m-bit output terminal, and the i-th stage (i is 1 to n
Take all positive integers up to. ), The OR signal output of the first phase clock and the i-th control signal output from the control circuit is connected to the first clock input of the m data flip-flops, Shift register of m bits × n stages in which an OR signal output of the second phase clock and the i-th control signal output from the control circuit is connected to the second clock input of And a control circuit for providing

As a result, the data flip-flop in the stage where Gi = "1" is activated simultaneously with the first and second clock inputs, so that the input data operates as a gate that is directly output as output data. Since the stage set to "0" operates as a normal data flip-flop, an arbitrary number of delay stages can be obtained without using a multiplexer.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The FIFO circuit shown in FIG. 1 has master-slave-type data flip-flops arranged in m bits × n stages (m = 4, n = 8 in the example of FIG. 1), and the data flip-flops of the first stage are arranged. The data inputs of the block block 101 are connected to the input data 1, 2, 3, and 4, respectively, and the data inputs of the second-stage data flip-flop block 102 and the subsequent stages are respectively connected to the data output of the preceding stage, and the n-th Data output of data flip-flop block (8th stage) 108 is output data 1
1, 12, 13, 14 and further to the first clock input of the i-th stage data flip-flop block, the first phase clock 5 and the gate signal Gi = (i = 1 to 1 from the control circuit 15
n) OR signal output is connected to the second clock input
The configuration is such that the OR signal output of the phase clock 6 and the gate signal Gi are connected. The gate signal Gi from the control circuit 15 is controlled by the control inputs 7, 8 and 9. 2 (a) to 2 (c) are operation explanatory diagrams of the master-slave type data flip-flop shown in FIG.

FIG. 2 (a) shows the internal circuit of the master-slave type data flip-flop 200.
2 is connected in cascade.

FIG. 2B is a truth table showing the operation of these data latches 201 and 202. As is clear from this truth table, the data latches 201 and 202 output the data input data as they are while the clock input is “1” and hold the latched data while the clock input is “0”. Operate.

FIG. 2C is a timing chart showing the operation of the master / slave type data flip-flop 200,
A master / slave type operation is performed in which the input data D is taken into the data clutch 201 at the timing of the first clock C1 and the output of the data latch 201 is output as an output signal at the timing of the second clock C2.

Here, in order to operate as a normal data flip-flop, as is clear from the above, it is necessary to control the timing so that the first clock and the second clock do not become active at the same time. When the two clocks become active at the same time, a so-called "data leakage" phenomenon occurs, that is, input data appears as it is as output data. The present invention positively utilizes this "data puncture phenomenon" of the data flip flop.

The gate signals G1, G2, ..., G8 from the control circuit 15 of FIG.
It is a control signal of each stage for performing this "data tsukushi", and the master of the stage when Gi = "1" (i = 1 to n)
The first and second clock inputs of the slave type data flip-flop are both active regardless of the first phase clock 5 and the second phase clock 6, so that "data leakage" occurs and the next stage The input data is output as is.

Further, the first phase clock 5 is input to any one of OR 101a, 102a, ..., 108a at the first clock input of the master / slave type data flip-flop in the stage where Gi = "0" (i = 1 to n). Via the second clock input to the second clock input.
Since the phase clock 6 is applied via any of OR 101b, 102b, ..., 108b, it operates as a data flip-flop.

Next, FIG. 3 is a truth table of the operation of the circuit of FIG. 1 of the present invention. However, the internal circuit of the control circuit 15 is assumed to be given in FIG. Control input to control circuit 15, 8, 9
As a result, the gate signals G1, G2, ..., G8 have the logic shown in FIG. 3, and the data flip-flop blocks 101, 102,
, 108 states are determined, and the number of delay stages up to outputs 11, 12, 13, 14 can be arbitrarily selected.

4 shows the control inputs 7,8,9 in the truth table of FIG.
Is a timing chart when DL0 = "1", DL1 = "0", DL2 = "1", and shows that the number of delay stages is 5D. However, 1D represents a delay of one stage.

〔The invention's effect〕

As described above, according to the present invention, by actively utilizing the "data extraction" of the master / slave type data flip-flop, the multiplexer, which is indispensable in the conventional circuit, and the output of each stage are connected to the multiplexer. Since it is possible to eliminate the wiring for doing so, there is an effect that the area occupied by the LSI can be greatly reduced.

The operation speed is determined by the propagation delay time when the data flip-flops of the data flip-flops are cascade-connected, but it is not necessary to take the output of each data flip-flop block to the outside. Is possible.

[Brief description of drawings]

1 is a block diagram showing an embodiment of the present invention, FIGS. 2 (a) to 2 (c) are operation explanatory diagrams of the data flip-flop shown in FIG. 1, and FIG. 3 shows the operation of FIG. A truth table shown in FIG. 4, FIG. 4 is a timing chart showing the operation of FIG.
FIG. 5 is a circuit diagram showing details of the control circuit 15 of FIG. 1, FIG. 6 is a block diagram showing a first example of the prior art, and FIG. 7 is a timing chart showing the operation of FIG. FIG. 8 is a truth table showing the operation of FIG. 6, FIG. 9 is a block diagram showing a second conventional example, and FIG. 10 is a timing chart showing the operation of FIG. 1-4 ... Input data, 5,6 ... Clock, 7-9 ...
Control input, 11-14 ... Output data, 15 ... Control circuit, 10
1-108 …… Data flip-flop block, 200 ……
Data flip-flops, 201,202 ... Data latches, 5
01 ~ 503 ... Inverter, 101a, 101b, 102a, 102b, 103a, 10
3b, 104a, 104b, 105a, 105b, 106a, 106b, 107a, 107b, 108a, 10
8b ... OR circuit, 601 ... clock, 602 ... input data,
603 to 605 ... Selection input, 606 ... Output data, 607 to 613
... Data flip-flop block, 614 ... Multiplexer, 901 ... Input data, 902 ... Select input, 903
...... Clock, 904 …… Output data, 905 …… Counter,
906 ... Logic gate, 907 ... Adder, 908 ... Multiplexer, 909 ... RAM, 910 ... Control circuit, 911 ... Data flip-flop.

Claims (1)

[Claims] 1. A master / slave type data flip-flop for inputting first and second clocks is arranged in m bits × n stages (m and n are both positive integers), and the first stage m
Connect the bit data input to the m-bit input terminal
The m-bit data input of the subsequent stages is connected to the m-bit data output of the previous stage, and the m-bit data output of the nth stage is connected
From the clock and control circuit of the first phase to the first clock input of the m data flip-flops of the i-th stage (i is a positive integer from 1 to n) connected to the output terminal of the bit. Of the second phase clock and the i-th signal from the control circuit are connected to the second clock input of the m-th data flip-flop of the i-th stage by connecting the OR signal output to the i-th control signal output of
A FIFO including an m-bit × n-stage shift register formed by connecting an OR signal output with an n-th control signal output, and a control circuit for providing the i-th control signal output.
(First In First Out) circuit.