JPH0748518B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0748518B2 JPH0748518B2 JP17761587A JP17761587A JPH0748518B2 JP H0748518 B2 JPH0748518 B2 JP H0748518B2 JP 17761587 A JP17761587 A JP 17761587A JP 17761587 A JP17761587 A JP 17761587A JP H0748518 B2 JPH0748518 B2 JP H0748518B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon layer
- aluminum layer
- forming
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 title description 5
- 239000010410 layer Substances 0.000 claims description 75
- 229910052782 aluminium Inorganic materials 0.000 claims description 30
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 30
- 239000011229 interlayer Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 238000007743 anodising Methods 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229960000583 acetic acid Drugs 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012362 glacial acetic acid Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に多層配線構
造を有する半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a multilayer wiring structure.
高集積化半導体装置の配線に発生するエレクトロマイグ
レーション等による断線事故を防止するために多結晶シ
リコン層とアルミニウム層の２層構造の配線が用いられ
ている。In order to prevent a disconnection accident due to electromigration or the like which occurs in the wiring of a highly integrated semiconductor device, a wiring having a two-layer structure of a polycrystalline silicon layer and an aluminum layer is used.
第２図（ａ）〜（ｃ）は従来の半導体装置の製造方法の
一例を説明するための工程順に示した半導体チップの断
面図である。FIGS. 2A to 2C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an example of a conventional method for manufacturing a semiconductor device.
まず、第２図（ａ）に示すように、半導体基板１の上に
形成されたシリコン酸化膜２の表面に0.2μｍの多結晶
シリコン層３と1.0μｍのアルミニウム層４を順次堆積
する。次に、アルミニウム層４の表面の光反射によりホ
トレジスト膜のパターン形状が変形するのを防ぐため、
アルミニウム層４の上に薄い非晶質シリコン層９をスパ
ッタリング法等により形成する。次に、シリコン層９の
上に選択的に設けたホトレジスト膜（図示せず）をマス
クとしてシリコン層９とアルミニウム層４と多結晶シリ
コン層３を順次エッチングして下層配線を形成する。First, as shown in FIG. 2A, a 0.2 μm polycrystalline silicon layer 3 and a 1.0 μm aluminum layer 4 are sequentially deposited on the surface of a silicon oxide film 2 formed on a semiconductor substrate 1. Next, in order to prevent the pattern shape of the photoresist film from being deformed by the light reflection on the surface of the aluminum layer 4,
A thin amorphous silicon layer 9 is formed on the aluminum layer 4 by a sputtering method or the like. Next, the photoresist layer (not shown) selectively provided on the silicon layer 9 is used as a mask to sequentially etch the silicon layer 9, the aluminum layer 4, and the polycrystalline silicon layer 3 to form a lower wiring.
次に、第２図（ｂ）に示すように、シリコン層９とアル
ミニウム層４との反応により生ずるストレスマイグレー
ションを防止するため、CF4とO2の混合ガスによるドラ
イエッチングが、弗酸，硝酸，氷酢酸の混合液によるウ
エットエッチング法を用いてシリコン層９を除去する。
このとき、アルミニウム層４の直下にある多結晶シリコ
ン層３の側面が露出している為同時にエッチングされて
アンダーカット部５を生ずる。Next, as shown in FIG. 2 (b), in order to prevent stress migration caused by the reaction between the silicon layer 9 and the aluminum layer 4, dry etching using a mixed gas of CF 4 and O 2 is performed using hydrofluoric acid and nitric acid. The silicon layer 9 is removed by a wet etching method using a mixed solution of glacial acetic acid.
At this time, since the side surface of the polycrystalline silicon layer 3 immediately below the aluminum layer 4 is exposed, it is simultaneously etched and an undercut portion 5 is formed.
次に、第２図（ｃ）に示すように、アルミニウム層４を
含む表面に層間絶縁膜７を形成する。次に、層間絶縁膜
７の上にアルミニウム層８を堆積し、選択的にエッチン
グして上層配線を形成する。このとき、アンダーカット
部５のために層間絶縁膜７のステップカバレージが悪く
層間絶縁膜７の上に形成された上層配線に断線部10を生
ずる。Next, as shown in FIG. 2C, an interlayer insulating film 7 is formed on the surface including the aluminum layer 4. Next, an aluminum layer 8 is deposited on the interlayer insulating film 7 and selectively etched to form an upper wiring. At this time, the step coverage of the interlayer insulating film 7 is poor due to the undercut portion 5, and the disconnection portion 10 is generated in the upper layer wiring formed on the interlayer insulating film 7.
上述した従来の半導体装置の製造方法は、アルミニウム
層上のシリコン層をエッチングにて除去する際に、アル
ミニウム層直下の多結晶シリコン層も同時にエッチング
されてアンダーカット部を生じて層間絶縁膜のステップ
カバレージが非常に悪くなり、層間絶縁膜の上に形成し
た上層配線が層間絶縁膜の段差部下部で断線を生ずると
いう問題点がある。In the conventional method for manufacturing a semiconductor device described above, when the silicon layer on the aluminum layer is removed by etching, the polycrystalline silicon layer immediately below the aluminum layer is also etched at the same time to form an undercut portion, and the step of the interlayer insulating film is generated. There is a problem that the coverage becomes very poor and the upper layer wiring formed on the interlayer insulating film is broken below the stepped portion of the interlayer insulating film.
本発明の半導体装置の製造方法は、半導体基板上に設け
た絶縁膜上に多結晶シリコン層及びアルミニウム層を順
次堆積した後前記アルミニウム層の上に光反射防止用の
非晶質シリコン層を形成する工程と、前記非晶質シリコ
ン層の上に塗布してパターニングしたホトレジスト膜を
マスクとして前記非晶質シリコン層と前記アルミニウム
層および前記多結晶シリコン層を順次エッチングして下
層配線を形成する工程と、前記ホトレジスト膜を除去し
た後、前記非晶質シリコン層をエッチングして除去する
工程と、前記アルミニウム層の表面を陽極酸化してアル
ミナ膜を形成し且つ前記非晶質シリコン層のエッチング
により生じた前記多結晶シリコン層のアンダーカット部
を前記アルミナ膜で埋める工程と、前記アルミナ膜を含
む表面に層間絶縁膜を形成する工程と、前記層間絶縁膜
の上に金属層を堆積し選択的にエッチングして上層配線
を形成する工程とを含んで構成される。According to a method of manufacturing a semiconductor device of the present invention, a polycrystalline silicon layer and an aluminum layer are sequentially deposited on an insulating film provided on a semiconductor substrate, and then an amorphous silicon layer for preventing light reflection is formed on the aluminum layer. And a step of forming a lower wiring by sequentially etching the amorphous silicon layer, the aluminum layer and the polycrystalline silicon layer using the photoresist film coated and patterned on the amorphous silicon layer as a mask. A step of etching and removing the amorphous silicon layer after removing the photoresist film, and forming an alumina film by anodizing the surface of the aluminum layer and etching the amorphous silicon layer. Filling the resulting undercut portion of the polycrystalline silicon layer with the alumina film, and performing interlayer insulation on the surface including the alumina film. Forming a configured and forming a deposited metal layer is selectively etched to upper wiring on the interlayer insulating film.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｃ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.
まず、第１図（ａ）に示すように、半導体基板１の表面
に形成されたシリコン酸化膜２の表面に0.2μｍの多結
晶シリコン層３及び1.0μｍのアルミニウム層４を順次
堆積し、選択的に順次エッチングして多結晶シリコン層
３とアルミニウム層４の２層構造の下層配線を設ける。
このとき、前述の従来例にて述べた通り、下層配線を形
成する為のホトレジストパターン（図示せず）を形成す
る際のアルミニウム層４からの光の反射を防止するため
に設けた非晶質のシリコン層（図示せず）を除去する時
に多結晶シリコン層の側面もエッチングされ、アルミニ
ウム層４の下にアンダーカット部５ができる。First, as shown in FIG. 1A, a 0.2 μm polycrystalline silicon layer 3 and a 1.0 μm aluminum layer 4 are sequentially deposited on the surface of a silicon oxide film 2 formed on the surface of a semiconductor substrate 1, and selected. Of the polycrystalline silicon layer 3 and the aluminum layer 4 to form a lower layer wiring having a two-layer structure.
At this time, as described in the above-mentioned conventional example, an amorphous material provided to prevent reflection of light from the aluminum layer 4 when forming a photoresist pattern (not shown) for forming the lower layer wiring. When the silicon layer (not shown) is removed, the side surface of the polycrystalline silicon layer is also etched, and an undercut portion 5 is formed under the aluminum layer 4.
次に、第１図（ｂ）に示すように、アルミニウム層４の
表面を陽極酸化法等により酸化し、約0.4μｍのアルミ
ナ膜６を形成する。このとき、アルミニウム層４の直下
のアンダーカット部５は完全にアルミナ膜６で埋められ
る。Next, as shown in FIG. 1B, the surface of the aluminum layer 4 is oxidized by an anodic oxidation method or the like to form an alumina film 6 of about 0.4 μm. At this time, the undercut portion 5 immediately below the aluminum layer 4 is completely filled with the alumina film 6.
次に、第１図（ｃ）に示すように、プラズマCVD法によ
りシリコン酸化膜を0.6μｍ堆積して層間絶縁膜７を形
成する。このとき、アンダーカット部５はアルミナ膜６
で埋められている為に、層間絶縁膜７のステップカバレ
ージは良好となる。次に、層間絶縁膜７の上にアルミニ
ウム層８を堆積し、選択的にエッチングして上層配線を
形成する。Next, as shown in FIG. 1C, a silicon oxide film is deposited to a thickness of 0.6 μm by a plasma CVD method to form an interlayer insulating film 7. At this time, the undercut portion 5 is formed of the alumina film 6
Since it is filled with, the step coverage of the interlayer insulating film 7 becomes good. Next, an aluminum layer 8 is deposited on the interlayer insulating film 7 and selectively etched to form an upper wiring.
以上説明したように本発明は、アルミニウム層上に形成
したシリコン層を除去する際にアルミニウム層直下の多
結晶シリコン層がエッチングされて生じたアンダーカッ
ト部をアルミニウム層の表面に形成したアルミナ膜で埋
めることにより、層間絶縁膜のステップカバレージが良
くなり、その結果、上層配線の断線を防止することがで
きるという効果を有する。INDUSTRIAL APPLICABILITY As described above, the present invention is an alumina film having an undercut portion formed on the surface of an aluminum layer, which is formed by etching the polycrystalline silicon layer immediately below the aluminum layer when removing the silicon layer formed on the aluminum layer. By filling, the step coverage of the interlayer insulating film is improved, and as a result, disconnection of the upper layer wiring can be prevented.
第１図（ａ）〜（ｃ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図、第２図
（ａ）〜（ｃ）は従来の半導体装置の製造方法を説明す
るための工程順に示した半導体チップの断面図である。 １…半導体基板、２…シリコン酸化膜、３…多結晶シリ
コン層、４…アルミニウム層、５…アンダーカット部、
６…アルミナ膜、７…層間絶縁膜、９…シリコン層、10
…断線部。1 (a) to 1 (c) are sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIGS. 2 (a) to 2 (c) are conventional semiconductor device manufacturing methods. FIG. 6 is a cross-sectional view of the semiconductor chip in the order of steps for explaining. 1 ... Semiconductor substrate, 2 ... Silicon oxide film, 3 ... Polycrystalline silicon layer, 4 ... Aluminum layer, 5 ... Undercut portion,
6 ... Alumina film, 7 ... Interlayer insulating film, 9 ... Silicon layer, 10
… Broken wire.
Claims (1)
リコン層及びアルミニウム層を順次堆積した後前記アル
ミニウム層の上に光反射防止用の非晶質シリコン層を形
成する工程と、前記非晶質シリコン層の上に塗布してパ
ターニングしたホトレジスト膜をマスクとして前記非晶
質シリコン層と前記アルミニウム層および前記多結晶シ
リコン層を順次エッチングして下層配線を形成する工程
と、前記ホトレジスト膜を除去した後前記非晶質シリコ
ン層をエッチングして除去する工程と、前記アルミニウ
ム層の表面を陽極酸化してアルミナ膜を形成し且つ前記
非晶質シリコン層のエッチングにより生じた前記多結晶
シリコン層のアンダーカット部を前記アルミナ膜で埋め
る工程と、前記アルミナ膜を含む表面に層間絶縁膜を形
成する工程と、前記層間絶縁膜の上に金属層を堆積し選
択的にエッチングして上層配線を形成する工程とを含む
ことを特徴とする半導体装置の製造方法。1. A step of sequentially depositing a polycrystalline silicon layer and an aluminum layer on an insulating film provided on a semiconductor substrate and then forming an amorphous silicon layer for preventing light reflection on the aluminum layer, Forming a lower wiring by sequentially etching the amorphous silicon layer, the aluminum layer and the polycrystalline silicon layer using the photoresist film patterned and applied on the amorphous silicon layer as a mask; and the photoresist film And then removing the amorphous silicon layer by etching, and the polycrystalline silicon produced by etching the amorphous silicon layer by forming an alumina film by anodizing the surface of the aluminum layer. Filling the undercut portion of the layer with the alumina film, forming an interlayer insulating film on the surface including the alumina film, The method of manufacturing a semiconductor device which comprises a step of forming a deposited metal layer is selectively etched to upper wiring on the interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17761587A JPH0748518B2 (en) | 1987-07-15 | 1987-07-15 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17761587A JPH0748518B2 (en) | 1987-07-15 | 1987-07-15 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6420642A JPS6420642A (en) | 1989-01-24 |
| JPH0748518B2 true JPH0748518B2 (en) | 1995-05-24 |
Family
ID=16034102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17761587A Expired - Lifetime JPH0748518B2 (en) | 1987-07-15 | 1987-07-15 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0748518B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102811548A (en) * | 2011-05-31 | 2012-12-05 | 精材科技股份有限公司 | Circuit structure and its manufacturing method |
-
1987
- 1987-07-15 JP JP17761587A patent/JPH0748518B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102811548A (en) * | 2011-05-31 | 2012-12-05 | 精材科技股份有限公司 | Circuit structure and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6420642A (en) | 1989-01-24 |
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