JPH0748632B2 - Digital signal processing integrated circuit - Google Patents

Description

The present invention relates to a digital signal processing integrated circuit, and more particularly to a digital signal processing integrated circuit having a delay adjusting function inside.

[Conventional technology]

In recent years, the digitization of image processing has progressed rapidly,
Accompanying this, the integration of digital signal processing circuits has become active. At that time, various conditions are imposed on the sampling frequency related to the processing of the digital signal, and the configuration shown in FIGS. 4 and 5 has been used for its optimization. A conventional example will be described below with reference to FIGS. 4 and 5.

FIG. 4 shows an example of a television signal processing circuit by digital signal processing. The digitized luminance signal (hereinafter, simply referred to as luminance signal) is a signal processing circuit whose operating frequency is given by the sampling frequency nf.
A brightness signal processing circuit system 13 constituted by 10 performs aperture correction, noise reduction, contrast control, and the like, for example. The output of the signal processing circuit 10 is input to the post-processing circuit 16. On the other hand, a digitized color signal (hereinafter, simply referred to as a color signal) is formed by a signal processing circuit 11 whose operating frequency is given by a sampling frequency f and a signal processing circuit 12 which converts the sampling frequency rate. By the circuit system 14,
For example, color demodulation and hue control are performed. Signal processing circuit
The output of 12 is input to the post-processing circuit 16 like the luminance signal.
In the post-processing circuit 16, for example, a luminance signal / color signal mixing circuit outputs the image composite signal. In such a television signal processing circuit, the signal processing circuits 10 to 12 and the post-processing circuit 16 are constituted by a digital integrated circuit.

At this time, the sampling frequency in each signal processing is
It is set by the frequency band of the luminance signal and the color signal. In the color signal processing circuit system 14, for example, in the case of the NTSC system in which three primary colors are simultaneously transmitted in a color television, the sampling frequency of the color signal is a color subcarrier frequency (fsc≈3.5).
8MHz), but in the luminance signal processing circuit system 13 the frequency band is 4.5MHz in the case of the NTSC system, so set the same as the sampling frequency of the color signal processing circuit system 14. However, in order to obtain high-definition image quality, it is necessary to expand the frequency band of the luminance signal and set the sampling frequency of the luminance signal processing circuit system 13 higher than that of the color signal processing circuit system 14. Further, in the mixing circuit of the luminance signal and the chrominance signal in the post-processing circuit 16, it is necessary to set the sampling frequencies of both signals to the same condition.
As shown in the figure, the sampling frequency f is set to the output from the color signal processing circuit 17 as the sampling frequency of the luminance signal processing system 13.
Sampling frequency rate conversion circuit for rate conversion to nf
18 are provided. Generally, in a sampling frequency rate conversion circuit, when converting only the frequency rate of a sampled digital signal, n times (n
Can be more easily realized by using a clock switch of an integer greater than or equal to 2), and the hardware is simpler than the case of performing fractional multiple rate conversion. Therefore, the sampling frequency ratio before and after conversion is, for example, f and nf. It is set to an integral multiple.

Further, the signal processing circuit 12 composed of a digital integrated circuit
In, when converting the sampling frequency rate,
As shown in FIG. 5, the input signal is input to the signal processing circuit 17 through the input terminal group 7 and processed, and then the sampling frequency is rate-converted by the sampling frequency rate conversion circuit 18, and the output signal is output through the output terminal group 8. Is output.

[Problems of conventional technology]

In the conventional digital signal processing of images, for example, when the sampling frequency of the output section of the color signal processing circuit system 14 is rate-converted to the sampling frequency of the luminance signal processing circuit system 13, the normal luminance signal processing circuit system 13 The number of processing steps is larger than that of the color signal processing circuit system 14, and in addition, the motion information of the image is extracted from the luminance signal in order to realize high image quality, which further increases the processing steps. Therefore, the processing time of the color signal processing circuit system 14 is relatively faster than that of the luminance signal processing circuit system 13. Therefore, in order to match the timing of the output signals from these signal processing systems,
As shown in the figure, a delay adjusting circuit 15 is provided at the output of the color signal processing circuit system 14.

Conventionally, such a delay adjustment circuit 15 is provided outside a semiconductor substrate on which a signal processing circuit is mounted and requires a general-purpose logic integrated circuit such as a shift register circuit. Further, when the delay adjustment circuit is incorporated after the sampling frequency rate conversion in the digital signal processing integrated circuit as described above, since the sampling frequency is high, the power consumption is increased and the delay adjustment amount is limited, so that the degree of freedom is reduced. I was only able to make small adjustments.

[Object of the Invention]

An object of the present invention is to reduce hardware related to signal processing in a digital signal processing integrated circuit, enable integration on the same semiconductor substrate, and reduce power consumption.

[Structure of Invention]

A digital signal processing integrated circuit according to the present invention includes an input terminal group for inputting a digital signal sampled at a first sampling frequency, a signal processing circuit having an operating frequency set at the first sampling frequency, and the signal processing circuit. Frequency conversion circuit for converting the sampling frequency of the signal sampled by the first sampling frequency into a second sampling frequency higher than the first sampling frequency, and the second sampling frequency. In a digital signal processing integrated circuit having an output terminal group for outputting a digital signal sampled by the same semiconductor integrated circuit substrate, the first terminal is provided between the input terminal group and the sampling frequency rate conversion circuit. To the sampling frequency A second delay adjustment circuit in which the operating frequency is set, and a second operating frequency is set between the sampling frequency rate conversion circuit and the output terminal group by the second sampling frequency. It is characterized by having a delay adjustment circuit.

That is, according to the present invention, in a digital signal processing integrated circuit, two delay adjusting circuits having different operating frequency characteristics are provided before and after a sampling frequency rate converting circuit, and a delay adjusting circuit having a low operating frequency is provided before the sampling frequency rate converting circuit. The circuit is characterized in that the digital signal is adjusted to a value close to a desired delay amount, and the delay amount is finely adjusted in a subsequent stage by a delay adjusting circuit having a high operating frequency.

〔Example〕

One embodiment of the present invention is shown in FIG. In the digital signal processing integrated circuit 1, the input terminal group 7 and the output terminal group 8
A signal processing circuit 2 and a sampling frequency rate conversion circuit 3 that perform signal processing and conversion of sampling frequency are connected in series between the two. Further, between the sampling frequency rate conversion circuit 3 and the input terminal group 7, a delay adjustment circuit 4 to which an operating frequency is given at the first frequency f is provided.
Between the sampling frequency rate conversion circuit 3 and the output terminal group 8, a delay adjustment circuit 5 to which an operation frequency is given at a second frequency nf which is an integral multiple of the first frequency is connected, and the delay adjustment circuit 4 is connected. And 5 are connected to the control circuit 6,
It is controlled by a signal input through the control input terminal group 9.

In FIG. 1, the sampling frequency rate conversion circuit 3
Thus, for example, when the first sampling frequency f is rate-converted to the second sampling frequency nf (where n is an integer of 2 or more), the operating frequency of the delay adjusting circuit 4 is given by f and the delay adjusting circuit 5 The operating frequency is given by nf. At this time, set the desired delay adjustment range x And the delay adjustment range of the delay adjustment circuit 5 is D and the delay adjustment range of the delay adjustment circuit 4 is D ', the respective delay adjustment ranges are Under these conditions, the delay amount can be adjusted within the desired delay adjustment range x. Therefore, when the delay adjustment of the signal output sampled at the sampling frequency of nf is performed by the delay adjustment circuit operating at the sampling frequency of nf as in the conventional case, the required delay adjustment range D ″ is 0 ≦ D ″ ≦ M − (4) At this time, assuming that the maximum delay adjustment amount of the delay adjustment circuit 5 is D _MAX and the maximum delay adjustment amount in the conventional case is D ″ _MAX , from the formula (2) From the equation (4), D ″ _MAX = M− (6) From the conditions of the equations (5), (6) and (1), D _MAX << D ″ _MAX − (7) According to this, the delay adjustment circuit 5 operating at a frequency of nf necessary to obtain a desired delay adjustment range
The delay adjustment range can be greatly reduced. here,
In the present invention, the delay adjustment circuit 4 that operates at the frequency of f in which the delay adjustment range is set under the condition of the expression (3) is required at the front of the sampling frequency rate conversion circuit 3. Since the delay amount is n times the unit delay amount in the delay adjustment circuit 5, that is, the unit delay amount of the output signal, the hardware scale can be reduced as described above. Further, in the present invention, the delay adjustment is performed at a frequency as low as 1 / n times the sampling rate of the output signal, so that the power consumption can be reduced and it is suitable for an integrated circuit.

FIG. 2 is an example in which the digital signal processing integrated circuit of the present invention is applied to the television signal processing circuit by the conventional digital signal processing of FIG.

FIG. 2 is a signal processing circuit constituting a color signal processing circuit system 14 of a conventional television signal processing circuit by digital signal processing.
12. The digital signal processing integrated circuit 1 of the present invention is applied. The output signal from the color signal processing circuit system 24 has already been timing-adjusted with the output signal from the luminance signal processing circuit system 13, so both output signals are directly processed by the post-processing circuit.
Entered in 16. Therefore, it is not necessary to specially provide a delay adjusting means such as the delay adjusting circuit 15 shown in FIG. 4 as a conventional example.

Next, FIG. 3 shows an example of a concrete constituent means of the delay adjusting circuit in the digital signal processing integrated circuit of the present invention. Cascaded latch groups 31 to 35 and multiplexer channels to which output signals from the respective latch output points are input
The control circuit 6 controls the multiplexer channel 36 to determine which latch output is the delay adjustment circuit.
The delay is adjusted by selecting whether to take it out as the output of 30. With such a configuration, there is no need for a delay adjusting means such as a logic integrated circuit, which has been separately provided outside the semiconductor substrate on which the digital signal processing integrated circuit is mounted, and the delay adjusting circuit is combined with the digital signal processing integrated circuit. It can be formed on the same semiconductor substrate.

〔The invention's effect〕

According to the present invention, in a digital signal processing integrated circuit, a delay adjusting circuit is provided before and after a sampling frequency rate converting circuit for rate converting a sampling frequency for sampling a digital signal, and a delay adjusting circuit in a preceding stage performs a coarse adjustment of a delay amount, By performing the fine adjustment in the subsequent stage, the scale of the hardware of the digital signal processing integrated circuit can be reduced and the power consumption required for the signal processing can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the configuration of a digital signal processing integrated circuit according to the present invention, FIG. 2 is a block diagram showing an application example of the present invention to a television signal processing circuit, and FIG. FIG. 4 is a block diagram showing a specific example of the delay adjustment circuit, FIG. 4 is a block diagram showing an example of a conventional television signal processing circuit, and FIG. 5 is a block diagram showing the configuration of a conventional signal processing circuit. 1 ... Digital signal processing integrated circuit, 2,10-12,17,22 ...
… Signal processing circuit, 3,18 …… Sampling frequency rate conversion circuit, 4,5,15,30 …… Delay adjustment circuit, 6 …… Control circuit, 14,24 …… Color signal processing circuit system, 7 …… Input Terminal group, 1
6 ... Post-processing circuit, 8 ... Output terminal group, 31-35 ... Latch circuit, 9 ... Control input terminal group, 36 ... Multiplexer channel, 13 ... Luminance signal processing circuit system.

Continuation of front page (56) Reference JP 59-105712 (JP, A) JP 59-185422 (JP, A) JP 61-195015 (JP, A) JP 60-75117 (JP , A) JP 60-160720 (JP, A) JP 62-143588 (JP, A) JP 60-68419 (JP, A) JP 49-131548 (JP, A) JP 60-89773 (JP, A) Actually opened 62-57835 (JP, U)

Claims (1)

[Claims] 1. A group of input terminals for inputting a digital signal sampled at a first sampling frequency, a signal processing circuit having an operating frequency set at the first sampling frequency, and an output of the signal processing circuit. age,
A sampling frequency rate changing circuit for converting a sampling frequency of a signal sampled by the first sampling frequency into a second sampling frequency;
The operating frequency is set by the output terminal group for outputting the digital signal sampled at the second sampling frequency, and the first sampling frequency connected between the sampling frequency rate conversion circuit and the input terminal group. A first delay adjustment circuit and a second delay adjustment circuit whose operating frequency is set by the second sampling frequency connected between the sampling frequency rate conversion circuit and the output terminal group are the same semiconductor. A digital signal processing integrated circuit characterized by being provided on an integrated circuit board.