JPH0748664B2 - Serial-parallel converter - Google Patents

Description

The present invention relates to a circuit of a serial-parallel converter that converts a serial data signal into a parallel data signal.

[Outline of Invention]

The present invention relates to a serial-parallel converter for converting a serial data signal into a parallel data signal, wherein a plurality of latch circuits each receiving at least one series of serial data signals and a plurality of master slaves outputting a latch control signal of the latch circuits. One of the two latch circuits that has a shift register formed of a flip-flop (hereinafter abbreviated as FF) and latches the serial data signals that are adjacent in time series among the serial data signals. By using the master output of the flip-flop as a latch control signal and the other latch circuit as a slave output as a latch control signal, the number of constituent elements of the shift register is halved, and a low-power, high-speed serial-parallel converter is provided. It will be realized.

[Conventional technology]

The circuit of the conventional serial-parallel converter is a shift register circuit composed of n bits of FFs as shown in FIG.
The serial data signal was input to the FF in the first stage of the shift register, sequentially transferred by the transfer clock, and output as n-bit parallel data to the output group of the FF corresponding to each bit.

[Problems to be Solved by the Invention]

However, in the above-mentioned conventional technique, n transfer clocks are required to transfer an n-bit serial signal, and when serial-parallel conversion is performed at high speed, the serial-parallel conversion speed is determined by the transfer speed of the shift register. However, there is a problem that the serial-parallel conversion speed cannot be increased.

Further, in the case of serial-parallel conversion of serial signals of two or more systems, shift registers corresponding to the number of series of serial signals are required, and there is a problem that the number of circuit constituent elements significantly increases as the number of series of serial signals increases. . Therefore, the present invention solves such a problem, and an object of the present invention is to provide a high-speed, highly integrated, low-power serial-parallel converter that can be used as a bidirectional shift register.

[Means for Solving the Problems]

In a serial-parallel converter for converting a serial data signal into a parallel data signal, a plurality of latch circuits for inputting at least one series of serial data signals and a plurality of master slave type flip-flops for outputting a latch control signal of the latch circuit are provided. Of the serial data signals, one of the two latch circuits that latches the serial data signals that are adjacent in time series among the serial data signals, one of the latch circuits uses the master output of the flip-flop as a latch signal. The other latch circuit uses the slave output as a latch signal.

[Action]

According to the above configuration of the present invention, the latch control signal is transferred in the shift register by the shift clock. The latch control signal is connected from the master and slave outputs of the FF forming the shift register to the control input of the corresponding latch, and the serial data signal is held only for the latch selected by the latch control signal.

A shift register that transfers a latch control signal when converting a serial signal consisting of n pieces of data into a parallel signal by allocating a master signal and a slave output of the FF that constitute the shift register to a control signal for each 1-bit latch Can be composed of n / 2 FFs.

Therefore, since a serial signal composed of n pieces of data can be serial-parallel converted by n / 2 transfer clocks, the serial-parallel conversion speed can be substantially doubled.

Also, serial data signals of a plurality of systems can be serial-parallel converted by increasing only the number of latch groups without changing the number of shift registers, and high integration can be achieved.

[Embodiment] FIG. 1 is a circuit diagram in an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the embodiment.

The serial data signal is input to the serial signal input terminal 1 and connected to the latch group 9 including n latches. The latch control input signal is input to the shift register input terminal,
Transferred by a shift register composed of n / 2 FF4s. The master and slave outputs of FF4, which constitutes the shift register, become the latch control signals for one latch. The 1-bit latch control signal in FIG. 2 is the signal 5 in FIG. 1 and the 2-bit latch control signal is the signal 6 in FIG.
The 3-bit latch control signal corresponds to the signal 7 in FIG. 1 and the n-bit latch control signal corresponds to the signal 8 in FIG.

At the falling edge of the 1-bit latch control signal output from the shift register, the 1-bit serial signal input from the serial signal input terminal 1 is held in the 1-bit latch of the latch group 9. The latch control signal is transferred in the shift register by n / 2 transfer clocks, causes the corresponding latch group 9 to sequentially hold the serial data signals, completes the serial-parallel conversion of the n serial data signals, and outputs the parallel output terminals. Group 10
Is output to.

The upper limit of the serial-parallel conversion speed depends on the transfer speed of the shift register. According to the circuit diagram shown in FIG. 1, n / 2 transfer clocks are used for serial-parallel conversion of n serial data signals. Done, the upper limit of the effective conversion speed is doubled.

Considering the same serial-parallel conversion operation, according to the present invention,
The transfer clock frequency is halved, which reduces the current consumption by half and realizes a lower power serial-parallel converter.

Although the latch group 9 in FIG. 1 is composed of D type latches, the present invention can be realized as long as the latch group 9 performs signal holding operation by the latch control signal.

As described above, according to the present invention, the master output and the slave output of the shift register are used as the control signals of the latch circuit as they are. Therefore, as shown in FIG. Therefore, even if the input clock pulse width fluctuates, the transfer clock width does not fluctuate, and stable shift register operation is possible even at high speeds. Since the latch control signal becomes active from the signal immediately before the corresponding serial signal, the time to open the gate of the latch circuit is irrelevant to the latch operation, and only the time to close the gate (falling edge of the latch control signal). Determine the timing of the latch operation. Therefore, even if the latch circuit corresponding to LS75 is used, the same result as when the substantially D-type flip-flop is used as the latch circuit can be obtained.

FIG. 4 shows another embodiment according to the present invention. 4 in FIG. 9 is 2
It is a system latch, and it is possible to simultaneously hold two systems of serial data signals input from the serial data signal input terminal by a latch control signal. The embodiment of FIG. 4 is 2
It is needless to say that it is possible to easily realize serial data signals of two or more systems by increasing the number of systems of latches, though it is the case of serial data signals of two systems.

When converting serial data signals of a plurality of systems as shown in FIG. 4, serial / parallel conversion can be performed only by increasing the number of latch groups 9 without decreasing the serial / parallel conversion speed.

In the present invention shown in FIG. 4, the transfer clock is input to the shift register transfer clock input terminal at twice the frequency of the transfer clock shown in FIG. 2, and is connected to the shift register through the 1/2 frequency dividing circuit.

FIG. 5 shows another embodiment according to the present invention. By using a bidirectional shift register as the shift register for transferring the latch control signal and giving a high or low level to the transfer direction selection terminal, it is possible to reverse the order of the parallel data signals after serial-parallel conversion.

The terminal 13 in FIG. 5 becomes a shift register input terminal when the transfer direction selection terminal 12 is set low.

In the case of the bidirectional shift register, the load on each element increased as the number of constituent elements increased, and high-speed operation could not be performed as compared with the unidirectional shift register. According to the present invention, by using the bidirectional shift register as the shift register of the serial converter, high speed bidirectional serial-parallel conversion can be performed. When the transfer speed of the bidirectional shift register is set to about 80% of the transfer speed of the unidirectional shift register, the transfer speed is doubled according to the present invention, and therefore about 160% of the transfer speed of the conventional serial-parallel converter. It is possible to realize a bidirectional serial-parallel converter having a conversion speed of.

〔The invention's effect〕

As described above, according to the present invention, the serial-parallel conversion speed is higher than that of the conventional example shown in FIG. 3, and the pulse number of the transfer clock is reduced in consideration of the same serial-parallel conversion operation.
It enables a lower power serial-parallel converter.

Therefore, for example, thermal head driver and LCD, L
When the present invention is applied to a display driver used for ED, EL, PDP, etc., high-speed operation becomes possible, which enables a high-density, large-screen, low-power system.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a serial-parallel converter of the present invention. FIG. 2 is a timing chart showing the operation of the serial-parallel converter of the present invention. FIG. 3 is a circuit diagram of a conventional serial-parallel converter. 4 and 5 are circuit diagrams showing an embodiment of the serial-parallel converter of the present invention. 1 ... Serial data signal input terminal 2 ... Shift register input terminal 3 ... Transfer clock input terminal 4 ... Flip-flop 5,6,7,8 ... Latch control circuit 9 ... Latch group 10 ... Parallel output terminal group 11 ... 1/2 minute Circulation circuit 12 ... Transfer direction selection pin 13 ... Shift register input pin

Claims (1)

[Claims] 1. A serial-parallel converter for converting a serial data signal into a parallel data signal, wherein a plurality of latch circuits for receiving at least one series of serial data signals and a plurality of masters for outputting a latch control signal of the latch circuits. A slave flip-flop has a shift register, and one latch circuit of any two latch circuits that latch adjacent serial data signals in time series among the serial data signals is one master circuit of the flip-flop. The serial-parallel converter, wherein the output is the latch control signal, and the other latch circuit uses the slave output as the latch control signal.