JPH0749966B2 - Measuring device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of measurement accuracy of a measuring device for measuring temperature, pressure, etc., and particularly, it is possible to adjust absolute value accuracy when measuring by digital processing such as an electronic thermometer. It is what

[0002]

2. Description of the Related Art Conventionally, an electronic thermometer using a temperature sensitive resistance such as a thermistor has a reference resistance which shows a substantially constant resistance value without being affected by temperature change in a measurement temperature range,
Ratio of resistance value of reference resistance and resistance value of temperature sensitive resistance (resistance ratio)
Is obtained and converted (decoded) into temperature. That is, the conventional electronic thermometer has a thermistor, a reference resistance, and a variable resistor for initial adjustment, and switches the thermistor and the reference resistance to generate a pulse signal having a frequency based on each resistance value. A circuit, a frequency dividing circuit that divides the source oscillation clock to generate a window pulse having a predetermined pulse width, and counts a reference pulse signal based on the reference resistance for a counting time corresponding to the predetermined pulse width, and also after resetting. A counter that counts the detection pulse signal based on the temperature-sensitive resistance over the counting time, calculates a ratio (resistance ratio) between the count value of the reference pulse signal and the count value of the detection pulse signal, and then refers to the reference memory. Then, the resistance ratio is converted into temperature and the temperature is displayed.

The electronic thermometer having such a structure operates as follows. First, in the first phase, the resistance value-frequency conversion circuit selects the reference resistance and the initial adjustment variable resistor to generate the reference pulse signal having the series combined resistance value of both. The reference pulse signal is counted by the counter for a certain counting time determined by the frequency dividing circuit, and the count value (first count value) of the reference pulse signal is temporarily stored by the storage means. Then the counter is reset.
Next, in the second phase, the resistance value-frequency conversion circuit selects the thermistor and generates a temperature detection pulse signal having a frequency corresponding to the resistance value. This temperature detection pulse signal is also counted by the counter for a certain counting time determined by the frequency dividing circuit, and the count value (second count value) of the temperature detection pulse signal is obtained. Then, the ratio between the temporarily stored first count value and the second count value is calculated, and the temperature is displayed by temperature conversion.

In order to obtain the temperature display from the ratio between the resistance value of the reference resistance and the resistance value of the thermistor as described above, since the conversion table for each thermometer has constant conversion data, a certain constant temperature is obtained. At room temperature, the resistance ratio must be a constant value for all thermometers, but in reality, there are individual differences in resistance values (manufacturing variations in resistance values) between the reference resistance and thermistor. The ratio is not constant. Therefore, in order to keep the resistance ratio constant, the variable resistor for initial adjustment is moved in the inspection process in the manufacturing stage to increase or decrease the combined series resistance value with the reference resistance so that the resistance ratio is adjusted to a constant value. (Absolute value precision adjustment).

[0005]

However, the above-mentioned electronic thermometer has the following problems.

In the inspection process, placing an electronic thermometer under a constant temperature and manually adjusting the variable resistance value so that the temperature display value becomes a constant temperature requires complicated labor, and particularly, For thermometers that require strict accuracy, fine adjustment work requires skill. Therefore, the productivity remains low, which is an obstacle to cost reduction.

Further, in the above-mentioned electronic thermometer, the variable resistance value is inferior to the fixed resistance value in the environment resistance, is prone to change over time (change in resistance value), and the reliability of temperature display during use is poor.

Furthermore, since the variable resistor has a movable portion, it is not suitable for semiconductor integration of the entire circuit system, and the resistance value-frequency conversion circuit, frequency dividing circuit, and counter cannot be integrated into one chip, and the variable resistor Must be mounted on the board as an external discrete component. Therefore, when applied to a thermometer, etc., it becomes an obstacle to miniaturization,
An increase in the number of parts leads to an increase in manufacturing cost.

As a technique for solving the above-mentioned problems, the applicant of the present application has previously disclosed an electronic thermometer in Japanese Patent Application No. 59-17499 (Japanese Patent Laid-Open No. 60-161538). The electronic thermometer disclosed in this application has a resistance value that is switchably generated between a reference pulse signal having a frequency based on the resistance value of a reference resistance and a temperature detection pulse signal having a frequency based on the resistance value of a temperature-sensitive resistance.
It has a frequency conversion circuit and a counting circuit that counts the reference pulse signal for a predetermined counting time and counts the temperature detection pulse signal for the predetermined counting time after reset, and has a count value of the reference pulse signal. In an electronic thermometer that displays temperature based on the ratio of the count value of the temperature detection pulse signal, the counting circuit is a counting circuit with a set, and the counting circuit has a set before measuring either the reference pulse signal or the temperature detection pulse signal. The counter circuit has an initial value setting circuit for setting resistance value variation correction data as an initial value.

In this electronic thermometer, it is also necessary to make the ratio of the reference resistance count value and the temperature sensitive resistance count value constant at a specific temperature without variation among products as in the conventional case. , Unlike the conventional method, the resistance ratio between the reference resistance and the temperature-sensitive resistance is not set to a constant value by adjusting the variable resistance value, but the unique resistance value variation correction data is set so that the count ratio becomes a constant value. Is sent to the counting circuit with set when measuring temperature. Whereas the conventional correction method for eliminating the variation in the resistance value is to increase or decrease the resistance value itself in the inspection process (hard permanent correction), the electronic thermometer according to the above application matches the specified temperature and the display temperature in the inspection process. This is the selection of a specific resistance value variation correction data value and the initial value setting (software-based correction) of the counting circuit with a set based on the correction data at the time of temperature measurement. In order to achieve such soft random correction, the conventional counting circuit is changed to a counting circuit with a set, and a resistance unique to the counting circuit with a set is provided prior to either the reference pulse signal or the temperature detection pulse signal. An initial value setting circuit for initializing the value variation correction data is required.

Further, it is not necessary to use a variable resistor for initial adjustment, and even if a reference resistor and a temperature-sensitive resistor having variations in resistance value are used, their resistance ratios can be apparently made constant, It is possible to realize an electronic thermometer that is low in cost, has few adjustment steps, and does not change with time.

By the way, in the electronic thermometer, the count value of the reference pulse signal based on the reference resistance and the count value of the detection pulse signal based on the temperature-sensitive resistance are obtained under the condition that the count times are the same, and the count value is calculated from both count values. After calculating the counting ratio,
The temperature is converted into a temperature corresponding to the counting ratio.
For this reason, a division circuit for calculating the count ratio is essential. If the division circuit is configured with a counter or the like, the circuit becomes very complicated. For this reason, it may be difficult to apply to a thermometer. In addition to the thermometer and the thermometer, there is a demand to apply the above software-like corrections to small pressure gauges having a resistance value-frequency conversion circuit equipped with a pressure-sensitive resistor, etc. Since it is indispensable, the circuit system is likely to be complicated and the formation area tends to be large.

In view of the above problems, an object of the present invention is to make apparent the resistance ratio between a reference resistor and a detection resistor having a variation in resistance value without using a variable resistor for initial adjustment. To realize a measurement device with a simple structure that does not require a division circuit, while assuming that it can provide a constant value, a low cost, a low adjustment process, and a temperature and other measurement device that does not change over time. is there.

[0014]

In order to solve the above-mentioned problems, in the present invention, a reference pulse signal having a frequency based on the resistance value of the reference resistance and a detection in which the resistance value changes in response to temperature, pressure, etc. A resistance value-frequency conversion means for switchably generating a detection pulse signal having a frequency based on the resistance value of a resistor, and one of the reference pulse signal and the detection pulse signal as a first pulse signal and the other as a first pulse signal. Two
The first pulse signal is counted until the target count value is reached, and the second pulse is counted for a count time equal to the time until the count of the first pulse signal reaches the target count value after reset. In a measuring device that counts signals and a measurement device that displays a measurement result based on the observed count value of the second pulse signal over the counting time by the counting device, the counting device is a preset counting device, It is characterized by further comprising correction data setting means for setting resistance value variation correction data as an initial value for the preset type counting means prior to counting the first pulse signal.

[0015]

In the first phase, the first pulse signal is measured by the counting means. The counting time of the first pulse signal is not prescribed in advance to a predetermined time, but the counting value to be counted up is only prescribed as a target counting value. Therefore, the counting time to reach the target count value is determined by counting the first pulse signal.
For example, when the resistance value variation correction data is large, the counting time to reach the target count value is short, and conversely, when the resistance value variation correction data is small, the counting time to reach the target count value is long. Then, in the second phase, the second pulse signal is counted over the counting time determined by the counting means, and the observed count value of the second pulse signal is obtained. Then, the measurement result is displayed based on only this observed count value. In this way, since it is possible to convert to the temperature or the like based on the observed count value of the second pulse signal without calculating the count ratio, the division process is unnecessary. Therefore, it is possible to avoid the complexity of the circuit system and the increase in the size of the formation area. Of course, even if you do not use a variable resistor for initial adjustment and you use a reference resistor or a detection resistor with a variation in resistance value, the resistance ratio between them can be made apparently constant, and adjustment is possible at low cost. It is possible to provide a measuring device that has few steps and does not change with time.

[0016]

Embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a circuit configuration of an electronic thermometer according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a resistance value-frequency conversion circuit 1 in the block diagram of FIG. 1, and FIG. 1 is a circuit diagram showing a part of the initial logic adjusting circuit 9 and the frequency dividing circuit 10 in the block diagram shown in FIG. 1, and FIG. 4 is a time chart showing signals of respective parts of the electronic thermometer. The signal changes at points A to J are shown.

The thermometer of this embodiment has a reference resistance 2 and a capacitance 4
The pulse signal generated in the resistance value-frequency conversion circuit 1 from the charging / discharging of the circuit configured by is counted by the frequency dividing circuit 10, and the measurement time T0 is measured by the main counter. The pulse signal generated in the resistance value-frequency conversion circuit 1 due to the charging / discharging of the circuit constituted by the temperature sensitive element 3 and the capacitance 4 is divided by the frequency dividing circuit 10 during the measurement time T0 determined by the reference value setting unit 70. Measuring unit 71 for counting with the frequency dividing circuit 10
And a conversion display unit 72 that displays the temperature based on the count value (observation count value). Further, in the thermometer of this example, the frequency dividing circuit 10 is provided with an initial logic adjusting circuit 9 capable of setting an initial value.

The measurement principle of the thermometer of this example is that the reference resistance 2 is determined by the number of times of charging / discharging by the reference resistance 2 and the capacity 4 and the number of times of charging / discharging by the temperature sensitive element (temperature sensitive resistance) 3 and the capacity 4 in a certain period.
The resistance value ratio between the temperature sensitive element 3 and the temperature sensitive element 3 is obtained, and the temperature is determined from the resistance value ratio.

Therefore, the counting time is set from the target number of times of charging / discharging by the reference resistor 2 and the capacitor 4, the number of times of charging / discharging by the temperature sensitive element 3 and the capacitor 4 is counted by the frequency dividing circuit 10 over the counting time, and The digital count value is latched by the latch 11, converted into a temperature digital value by the conversion table prepared in the ROM 12, and the display unit 15 displays the digital temperature.

More specifically, the oscillator O
The clock signal from the SC 19 is divided by the main counter 18 to enable time measurement. Then, various control signals shown in FIG. 4 are output from the main controller 17 based on the result measured by the main counter 18. Of these signals, φ1, φ2, and φ3 are gate signals of the MOS transistors Tr1, Tr2, and Tr3 that form the resistance value-frequency conversion circuit 1 shown in FIG. 2, and perform the above-described charging / discharging operation. . In addition,
Tr1 and Tr2 are P-channel transistors (hereinafter abbreviated as P channels), and Tr3 is an N-channel transistor.
A transistor (hereinafter abbreviated as N-chan).

The operation of the resistance value-frequency conversion circuit 1 shown in FIG. 2 will be described below. The charging / discharging period by the reference resistor 2 and the capacitor 4 is called Phase I, and the charging / discharging period by the temperature sensitive element 3 and the capacitor 4 is called Phase II.

(1) Charge / Discharge Mode by Phase I In the resistance value-frequency conversion circuit 1, as shown in FIG. 2, a reference resistor 2 and a temperature sensitive element 3 are connected in parallel, and a capacitor 4 is connected in series to them in common. It is connected to the. Further, the reference resistor 2 has a transistor Tr1 and the temperature sensitive element 3 has a transistor T1.
r2 are connected in series. Furthermore, capacity 4
Is connected to a bypass circuit formed by the transistor Tr3. Therefore, the transistor Tr1 turns on / off the circuit related to the reference resistor 2,
The circuit related to the temperature sensitive element 3 is turned on / off by r2. Further, the charge / discharge of the capacitor 4 is controlled by the transistor Tr3.

In phase I, when signals φ2 and φ3 and point B are at high level and signal φ1 is at low level, Tr
1, Tr2 is P Chan and Tr3 is N Chan,
Only the P channel Tr1 is turned on, and the circuit of the reference resistor 2 is turned on. And the gate of the transistor Tr3 is
Since the signal φ3 and the signal at the point B are input via the NAND gate 6, the transistor Tr3 is turned off. Therefore, the capacitor 4 is charged via the reference resistor 2. Capacity 4
Let C be the capacitance value of R and the value of reference resistor 2 be R1.
Is charged with a time constant C × R1.

The voltage at the point A charged in the capacitor 4 is supplied to the point B via the inverter 5. The inverter 5 is inverted when the level at the point A exceeds the logic level 1/2 V _DD , and the point B becomes a low level. Therefore, the output of the NAND6 applied to the gate of the transistor Tr3 becomes high level, and the point A is short-circuited to V _SS via the N channel Tr3, so that the capacitor 4 is discharged. As a result, the voltage at the point A decreases, and the output of the inverter 5 is inverted to the high level again.
As a result, the transistor Tr3 is turned off, and the charging of the capacitor 4 starts. This waveform is shown as a signal at point A in FIG. 4 and is shown in phase I starting at time t1. The waveform B by the inverter 5 is also shown as a signal at point B in FIG. 4, and assuming that the period of the phase I from time t1 to time t2 is T1, the pulse number N1 of the waveform B during this period T1. And the value C of the capacitance 4 and the resistance value R of the reference resistor 2
The relationship with 1 is as follows.

T1 = (C × R1 × ln2) × N1 (1) (II) Charge / Discharge Mode by Phase II When signal φ2 is low level, signals φ1, φ3, and point B are high level, P Only Chan Tr2 is turned on. Therefore, if the circuit of the temperature sensitive element 3 and the capacitance 4 is connected and the resistance value of the temperature sensitive element 3 is Rs, the capacitance 4 is charged with a time constant C × Rs. Similar to the phase I described above, when the voltage at the point A reaches the logic level 1 / 2V _DD of the inverter 5, the N channel Tr3 is turned on. Therefore, point A is V
_Shorted to _SS , the waveform in Phase II at point A shown in Fig. 4 is obtained. Therefore, at the point B via the inverter 5, as shown in FIG.
When s fluctuates, a pulse whose period fluctuates is generated. Assuming that the period of Phase II is T2 and the number of pulses at the point B generated during this period T2 is N2, the value C of the capacitor 4 and the resistance value Rs have the following relationship.

T2 = (C × Rs × ln2) × N2 (2) During the phase T1 of phase I, the time t1 is generated due to the rise of the signal φ4 from the set frequency division stage of the main counter 18.
start from. Subsequently, the output signals φ2 and φ3 of the main controller 17 rise, and charging / discharging of the reference resistor 2 and the capacitor 4 starts.

The waveform at point B (signal B) is input from the resistance value-frequency conversion circuit 1 to the frequency dividing circuit 10 via the NOR gate 7. Therefore, when the C signal that is also input to the NOR gate 7 falls, the pulse of the signal B is input to the frequency dividing circuit 10 as a clock signal. When the charge and discharge of the reference resistor 2 and the capacitor 4 progress, and at time t2, the measurement by the frequency dividing circuit 10 reaches the target pulse number N1 set as the above-mentioned phase I, a multi-input NAND gate (hereinafter referred to as a multi-input gate The output setting is 16 and the signal G is output. When the signal G is output, the signals φ2 and φ3 fall, the signal C rises, and the phase I ends. At this time, in the main controller 17, the time of the counting time T1 of the phase I from time t1 to time t2 is stored by using the frequency division output of the main counter 18. The signal H is at a high level during the period T1 of the phase I.

The period T2 of Phase II starts from time t3 due to the fall of the output φ4 of the frequency dividing stage set by the main counter 18. Then, the main controller 17
Output signals φ1 and φ3 rise, charging and discharging of the temperature sensitive element 3 and the capacitor 4 are started, and the pulse-shaped signal B is output from the resistance value-frequency conversion circuit 1. Then, when the signal C falls, the pulse of the signal B is applied as a clock to the frequency dividing circuit via the NOR gate 7. At the same time, when charging / discharging by the temperature sensitive element 3 is started from time t3, the count-up of the main counter 18 also proceeds. At this time,
The main controller 17 compares the frequency-divided output data of the counting time T1 stored in the phase I with the count data of the main counter 18. At time t4, when they become equal to each other, the main controller 17 causes the signals φ1 and φ3 to fall and the signal C to rise.
The period T2 of II ends. During this period, the observed count value N2 obtained by counting the signal B by the frequency divider circuit 10 is latched, so at time t4, the main controller 17 outputs the latch signal U, and the latch 11 latches the count value N2. Then, the count value N2 is converted into a temperature digital value by the conversion table stored in the ROM 12,
It is displayed on the display unit 15 via the decoder 13 and the try bar 14.

As described above, in the thermometer of this example, as a result, the period T1 of the phase I in which the main controller 17 measures the number of pulses by the reference resistor 2 and the phase II in which the number of pulses by the temperature sensitive element 3 is measured. The period T2 of 1 is operated at the same time interval. Therefore, the equations (1) and (2) are equal and expressed as follows.

(C × R1 × ln2) × N1 = (C × Rs × ln2) ×
N2 (3) Therefore, it is understood that N1, N2, Rs, and R1 have the following relationships.

N2 = R1 / Rs × N1 (4) When a thermistor is used as the temperature sensitive element 3, the resistance Rs at the temperature W ° C. is given by the following equation.

Rs = R0 × exp (B (1 / W-1 / W0)) ...
(5) where B is the thermistor constant, W0 is the reference temperature, and R0 is the resistance value of the thermistor at temperature W0. Substituting this into the equation (4) gives the following equation.

N2 = R1 × N1 / (R0 × exp (B (1 / W-1 / W
0))) ... (6) The relationship between the temperature W ° C. and the count number N2 is as shown in equation (6), and N2 measured in phase II is transferred from the latch 16 to the ROM 12, ) Is converted into a digital temperature value of ° C or ° F by a conversion table based on the equation), and further, the digital temperature is displayed on the display unit 15 through the decoder 13 and the driver 14.

Unlike the thermometer of this example, the temperature sensing element and the capacitance are charged and discharged in the first charge and discharge phase I of the resistance value-frequency conversion circuit 1, and the reference resistance and the capacitance are charged and discharged in phase II. Even if the conversion to the temperature digital value is performed by performing the same processing as above with charging and discharging of the reference resistance and the capacitance as N2, N1, N2, Rs, and R1 have the same relationship. It is possible to make measurements.

Next, the absolute value adjustment used in the thermometer of this example will be described. For the adjustment, the count value N2 of the pulse signal whose frequency fluctuates due to the change in the resistance value of the temperature sensing element 3 at the temperature at the adjustment point according to the temperature measurement principle may be matched with the set number in the conversion table stored in the ROM 12. . Therefore, it is only necessary to correct the deviation of the count value N2 due to the resistance values of the reference resistor 2 and the temperature sensitive element 3 being varied due to individual differences and deviating from the set value resistance ratio of the conversion table. That is why. When the deviation with respect to the set value resistance ratio due to such individual difference is K, the equation (4) becomes the following equation.

N2 = R1 / Rs × N1 × K (7) Therefore, if K can be corrected by some method, the count value N2 that matches the set value resistance ratio of the conversion table can be supplied to the latch 11. , It becomes possible to adjust the absolute value.

Therefore, the count value N1 for determining the measurement time of Phase II is changed by the reference resistor 2 to N11.
Then, when the count value N11 is N11 = N1 / K, the equation (7) becomes the following equation.

N2 = R1 / Rs × N11 / K × K N2 = R1 / Rs × N11 (8) Thus, the deviation K with respect to the set resistance value ratio is N1 to N1.
It can be seen that if it can be variably set to 1, it can be corrected and absolute value adjustment can be performed. Therefore, in this example, the initial logic adjustment circuit variably sets the count value N1 to be the count value N11 in consideration of individual differences.

The method of adjusting the count value N1 is to preset the count value necessary for the adjustment in the frequency dividing circuit 10 for counting before starting the counting, or to count up in the frequency dividing circuit 10. There is a method of changing the target count value N1 to N11.

In the thermometer of this example shown in FIG. 1, the count value is set to N1 to N11 by presetting the initial value in the frequency dividing circuit 10 using the initial logic adjusting circuit 9.

That is, the difference between the output setting of the multi-input NAND gate 16 used for counting up in the frequency dividing circuit 10 and the setting of the initial data set of the initial logic adjusting circuit 9 can be variably set as the count value N11. . When this count value N11 is expressed by a mathematical expression, the multi-input N
If the output setting of the AND gate 16 is M and the set value of the initial data set of the initial logic adjusting circuit 9 is M0, then N1
1 = M−M0. Then, the count value N1 is changed to N11.
In order to variably set to M, M is fixed and M0 is variably set.

FIG. 3 shows the configurations of the frequency dividing circuit 10 and the initial logic adjusting circuit 9. The frequency dividing circuit 10 includes a set-priority type 1/2 frequency dividing circuit with reset (hereinafter abbreviated as set 1/2 frequency dividing circuit) 28 to 31 and a 1/2 frequency dividing circuit with reset 3.
2 are composed of, it is sequentially counted up 2 ^{0-2 4.} Then, the result of each bit constituted by the set 1/2 frequency dividers 28 to 31 and the reset 1/2 frequency divider 32 is output to the latch circuit 11 and the multi-input gate 16.

The initial logic adjusting circuit 9 for setting the initial data set in the frequency dividing circuit 10, 2 ^0-2 of the divider circuit 10
Half-bit flip-flop circuits 20 to 23 corresponding to the set 1/2 frequency dividing circuits 28 to 31 of ³ are provided. The data input terminal D of each flip-flop circuit 20-23 is grounded via the terminals D0-D3, and at the same time, each pull-up transistor T
It is pulled up by r4 to Tr7. Therefore, when the terminals D0 to D3 are disconnected, the pull-up transistors Tr4 to Tr7 set data in predetermined prep-flop circuits 20 to 23. The outputs of the flip-flop circuits 20 to 23 are output to the corresponding set 1/2 frequency divider circuit 2 via the NAND gates 24 to 27, respectively.
8 to 31 set (bar) terminals are connected. Therefore, the signal J input to the NAND gates 24 to 27 at the same time is
Becomes high level, the flip-flop circuits 20 to 23
Of the initial logic adjusting circuit 9 is set in the frequency dividing circuit 10.

For example, when the set value M0 of the initial data set is set to M0 = 1, the logic adjustment data input terminal (hereinafter abbreviated as D terminal) of the terminal D0 is opened. The data terminal D of the flip-flop circuit 20 from the V _SS line 33
Is released from the V _SS line 33 and pulled up by Tr 4 of the P channel, so that M0 = 1 is set in the half-bit flip-flop circuit 20. Then, the NAND 24 is turned on at the timing of the data read signal J to output 2 ⁰ of the set 1/2 frequency divider circuit 28 to 1. As a result, M0 = 1 is set in the frequency dividing circuit 10. When M0 = 5, terminal D
Not only is 0 released from V _SS line 33, but terminal D2 is also released from V _SS line 33. Then set 1
The 2 ² output of the 1/2 frequency divider circuit 30 is also set by the setting value of the prep-flop circuit 22 via the NAND gate 26,
In the frequency dividing circuit 10, M0 = 5 is set.

The other terminals D1 and D3, which are not opened from the V _SS line 33, have the data input terminals D of the flip-flop circuits 21 and 23 remaining at the low level, and therefore the corresponding set 1/2 frequency divider circuits 29 and 31. No data is set in.

If the P channels Tr4 to Tr7 are always on, a current always flows between V _DD and V _SS , resulting in a large current consumption of the circuit. Therefore, in the present embodiment, P is set at an appropriate initial data read cycle.
Chans Tr4 to Tr7 are turned on by a low level signal to the gate terminal 34, and a data read signal is also input to the clock terminal 35, and the half bit flip-flops 20 to 23 also read the data, and thereafter the data is stored until the read cycle. To be done.

In the thermometer of this example, the timing of reading the initial data set in the initial logic adjusting circuit 9 is as shown in FIG.
Prior to 1, the frequency dividing circuit 10 is all reset by the reset signal I, and then M0 of the initial data is read into the frequency dividing circuit 10 by the signal J of the data reading signal. Then, by the frequency dividing circuit 10 in which the initial data M0 is set,
The pulse signal B based on the reference resistance of the phase I output from the resistance value ⇔ frequency conversion circuit 1 is counted, and the time to reach the count value N1 is set by the main counter 18 as the reference value.

Next, in the phase II, the pulse signal B based on the temperature sensitive element 3 is counted. At this time, the read signal J does not become high level and the frequency dividing circuit 10
After the reset, starts counting from a state where the initial data M0 is not set.

Thus, in this example, terminals D0 to D
In order to open the D terminal 3 of line 3 from the V _SS line, by inputting the logic adjustment data indicating whether the substrate pattern is cut or not, the initial data initially set by the initial logic adjustment circuit 9 can be variably set. As a result, Phase I
In period T1 which determines the measurement period of Phase II,
It can be set by counting from the number of times of charging / discharging by the reference resistor 2 and the capacitor 4 to the corrected count value. Therefore, it is possible to correct the variation due to the individual difference between the reference resistance and the resistance value of the temperature sensitive element at the adjustment point, that is, the deviation of the resistance value ratio, and to perform the absolute value adjustment.

The present invention is applicable not only to electronic thermometers but also to thermometers, pressure gauges, scales and the like.

[0052]

As described above, according to the present invention, the measurement time for measuring the first pulse signal is not specified in advance, but the target count value is specified.
The counting time up to the target count value is determined by counting the pulse signals of the second pulse signal, the counting of the second pulse signal is performed for the determined counting time, and the observed count value of the second pulse signal is determined. Is obtained. Then, the measurement result is displayed based on the observed count value. Therefore, the following effects are obtained.

Since it is possible to convert the temperature into a temperature or the like based on the observed count value of the second pulse signal without calculating the count ratio, the division process is unnecessary. Therefore, it is possible to avoid the complexity of the circuit system and the increase in the size of the formation area.

Of course, due to the presence of the counting means with a set and the correction data setting means, even if a reference resistor or a temperature-sensitive resistor having a variation in resistance value is used without using the variable resistor for initial adjustment, those resistors are used. It is possible to provide a temperature measuring device that can keep the ratio apparently constant, has a low cost, has few adjustment steps, and does not change with time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an electronic thermometer according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a resistance value-frequency conversion circuit in the block diagram of FIG.

3 is a circuit diagram showing a part of an initial logic adjusting circuit and a frequency dividing circuit in the block diagram shown in FIG.

FIG. 4 is a time chart showing signals of various parts of the electronic thermometer of the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Resistance-frequency conversion circuit 2 ... Reference resistance 3 ... Temperature-sensitive resistance 4 ... Capacitance 5 ... Inverter 6,8, 24-27 ... NAND gate 7 ... NOR gate 9 ... Initial logic adjusting circuit 10 ... Dividing circuit 11 ... Latch Circuit 12 ... ROM 13 ... Decoder 14 ... Driver 15 ... Display 16 ... Multi-input NAND gate 17 ... Main controller 18 ... Main counter 19 ... Oscillator 20-23 ... Half-bit flip-flop circuit 28-31 ... Set priority type reset 1/2 frequency divider 32 ... reset with 1/2 frequency dividing circuit 33 ... V _SS supply line 34 ... gate terminal 35 ... clock terminal Tr1 to Tr3 ... for initial data setting of the MOS transistor D0 to D3 ... initial logic adjusting circuit Terminal 70 ... Reference value setting unit 71 ... Measuring unit 72 ... Conversion display unit.

Continuation of the front page (56) Reference JP-A-47-27041 (JP, A) JP-A-58-500821 (JP, A) JP-A-58-500822 (JP, A) JP-A-59-100815 (JP , A) Actual Development Sho 57-116824 (JP, U) Japanese Patent Publication 2-16448 (JP, B2) Japanese Patent Publication 57-14485 (JP, B2)

Claims (1)

[Claims] 1. A reference pulse signal having a frequency based on the resistance value of a reference resistor and a detection pulse signal having a frequency based on the resistance value of a detection resistor whose resistance value changes in response to temperature, pressure, etc. are switchably generated. Resistance value-frequency conversion means and one of the reference pulse signal and the detection pulse signal as a first pulse signal and the other as a second pulse signal, and the first pulse signal until the target count value is reached. Counting means for counting and counting the second pulse signal for a counting time equal to the time until the count of the first pulse signal reaches the target count value after resetting, and the counting time by the counting means. In the measuring device displaying the measurement result based on the observed count value of the second pulse signal, the counting means is a preset type counting means, and prior to the counting of the first pulse signal. A measuring device comprising a correction data setting means for setting resistance value variation correction data as an initial value for the preset type counting means.