JPH0750431B2 - Serial access memory device - Google Patents

Description

The present invention relates to a serial access memory device suitable as a memory for video signals and the like.

[Conventional technology]

A technique of performing time-axis processing by digitally processing a video signal is generally known. As an example thereof, there is a frame synchronizer which converts a video signal into another synchronous video signal having no relation in phase and frequency. The frame synchronizer is usually provided with a 1-field or 1-frame memory, and as the memory, a serial access memory device in which addresses are sequentially increased and accessed is used.
Writing is performed in synchronization with the synchronous system of the input video signal, and reading is performed in synchronization with the synchronous system to be converted.

When writing and reading the NTSC video signal to the memory, this video signal is read as 4f _SC (where f _SC is the color subcarrier frequency, and in the case of the NTSC system, the horizontal sync signal frequency is (2 × 227 + 1) / 2). The number of words per line is 4 × (2 × 227) / 2 = 910, and the number of lines per field is 263, 1 Since the number of lines in a frame is 525, one field memory requires 8 × 910 × 263 = 1914640 bits and one frame memory requires 8 × 910 × 525 = 3822000 bits. On the other hand, a memory often has a configuration of 2 ⁿ (n is a natural number) bits in terms of good layout efficiency and easy address control. Therefore, the amount of data of one field is 2 ²⁰ = 1048576 bits of 2 so-called 1 megabit memory, or 2 ²² = 419.
1/2 of the so-called 4-megabit memory with a capacity of 4304 bits
The data amount of one frame can be accommodated in four 1-megabit memories or one 4-megabit memory.

By the way, regarding the writing and reading in the field memory or the frame memory in the frame synthesizer, there are the following two problems.

The first problem is that the write and read operations must be performed asynchronously.

Even consider a was rows summer synchronously writing and reading to 4f _SC, the frequency f _SC of the synchronization system towards reading synchronous with the video signal towards the writing of the video signal is not strictly identical, Therefore, the phases of the write operation and the read operation randomly change. Therefore, it is necessary for the field memory or frame memory to perform asynchronous write and read operations.

However, the first problem is, for example, NEC Technical Report, V
ol.39 No.10 (October 1986 issue) pp.94-99, write word line, read word line, write bit line to each memory cell of the field memory or frame memory. The problem can be solved by providing separate read bit lines so that writing and reading of data can be performed independently and simultaneously.

The second problem is that the write address and the read address match.

In memory writing and reading, those addresses are sequentially moved, and data is written to these addresses in order or data at these addresses is read in order. Since the phase of the operation is random, the write address and the read address may almost match. In such a case, if the video signal to be written has jitter or the like, the read address often overtakes or is overtaken by the write address.

The operation will be described below by taking a frame synthesizer using a field memory in which writing and reading operations are independent of each other as an example.

FIG. 11 shows the basic operation of this field memory. FIG. 6A shows an address set signal of the field memory, and T ₁ is a cycle of one field. Further, FIG. 6B shows the transition of this address, with the horizontal axis representing time and the vertical axis representing the address of the field memory.

In the same figure, in the field memory, when an address set signal is input, it becomes the head address. Therefore, when the address set signal is input at time t ₁ , the address of the field memory becomes the start address, and thereafter, 1
During the field period, the address increases sequentially with the transition shown by the solid line A. As described above, the data amount of one field is 1914640 bits, and if two 1 megabit memories are used as one field memory, one field data is stored in about 91% of all addresses.
When the address set signal is input at time t ₂ after one field period T ₁ , the field memory returns to the head address.

The above operation is performed for writing and reading,
Therefore, an address set signal is provided for each.

Next, the relationship between the write address and the read address of the field memory will be described with reference to FIG. Note that FIG. 7A shows a write address set signal, and FIG. 7B shows a read address set signal. These periods T ₂ and T ₃ are different field periods of the synchronization system and are different from each other. And also F1, F2, F
3, F4, F5, ... Represent the sequential fields of the video signal to be written. Further, FIG. 6C shows the transition between the write address and the read address, with the horizontal axis representing the time and the vertical axis representing the address of the field memory.

In the same figure, it is assumed that the clock cycle of the write synchronous system is longer than the clock cycle of the read periodic system, and the cycle T ₂ of the write synchronous system is longer than the cycle T ₃ of the read synchronous system. At time t ₃ , the write address becomes the start address by the write address set signal, and then at time t ₄ , the read address is set at the start address by the read address set signal, and thereafter, the write address becomes one point. As indicated by the chain line A _W , and the read address increases sequentially as indicated by the broken line A _R. As a result, the field F1 is written from the head address, and thereafter the field F1 is read. And about 91% of the total in one field period T ₂
When one field of data is written to the address of and the next write address set signal is input (time
t ₅ ), the write address returns to the beginning and the writing of the next field F 2 is started. Then, when the read address set signal is input at time ₆ which is one field period T ₃ after time t ₄ , the read address set signal is read. The address of is returned to the start address and reading of the field F2 is started.

Here, time t ₃ is before time t ₄ , and in the field memory, the read address A _R is the write address.
It is in a state of chasing A _W. That is, at each address, the data is read out after the data is written. Further, as described above, because the clock period towards the period of reading than synchronous write is short, the read address as compared to the transition of the address A _W of the write
Although the transition of A _R is rapid, it is assumed that the read address A _R cannot catch up with the write address A _W between times t _{3 and} t ₆ . Therefore, the transition line of the read address A _R shown by the broken line during this period is the write address shown by the alternate long and short dash line.
It is on the right side of the A _W transition line.

However, the times t ₅ and t ₆ are extremely close to each other, and when the data is written at the start address and the data is read from the start address almost at the same time, the transition of the write address A _W shown by the one-dot chain line The line and the transition line of the read address A _R shown by the broken line intersect. This means that the read address A _R catches up with the write address A _W within the write period of the field so that they match, and then the read address A _R precedes the write address A _W. Even after this, the write address excisional signal input every (time t _8, t
₁₀ , t ₁₂ , ... ……) The write address A _W returns to the start address, and each time the read address set signal is input (time
_{t 7, t 9, t 11} , .........) read address A _R is to the first address, go One Hiroga the spacing of these addresses.

Thus, when the reading of the address A _R between time t ₆ ~t ₈ overtakes an address A _W of the write until the overtaking occurs is read is field written currently in field memory, after overtaking Then, the previously written field, which is one before the currently written field, is read out. Therefore, the reproduced image during the field period read between times t _{6 and} t ₈ is The continuous two-field images are spliced one by one.

A means for solving such a problem is disclosed in Journal of Television Society Vol.33 No.4 (1979) pp.277-282.

One of the means is shown in FIG. 3 of this known document, which uses several delay lines. That is, the phase difference between the write clear pulse (write address set signal) and the read clear pulse (read address set signal) is compared, and when this phase difference becomes 2H (1H is one line period) or less, the next write Delay the data to be written and the write clear pulse in synchronization with the address set signal by the delay lines, respectively,
Alternatively, the delay line is removed so as not to be delayed by this, and it is supplied to the field memory or the frame memory.

The other one is for a frame memory composed of two memories having a memory capacity of one field, and writing and reading are performed by one field alternately in these two memories. In such frame memory, writing,
The memory to be read is selected by the selection signal, but the write address set signal and the read address set signal are compared, and the phase difference between them, that is, the difference between the write address and the read address is less than a certain value. At this time, the polarity of the selection signal is inverted in synchronization with the next write address set signal, and the next field is written again in the memory in which the writing has been completed. The reading is performed in another memory, and the reading of the field immediately preceding the field for which the reading has been completed is performed.

Here, the operation of the conventional example using the delay line will be described in detail with reference to FIG. Note that FIG. 7A shows the write address set signal of the field period T ₂ , and FIG. 8B shows the read address set signal of the field period T ₃ , where T ₂ > T ₃ and F6 and F7. , F8, F9, F10, ... Represent the sequential fields of the video signals to be written. Further, FIG. 7C shows the transition between the write address A _W and the read address A _R, with the horizontal axis representing time and the vertical axis representing the memory (here, the field memory) address. There is.

In the figure, writing in the field memory is performed prior to reading, and therefore, at each address, this data is read after writing data. In this case, it is assumed that the phase difference between the write address set signal and the read address set signal is larger than 2H until just before the field F6. Since the read transition is faster than the write transition, the read address A _R approaches the write address A _W , but at the start time t ₁₃ of the field F7, the write address set signal causes
The write address A _W returns to the start address, and then
If the read address A _R returns to the start address at time t ₁₄ , and the phase difference between the write address set signal and the read set address signal is within 2H, the end of field F7 (that is, A delay line is inserted (at the trailing edge of the write address set signal), and the data to be written and the write address set signal are delayed by several lines by this delay line and supplied to the field memory.

In general, the difference between the period T ₃ read address excisional signal and the period T ₂ of the write address signal is very small,
The read address is very close to the write address, so that the write address does not overtake the read address during writing of the field F7.

Due to the read address set signal, the read address A _R is delayed by the field period T ₃ from time t _{14 at} time t
_Although it returns to the start address in ₁₆ , the next field F8 to be written and the write address set signal are delayed by a few lines by the delay line, so the writing of the field F8 is started from the start address with a delay of this delay time T _d. . Thus, field F8 is should be written from the head address from the period T ₂ delayed by the time t ₁₅ a write address excisional signal than the original time t _13, the delay time T _d of the delay lines than the time t ₁₅ It delayed, but the connexion, from the time t ₁₇ which is delayed than the time t ₁₆ the read address a _R is set to the head address, writing from the start address of the field memory is started. Because of this, the time t
_The field F7 is read again from ₁₆ and then the field 8 is written.

Therefore, in FIG. 12, as shown in FIG. 14, the field F1 is read from the time t ₄ and the field is read from the next time t _6.
F2 is read out, but the field F1 is read out again within one field period, and from the next time t ₈ , the field F2, F3, F4, ... is read in order of one field period T _{3 at a} time. become. In this way, when two fields of image are combined and displayed on one screen, that is, when there is switching of two fields of image on one screen and there is jitter in the writing synchronization system or the reading synchronization system. In such cases, switching of this image occurs frequently,
The image is very unsightly.

On the other hand, in the case of FIG. 13, as shown in FIG.
From the time t ₁₄ field F7 is read, it is read out field F7 again from the next time t _16, thereafter, field
F8, F9, ... Are read in sequence one field period at a time. Therefore, the images of the same field are repeated twice, but the images of two fields are not stitched together in one field period, and the images of two fields are not switched on one screen. Also, in fact,
The cycle of the write synchronization system and the cycle of the read cycle system are almost the same on average, and the repetition of the same field as shown in FIG. 15 does not occur frequently. Also,
Even when this repetition occurs, as shown in FIG. 15, the image is better than that in the case of switching in the two-field image screen, which is not bothersome.

The means shown in FIG. 4 of the previously known document (Journal of Television Society) is basically the same as the means using a delay line.

[Problems to be solved by the invention]

As described above, it is possible to prevent switching of images of two different fields on the screen, but this requires a delay line, and in the case of the frame memory, one field capacity of two memories is used. The number of the memories is increased, and the size is increased due to the complicated structure, and the control becomes complicated when two memories are used.

An object of the present invention is to solve the above problems and provide a serial access memory device having a simplified configuration and simple memory control.

[Means for solving problems]

In order to achieve the above object, the present invention sets the number of addresses of a memory unit for writing and reading a periodicity information signal to be larger than the number of addresses required to store a unit period of the periodicity information signal. A unit cycle of the cycle information signal to be written in the memory section is provided by providing a write set register for subtracting a predetermined value every time and a read set register for taking in the count value of the write set register immediately before the subtraction operation in the write set register. The count value of the write set register is loaded into the write address register for generating a write address at each start of the read set register, and the count value fetched into the read set register at each start of reading of the unit period of the periodicity information signal from the memory section. Is loaded into the read address register that generates the read address. The reading timing of the counter value in the read set register is stored in the write address register after the count value of the write set register is loaded, and the number of addresses in the memory unit and the unit period of the periodicity information signal are stored. There is provided a means for setting an approximately midpoint of a period until writing is performed in the memory portion by a difference from the number of addresses required for writing.

[Action]

It is assumed that the periodicity information signal is a video signal and the memory section can store a 1-field video signal.

In this case, the memory section has more addresses than the number of addresses required to store one field of the video signal.

The write address register is loaded with the count value of the write set register at the start of each field.
Since this count value is decremented by a predetermined value each time the field starts, the write start address of the field in the memory unit is advanced by the number of addresses corresponding to the predetermined value for each field. Therefore, the start address of the field to be written next is advanced by this address number with respect to the start address of the field previously written in the memory section, and the field written first is the next field by this address number. Remains stored until is written.

On the other hand, since the count value of the read set register is loaded into the read address register, the read is always started from the start address of the field of the memory section at this loading timing, and the successive fields are read. If there is sufficient time between the start of writing the field and the start of reading the field, the count value of the read set register is read after the count value of the write set register is loaded into the read set register. And the currently written field is read from the start address in the memory section.

In this case, the read address does not pass the write address in the memory section.

On the other hand, if the write start time of the field and the read start time of the field in the memory section are close to each other so that the read address will pass the write address, the count value of the write set register will not be read into the read set register. At this time, the count value previously fetched by the read set register is loaded into the read address register, and the field written before the currently written field is read from the start address in the memory section.

In this case, the field that has been read once will be read again, and this is because the write set must start before the write address reaches the start address of this field. The read value of the count value of the register is read into the set register. After the count value of the write set register is loaded into the write address register, the number of addresses in the memory section and the unit cycle of the periodicity information signal are stored. The difference from the number of addresses required for the writing is set to an almost midpoint until writing is performed in the memory section.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a serial access memory device according to the present invention, in which 1 is a write address register, 2 is a read address register, 3 is a write set register for determining the set value of the write address register 1, 4 is a read set register for determining the set value of the read address register 2, 5a to 5d are memory mats each having a capacity of 1024 × 256 bits, 6 is a selector, 7 is an address register for giving addresses to the memory mats 5a to 5d, and 8a to 8d Is a data input terminal, 9a to 9d are 32 bit serial-parallel conversion circuits, 10a to 10d are input buffer registers, 11a to 11d are output buffer registers, 12
a to 12d are parallel serial conversion circuits for 32 bits, 13a to 1
3d is a data output terminal, 14 is a timing control circuit, 15a to 15d are input terminals, and 16 is an address control block composed of a timing control and write / read address generator.

In this figure, it is assumed that the video signal is sampled at a frequency of 4fsc and quantized by 4 bits. Each sample point of this video signal is input from the input terminals 8a to 8d as 4-bit parallel data. The bit pulses from these input terminals 8a to 8d are supplied to the serial-parallel conversion circuits 9a to 9d by the 4fsc clock WSP from the timing control circuit 14 in the address control block 16, respectively.
Is taken in and converted into 32 bit parallel data.
The 32-bit parallel data output from these serial-parallel conversion circuits 9a to 9d are taken into the input buffer registers 10a to 10d by the clock WBF having a frequency of 1/32 of the clock WSP, and are respectively stored in the memory mats 5a to 5d. The data is written in the address area specified by the write address held in the address register 7.

Here, the number of bits in one field period of the NTSC video signal is 4 × 910 × 263 = 957320, and the total capacity of the memory mats 5a to 5d is set to 20 ²⁰ = 1048576 bits. It was but connexion, each volume of Memorimatsuto ^{5a~5d, 2 20/4 = 2} 18 , and the they are memory capacity of 1024 × 256 bits are used. Since the same address is given to each of the memory mats 5a to 5d and 32 bits are written in one address area,
Total number of addresses in each Memorimatsuto 5a~5d is 2 ^18/32 = 2 ¹³ = 8192, and the address is represented by 13 bits. In addition, the number of addresses of the memory mats 5a to 5d required for writing the 1-field video signal is This is about 91% of the total number of addresses. That is, each memory mat 5a-5d has a margin of about 9%.

On the other hand, in the address control block 16, the write control clock WCLK at the same frequency as the sampling clock of the video signal to be written from the input terminal 15a is synchronized with the timing control circuit 14 from the input terminal 15b to the vertical synchronizing signal of the video signal. The write address set signal ▲ ▼ synchronized with the read clock RCLK generated by the memory read synchronous system from the input terminal 15c.
Is a read address set signal from the input terminal 15d synchronized with the vertical sync signal formed by this sync system.
▼ are supplied respectively, and by these, clock WSP, WBF, RB
F, RSP, ARS, selection signal SEL, etc. are formed, and the write address A _W from the write address register 1
The read address A _R is generated from the read address register 2.

Here, the clock WSP is synchronized with the write clock WCLK, and the clock WBF is formed by dividing the write clock WCLK by 32. Similarly, the clock RSP is synchronized with the read clock RCLK and the clock RBF is formed by dividing the read clock by 32. The selection signal SEL is a pulse having the same cycle as the clock WBF and a duty ratio of 50%, whereby the selector 6 is controlled to alternately select the write address A _W and the read address A _R. The selected write address A _W and read address A _R are stored in the address register 7 by the clock ARS.

Therefore, when the write address A _W is stored in the address register 7, 32 bits are written in the address area designated by the memory mats 5a to 5d, as described above.
When read address A _R is stored in the address register 7, the clock RBF, respectively 3 Memorimatsuto 5a~5d
2 Bit parallel data is read and sent to the parallel-serial conversion circuits 12a to 12d via the output buffer registers 11a to 11b, converted to serial bit strings by the clock RSP, and output from the output terminals 13a to 13d. To be done.

As described above, the write address is written in the address register 7.
A _W and read address A _R are alternately stored, and therefore, even though the video signals are continuously input from the input terminals 8a to 8d, the memory mats 5a to 5d have a write and a read. Alternately, output terminals 13a-13d
The video signal is continuously obtained from

Next, generation of the write address A _W and the read address A _{R in} the address control block 16 will be described.

FIG. 2 shows the address control block shown in FIG.
16 is a block diagram showing in more detail, 20 is a 4-bit synchronous counter with load, 21 is a 14-bit synchronous counter with reset, 22 is a 4-bit subtractive synchronous counter, 23 is a 4-bit synchronous counter with a load, 24 is a A 14-bit synchronous counter with reset, 25 is a 4-bit D-type flip-flop circuit, and the parts corresponding to those in FIG.

In FIG. 2, the write address register 1 is composed of a 4-bit synchronous counter 20 with a load and a 14-bit synchronous counter 21 with a reset.
4 bit sync counter with load 23 and 14 with reset
It consists of a bit sync counter 24. The write set register 3 is composed of a 4-bit subtraction synchronization counter 22, and the read set register 4 is composed of a 4-bit D-type flip-flop circuit 25. 4 bit synchronous counters 20 and 23 with load, 14 bit synchronous counters 21 and 24 with reset (these are simply referred to as synchronous counters), 4
Bit subtraction synchronization counter 22 (hereinafter referred to as subtraction synchronization counter) and D-type flip-flop circuit 25 (hereinafter referred to as DFF)
Each) operates at the rising edge of the input clock. The carrier WCAR is sent from the synchronous counter 21 to the synchronous counter 20, whereby the write address register 1 constitutes an 18-bit counter in which the output of the synchronous counter 21 is the lower bit and the output of the synchronous counter 20 is the above bit. In addition, the carry RCAL is sent from the synchronous counter 24 to the synchronous counter 23, and similarly, the read address register 2 constitutes an 18-bit counter in which the output of the synchronous counter 24 is the lower bit and the output of the synchronous counter 23 is the above bit. is doing.

The timing control circuit 14 inputs the write clock WCLK, the write address set signal ▲ ▼, the read clock RCLK, and the read address set signal ▲ ▼ from the input terminals 15a to 15d, respectively, and outputs the clock WCP.
1, WCP2, WCP3, RCP and write address set signal WA
Outputs S and read address set signal RAS. The synchronous counters 20 and 21 are operated by the clock WCP1, and the write address set signal WAS acts on the synchronous counter 20 as a load signal and on the synchronous counter 21 as a reset signal. Similarly, the synchronous counters 23 and 24 operate by the clock RCP, and the read address set signal RAS acts on the synchronous counter 23 as a load signal and on the synchronous counter 24 as a reset signal.

The subtraction sync counter 22 operates according to the clock WCP2,
F25 works by clock WCP3.

Next, the operation of the address control block 16 will be described with reference to FIG. Note that FIG. 3 is a waveform diagram showing the signals of the respective parts in FIG. 2, and in FIG. 2, the corresponding signals are given the same reference numerals.

The write clock WCLK synchronized with the sampling clock of the video signal to be written is input from the input terminal 15a. From the input terminal 15b, the edge of the write clock WCLK is synchronized with the vertical synchronizing signal of this video signal, and the edge matches the edge of the write clock WCLK. When ▼ is input, the timing control circuit 14 causes the write address set signal ▲
▼ is output as the write address set signal WAS, and the clock W is output at the rising edge (time t ₄₀ ) of the write clock WCLK in the input write address set signal Wset.
Phase-sync the rising edge of CP1. By this write address set signal WAS, the synchronous counter 21 is reset and all the bits of its count value become "0" (that is, the count value of the synchronous counter 21 becomes zero), and the synchronous counter 20 subtracts the synchronous counter 22. The value NW of is loaded. After this, the synchronous counter 21 will change to the clock WCP1.
The value is incremented by 1 for each rising edge of
Each time the synchronous counter 21 outputs the carrier WCAR, the synchronous counter 20 counts up the carrier WCAR from the loaded value in synchronization with the rising edge of the clock WCP1.

Here, the upper 9 bits of the count value of the synchronous counter 21 are combined as the lower bit, and the 4-bit count value of the synchronous counter 20 is combined as the upper bit, to form a 13-bit write address A _W. Therefore, this write address A _W changes by 1 for every ²⁵ = 32 clocks WCP1. However, since the frequency of this clock WCP1 is equal to the sampling frequency of the video signal to be written, the change of the write address A _W Timing and serial-parallel conversion circuits 9a-9d (first
It is synchronized with the output timing of 32-bit parallel data in the figure).

The timing control circuit 14 is provided with a counter that resets the write address set signal ▲ ▼ and counts the write clock WCLK. When this counter counts a predetermined number, a clock WCP3 is generated (time t ₄₁ ), which is almost the same as this. clock WCP2 is generated at the same time (time t _42). With this clock WCP3, DFF25
Is loaded with the count value NW of the subtraction synchronization counter 22,
Next, the clock WCP2 causes the subtraction synchronization counter 22 to decrement the count value by one. That is, the synchronization counter
The count value NW of the subtraction synchronization counter 22 is loaded into 20,
Then, after this count value NW is loaded into DFF25,
The count value NW of the subtraction synchronization counter 22 is decremented by 1.

Similarly, the timing control circuit 14 outputs the read address set signal ▲ input from the input terminal 15d.
▼ is output as the read address set signal RAS, and this read address set signal ▲
Within the pulse period of ▼, the rising edge of the clock RCP is synchronized with the rising edge of the read clock RLCK. The synchronous counter 24 counts the clock RCP, but all the bits are reset to "0" by the read address set signal RAS, and the synchronous counter 23 counts the carrier RCA of the synchronous counter 24 and the read address set signal. The count value NR of the subtraction synchronization counter 22 loaded in the DFF 25 is loaded by the RAS. After that, the synchronous counter 24 counts up by one for each rising edge of the clock RCP, and the synchronous counter 24 carries the carrier.
Each time RCAR is output, the synchronous counter 23 counts up this carrier RCAR from the loaded value in synchronization with the rising edge of the clock RCP.

Here, the upper 9 bits of the count value of the synchronous counter 24 are combined as the lower bit, and the 4-bit count value of the synchronous counter 23 is combined as the upper bit to form a 13-bit read address A _R. It was but connexion, the read address A _R is changed to 2 ⁵ = 32 for each of the read clock RCP1.

Where write clock WCLK and read clock RCLK
Phase relationship with, write address set signal ▲
The phase relationship between ▼ and the read address set signal ▲ ▼ is random with respect to each other. Therefore, as shown in FIG. 4 (a), the read address set signal RAS
Is ahead of the clock WCP3 that drives the DFF25, and is behind the clock WCP3, as shown in FIG. 4 (b).
The values loaded into will differ by one. In the case of FIG. 4 (a), the read address set signal RAS causes the synchronous counter 23 to be loaded with a value one more than the value loaded into the synchronous counter 20, but FIG. 4 (b). , A value equal to the value loaded in the sync counter 20 is loaded. If the loaded values differ by 1, the addresses of memory mats 5a-5d are 2 ⁹ = 51.
Becomes 2 differ by, this is the total number of address 2 ^{9/2 13}
It is equivalent to 1/16 (about 6.3%).

Therefore, the count value of the subtraction synchronization counter 22 is now [10
01] (however, assuming that the first bit is the highest bit), in FIG. 5, the synchronous counter 20 is activated by the write address set signal WAS at the start point (time t ₂₄ ) of the field F11.
This count value [1001] is loaded into the memory, and thereafter, the write address A _W is incremented by 1 from [100100 ... Therefore, in the memory mats 5a-5d, the field
F11 is sequentially written from this address [100100 ... 0]. Of course, in the memory mats 5a to 5d, when the data is written to the last address, the data is written back to the first address, the data is sequentially written from there, and the field F11 is written to the 7479 address as described above. .

At the next write address set signal (time t ₂₆ ), the count value of the subtraction counter 22 decremented by 1 [1000]
Is loaded into the synchronous counter 20, and accordingly, in the memory mats 5a to 5d, the field F12 is similarly written from the address [100000 ... Similarly, the field F13 is from the address [011100 ... 0], the field F14 is from the address [011000 ... 0], and so on.
They are written in the memory mats 5a to 5d, respectively.

On the other hand, as shown in FIG. 5, the read address set signal RAS is generated at time t ₂₅ and its phase is shown in FIG. 4 (b).
At this time, the DFF ₂₅ is loaded with the count value [1001] of the subtraction synchronization counter 22, and this count value is loaded into the synchronization counter 23 at time t ₂₅ . Therefore, the read address A _R is [100100
........ is incremented by 1 from 0], and reading is started from this address in the memory mats 5a to 5d. The previous field F11 is written from this address. Therefore, after writing this field F11, this field F11 is written.
11 readings will be performed.

Next, at time t ₂₇ , the read address set signal RAS is generated. If the generation timing is as shown in FIG. 4 (a), the count value of the subtraction synchronization counter 22 is decremented by 1 to become [1000]. However, the DFF25 is loaded with the original count value [1001], and for this reason,
The synchronization counter 23 is loaded again count [1001] read address A _R is incremented by 1 from [100100 ......... 0]. At this time, in the memory mats 5a to 5d,
Although the field F12 is being written from the address [100000 ......... 0], the difference in the count value 1 of the subtraction synchronization counter 22 is that the address is different by 2 ^9. Therefore, the write address set signal By WAS, the count value of the subtraction sync counter 22 is loaded into the sync counter 20 (time t _{40 in} FIG. 3) to the count value is loaded into the DFF 25 (time t _{41 in} FIG. 3). time, the write address a _W is 2 ⁹ (the but connexion, only the count value of the first synchronous counter 20) by multiplying the short than the period that varies, write address field F12 write start address of the previous field F11 [ 100100 .........
0] has not been reached. Therefore, from time t ₂₇ , the field F11 is read again.

Field F11 from this address [100100 ......... 0]
After rereading the next count value of the subtraction synchronization counter 22 to DFF25 [1000] is loaded, the read address excisional signal RAS at the next time t _30, Memorimatsuto 5a the count value is loaded into the synchronous counter 23 The field F12 is read from ~ 5d. Thereafter, the fields F13, F14 ... Are read in the same manner.

FIG. 6 shows the time transition of the write address A _W and the read address A _R described above. Memory mat 5 until time t ₂₇
The data is read out immediately after writing the data at each address of a to 5d, but after the time t ₂₇ , the writing is performed after reading the data at each address. Where time t
_{In 27} , when the read is started, the write address has not reached the start address. As a result, as shown in FIG. 5, the field F11 can be read again.

In this way, the write address A _W and the read address A _R
Is not reset to zero for each write address set signal ▼ and read address set signal ▲ ▼, but is set to a value having an offset for each. This offset is such that the write start address sequentially advances for each field so that it takes a certain time until the next field is written until the write start address of the previous field, and the read address set signal becomes the write address set signal. This time is used so that the previous field can be read out again when approaching to overtake.

The offsets of the write address A _W and the read address A _R are possible because the memory mats 5a to 5d have a larger number of addresses than the number of addresses required to write the video signal for one field. It may be equal to or less than the number (the total number of addresses of the memory mats 5a to 5d minus the number of addresses required to write the video signal for one field). In the above case, the total number of addresses of each of the memory mats 5a to 5d is 2 ¹³ = 8192, and the number of addresses required to write the video signal for one field is 7479. Here, 2 ⁹ <713 <because it is 2 ^10, in order to simplify as address number is 2n configuration of Memorimatsuto 5a to 5d, the offset was 2 ^9, is loaded in the synchronous counter 20, 23 The value is reduced by one. This offset is the memory mat 5a
It is equivalent to 1/16 (about 6.3%) of the total number of addresses of ~ 5d, and the number of extra addresses of the memory mats 5a to 5d is about 9% of the total number of addresses, so it is smaller than the number of extra addresses. .

Further, the load time t ₄₀ of the synchronous counter 20 in FIG.
From the load time t _{41 of the} DFF 25 to the subtraction time t ₄₂ of the subtraction synchronization counter 22 (the number of addresses), in FIG. 7, writing is started from the address A _W1 at the time t ₃₄ and the time t _35. Then, if writing of one field is completed and writing of the next field is started from the address A _W2 , ΔA _W1 = A _W1 −A _W2 becomes an offset. The offset .DELTA.A _W1 minutes from this address A _W2, that is, the time when it was written to address A _W1 and t _36, the time t _35, the read address between t ₃₆ A _R address A _W1
Once set, the previous field (the field written from address A _W1 ) can be read without being erased by the writing of the next field from time t ₃₅ . Therefore, at time t _{40 in} FIG.
The number of addresses from time t ₄₁ to time t ₄₂ should be smaller than the offset.

However, when the number of addresses is too small, the write start address A _W1 of the previous field is not returned even though the write address set signal and the read address set signal are close to each other. It is possible that the medium read address may overtake the write address. If the number of addresses is close to the offset, the write address and the read address are very close to each other near the start time of the next writing and reading, and if the writing speed becomes faster due to the jitter of the video signal, writing, It is possible that the write address may overtake the read address during read.

Therefore, the number of addresses from time t ₄₀ to time t ₄₁ , t ₄₂ in FIG. 3 is about 1/2 of the offset amount (in the above example, about 1/32 of all addresses of the memory mats 5a to 5d, that is, It is desirable to set it to about 3.1%).

Generally, assuming that the total number of addresses in the memory is A, and the number of addresses required to write a video signal of one field (or one frame) into this memory is B, the memory capacity is set so that A> B. . At this time, the offset amount C depending on the number of write addresses is C ≦ A−B
The write address is used to determine whether to set the read address for reading the field (or frame) in which writing is currently performed or for rereading the previous field (or frame). It is determined by whether or not the start of reading is ahead of the time when the writing of only the C / 2 address has passed since the offset was made. By doing so, the write address and the read address do not approach within the address number C / 2, and the relative jitter amount between the write and read per field (or one frame) is C / 2. . Therefore, if the average writing / reading time per address is T seconds, the equivalent jitter amount per one field (or one frame) is
It becomes CT / 2.

Although the video signal has a 4-bit configuration in this embodiment, other configurations such as a 6-bit configuration and an 8-bit configuration may be used, and it is clear that only the memory section needs to be changed accordingly. . In addition, in this embodiment, the memory section has a field memory configuration, but in FIG.
By doubling the capacity of each of the memory mats 5a to 5d and increasing the number of output bits of the synchronous counters 21 and 24 in FIG. 2 by 1, a frame memory can be obtained.

By the way, in the above-mentioned embodiments, the sequential address generation circuit by the counter is used in the randomly accessible memory section to control the order of writing or reading. The memory unit will be described below.

FIG. 8 is a block diagram showing the basic configuration of the memory section. 60 is a memory cell array of m rows × n columns configuration, 61 is a row decoder, 62 is a column decoder, 63 is a word line, 64 is a bit line, and 65 is a line decoder. , 66 is a switch MOS, 67 is a memory cell, and 68 is an input / output terminal.

In the figure, the row decoder 61 selects one row from the m rows, and the column decoder 62 selects one column from the n columns. As a result, a bit is written or read from the input / output terminal 68 in any one memory cell 67.

FIG. 9 is a circuit diagram showing a specific example of the row decoder 61 and the column decoder 62 of the memory having the random access structure shown in FIG. 8. 69a to 69n are address input terminals and 70a to 70n.
Is an AND gate, 71a to 71n are output terminals, and 72a to 72n are inverters.

In the figure, when an address is input to the address input terminals 69a to 69n, one of the output terminals 71a to 71n is selected. When the value of the address is sequentially increased by 1, the output terminals 71a to 71n are selected one after another. In this specific example, when a random address is input, any of the output terminals 71a to 71n can be randomly selected.

FIG. 10 shows the row decoder 61 or the column decoder in FIG.
62 is a block diagram showing another specific example of 62, in which 72a is a DFF with a set, 72b to 72n are DFFs with a reset, 73 to 75 are input terminals, and 76a to 76n are output terminals.

In the figure, when input terminal 74 is activated, DFF7
Only for 2a, the Q output is "H" (high level), the Q outputs of DFF72b to 72n are "L" (low level), and the output terminal 76a is selected. After that, when a clock is input from the input terminal 75 while keeping the input level from the input terminal 73 at "L", the output terminals 76b to 76n are sequentially selected for each clock. That is, such a decoder can also be used in the memory unit of the above-described embodiment for serial access.

〔The invention's effect〕

As described above, according to the present invention, by the simple control of offsetting the write address and the read address, writing and reading of the periodicity information signal in the memory section are continuously performed in an arbitrary phase relationship. , It is possible to prevent the write address and the read address from being coincident with each other during the writing and reading periods of the unit period of the periodicity information signal and one of them overtaking the other,
An excellent effect is obtained in that the memory control is simplified by eliminating the need for delay means for the periodicity information signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a serial access memory device according to the present invention, FIG. 2 is a block diagram showing a specific structure of the address control block shown in FIG. 1, and FIG. 3 is a write operation shown in FIG. FIG. 5 is a diagram showing the timing relationship of the drive signals of the address register, write set register and read set register, FIG. 4 is a diagram showing an example of the phase relationship between the write address set signal and the read address set signal in FIG. 2, and FIG. Is a diagram showing an example of the change in the phase relationship between the write address set signal and the read address set signal, FIG. 6 is a view showing the transition of the write address and the read address with respect to the phase relationship of FIG. 5, and FIG. FIG. 8 is an explanatory diagram of address offset, and FIG. 8 is a block diagram showing the basic structure of the memory mat in FIG. Click view, Figure 9 and Figure 10 is block diagram showing a specific example of a decoder in each FIG. 8, FIG. 11 basic explanatory view of the operation of field memories, Fig. 12 and 13
FIGS. 14A and 14B are diagrams showing transitions of a write address and a read address in a conventional field memory, respectively, and FIGS. 14 and 15 are diagrams showing a field relation of a read video signal with respect to FIGS. 12 and 13, respectively. . 1 ... write address register, 2 ... read address register, 3 ... write set register, 4 ...
Read set register, 5a to 5d ... Memory mat, 6
...... Selector, 7 …… Address register.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tsugumi Matsumoto 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Home Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Kazuo Kondo 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Shikisha, Ltd., Home Appliance Research Laboratory, Hitachi, Ltd. (56) Reference JP-A-51-2356 (JP, A)

Claims (1)

[Claims] 1. A write address register for generating a write address, a read address register for generating a read address, a selector for alternately selecting the write address and the read address, the selected write address and the read address. In a serial access memory device having a memory section for alternately writing and reading the periodicity information signal, the number of accesses of the memory section is set to the number of addresses required to store a unit cycle of the periodicity information signal. And a read set register that subtracts a predetermined value for each unit cycle of the periodicity information signal and a read set register that captures the count value of the write set register immediately before the subtraction operation in the write set register. Provide and write to the memory section The count value of the write set register is loaded into the write address register at each start time point of each unit cycle of the periodicity information signal, and the count value is read out each time the unit cycle of the periodicity information signal is read from the memory unit. The count value fetched in the read set register is loaded into the read address register, and a predetermined value for decrementing the count value in the write set register is used to store the number of addresses in the memory section and the unit cycle of the periodicity information signal The difference from the required number of addresses is made smaller, and the read timing of the count value in the read set register is set to the number of addresses in the memory section after the count value of the write set register is loaded into the write address register. Address of difference from the number of addresses required to store the unit period of the periodicity information signal A serial access memory device comprising means for setting the number to approximately the midpoint within a period until writing is performed in the memory section.