JPH0750449B2 - cache - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache, and more particularly to a cache capable of reducing a test time of a tag address stored in a tag memory.

[Prior Art] FIG. 2 is a block diagram showing an example of a conventional cache.

With reference to FIG. 2, the cache includes memory planes 1 and 2 forming a data memory, a tag memory 3, a set address (middle-order address) line 4, and a data line 8 for inputting / outputting data to / from the memory plane 1. , The data line 9 for inputting / outputting data to / from the memory plane 2, and the address line 10 in the block
A selector 11 for selecting the data on the data lines 8 and 9 according to the intra-block address line 10, a data pin 12, an address output circuit 13, a trigger signal line 14 for activating the address output circuit 13, and a counter 15. , Address pin 16, tag address lines 17 and 18, comparator 19, hit signal line 2
Includes 0, replace gate 21, and tag address line 22.

The memory plane 1 stores the data of the address 0 in the (lower address) block. The memory plane 2 stores the data of the address 1 in the block. Tag memory 3
Has a plurality of tag buffers and stores tag addresses of data in the memory plane 1 and the memory plane 2. The set address (middle level address) line 4 gives an address to specify the storage location in the memory plane 1, the memory plane 2, and the tag memory 3. Therefore, the storage location 5 is provided as a storage location of one data in the memory plane 1, and the storage location 6 is provided as a storage location of one data in the memory plane 2.
The tag memory 3 is provided with a tag buffer 7 that stores the tag addresses of the data in the storage locations 5 and 6.

The data line 8 inputs / outputs data to / from the memory plane 1. The data line 9 inputs / outputs data to / from the memory plane 2. The intra-block address line 10 selects the address indicating which of the data lines 8 and 9 is to be selected by the selector 11
To give to. The selector 11 selects the data on the data lines 8 and 9 in accordance with the given intra-block address. The data pin 12 is connected to the data line selected by the selector 11.

The address output circuit 13 outputs an address for accessing the data from the external memory when replacing the data in the storage location corresponding to a certain set address in the data memory. The trigger signal line 14 gives a trigger signal for activating the address output circuit 13 to the address output circuit 13. The counter 15 counts the number of address outputs of the address output circuit 13.

The address pin 16 is a pin to which an address for accessing the cache and an address for accessing the external memory are input. The tag address line 17 is a signal line for comparing the tag address in the tag buffer 7 with the accessed tag address. The tag address 18 is a signal line for outputting the tag address of the tag buffer 7 selected by the set address line 4. Comparator 19 is a tag address line
Compare tag addresses of 17,18. The hit signal line 20 is
When the comparison results of the comparator 19 are coincident (hit), 1 is output, and when they are not coincident (miss), 0 is output. The replace gate 21 transmits to the tag memory 3 side in order to replace the tag address accessed at the time of the comparator miss. The tag address line 22 is a signal line for writing the tag address to be replaced in the tag memory 3.

Next, the operation will be described. When the cache is accessed, it checks if there is data at the address entered on address pin 16. If there is a matching tag address, the data is retrieved from the corresponding data storage location. If there is no matching tag address,
That is, in the case of a miss, there is a high possibility that the data will be accessed again, so the data memory is replaced.

Explain in detail. First, the address is address pin 16
Will be entered more. It is assumed that the tag buffer 7 is selected by the set address. The tag address of the tag buffer 7 and the accessed tag address are compared by the comparator 19, and a miss signal is output. Due to the miss signal, the tag address is input from the replace gate 21 to the tag buffer 7. In parallel with this, the data of the address input to the external memory is accessed. This data is input to the memory plane selected by the selector 11 by the in-block address.

Then, in order to complete this replacement, it is necessary to input data to all the provided memory planes. Therefore, the address is output from the cache to the external memory. On the other hand, the address output circuit 13 is triggered by the counter 15, and the address of another memory plane is output from the address pin 16 to the external memory. The counter 15 outputs a trigger signal according to the number of times of the replacement operation, that is, the number of memory planes, and the address output circuit 13 sequentially outputs the addresses of the data to be taken. When the trigger signal for fetching data is stopped from being output, the cache stops fetching data. Then, the address output circuit 13 stops the address output. This completes the replacement operation.

[Problems to be Solved by the Invention] Since the conventional cache is configured as described above, the tag address cannot be directly written in the tag memory. Therefore, reading is performed with the tag address that causes a comparison miss, and the tag address is rewritten by the replacement operation that occurs. In this replacement operation, the tag memory is rewritten and the data memory is rewritten. For example, in the case of the conventional example shown in FIG. 2, the tag address stored in the tag buffer 7 is rewritten and stored in the storage location 5 of the memory plane 1 and the storage location 6 of the memory plane 2. Data is rewritten. Therefore, the rewriting of the data memory requires access to the external memory several times. Until the rewriting of the data memory is completed, the cache cannot be put into the next operation, so that it takes some time to rewrite the tag memory.

However, when the tag memory is tested, there is a problem that it takes time to write all the corresponding storage locations of the data memory.

Therefore, the present invention has been made in order to solve the above problems, and when the tag address stored in the tag memory is tested, it is possible to shorten the test time when the rewriting is necessary. The purpose is to provide a secure cache.

[Means for Solving the Problems] A cache according to the present invention is a data memory having a tag memory for storing a tag address and a plurality of memory planes for respectively storing data according to the tag address stored in the tag memory. And an address for rewriting the data stored in each of the plurality of memory planes according to the comparison result of the comparison means for comparing the address input from the outside with the tag address stored in the tag memory. And an output unit for outputting a tag address stored in the tag memory, and an output unit for stopping the output of the address by the output unit to prevent the data stored in each of the plurality of memory planes from being rewritten. It is configured with.

[Operation] In the cache according to the present invention, when the tag address stored in the tag memory is tested, the data stored in each of the plurality of memory planes is prevented from being rewritten, so that the data stored in the tag memory is stored. The test time when the tag address is rewritten can be shortened.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the structure of a cache according to an embodiment of the present invention.

With reference to FIG. 1, a part different from the conventional example shown in FIG. 2 will be particularly described. The cache of this embodiment is provided with a test pin 23 for disabling the counter 15 which counts the number of times the cache outputs an address for accessing the external memory at the time of replacement. The other configurations are the same as those shown in the conventional example, and the description thereof will be omitted.

The operation of rewriting the tag buffer 7 at the time of testing the tag memory 3 will be described. Since the tag buffer 7 is rewritten, the tag address to be written and the tag buffer 7
A set address designating the is input from the address pin 16. As a result, a mismatch occurs in the comparator 19 and the comparator miss signal is input to the replace gate 21. Then, the tag address input from the address pin 16 is transmitted to the tag address line 22 through the replace gate 21, and the tag address is rewritten and stored in the tag buffer 7.

At this time, a signal indicating that the test is being performed is input to the test pin 23. This allows counter 15
Are disabled and the address output circuit 13 is not provided with a trigger signal. Therefore, the address output circuit 13 stops outputting the replacement address. As a result, the cache does not access data to external memory. Therefore, the rewriting of the tag buffer 7 ends at this point. Therefore, the rewriting time can be shortened. In addition, by reducing the number of accesses to the external memory for replacing data, it is possible to reduce the amount of description of the operation when a test program is created, and reduce the load of test program creation work. it can. Further, there is an effect that a storage area such as a tester for storing the test program can be reduced.

In this embodiment, the address pin 16 is shown as being commonly used as the replacement address output pin and the address input pin when the cache is accessed from the MPU, but it may be separated into separate pins. .

As described above, according to the present invention, when the tag address stored in the tag memory is tested, the address for rewriting the data stored in each of the plurality of memory planes is output. By stopping the rewriting, the data stored in each of the plurality of memory planes is prevented from being rewritten, and the test time when the tag address of the tag memory needs to be rewritten can be shortened by the rewriting time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a cache according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional cache. In the figure, 1 and 2 are memory planes, 3 is a tag memory, 4 is a set address line, 5 and 6 are storage locations, 7 is a tag buffer, 8 and 9 are data lines, 10 is an intra-block address line, and 11 is a selector. , 12 is a data pin, 13 is an address output circuit, 14 is a trigger signal line, 15 is a counter, 16 is an address pin, 17, 18, 22 are tag address lines, 19 is a comparator, 20 is a hit signal line, and 21 is a replace The gate and 23 are test pins. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A tag memory for storing a tag address, a data memory having a plurality of memory planes for respectively storing data according to the tag address stored in the tag memory, an address inputted from the outside, and the Comparing means for comparing the tag address stored in the tag memory, and output means for outputting an address for rewriting the data stored in each of the plurality of memory planes according to the comparison result of the comparing means, When performing a test of the tag address stored in the tag memory, the output means stops the output of the address to prevent the rewriting of the data stored in each of the plurality of memory planes. cache.