JPH0750551B2 - Semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device.
Dynamic type RAM (random access memory) in which the column system selection circuit is composed of static type circuits
It is related to the technology that is effectively used.

[Background technology]

In the semiconductor memory device, for example, if the write enable signal ▲ ▼ is at high level, the read operation is performed, and if it is at low level, the write operation is performed. However,
In the read operation state in which the write enable signal ▲ ▼ is set to the high level, if the signal ▲ ▼ is set to the low level for an extremely short time (several ns) due to pulse noise, erroneous writing to the selected memory cell may occur. The problem of going away arises. In particular, a memory cell coupled to the word line is formed by configuring the column system selection circuit by a static type circuit and changing the column address signal while the word line is kept selected to switch the selected data line one after another. In a dynamic RAM that has a continuous access mode function such as a so-called static column mode or page mode in which continuous read / write operations are performed, memory cells are placed in a selected state for a relatively long time. Because it is
The probability of erroneous writing due to the noise increases. (For dynamic RAM, see, for example, Nikkei McGraw-Hill, Inc., July 18, 1983, "Nikkei Electronics," pages 169-193).

[Object of the Invention]

An object of the present invention is to provide a semiconductor memory device having an input circuit that prevents malfunctions due to pulse noise.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a latch circuit that is set by an operation mode signal supplied from an external terminal and its delay signal and that is reset by the delay signal is provided, and an internal timing signal according to the operation mode signal is formed from its output signal. Is.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a dynamic RAM according to the present invention. Although not particularly limited, each circuit element and circuit block in the figure is formed by a known semiconductor integrated circuit manufacturing technique on a semiconductor substrate such as one single crystal silicon.

As shown, the 1-bit memory cell MC comprises an address selecting MOSFET Qm and an information storage capacitor Cs whose one electrode is coupled to Qm and whose other electrode is maintained at the power supply voltage level of the circuit. , Information of logic "1", "0" is stored in correspondence with the form of whether the capacitor Cs has a charge or not.

To read information, the MOSFET Qm is turned on, the capacitor Cs is coupled to the common data line DL, and it is sensed how the potential of the data line DL changes according to the amount of charge accumulated in the capacitor Cs. Done by.

Although not particularly limited, a dummy cell DC is provided to form a reference potential for detecting such a minute signal. The dummy cell DC is made under the same manufacturing conditions and the same design constants as the memory cell MC, except that the capacitance value of the capacitor Cd is about half that of the capacitor Cs of the memory cell MC. The capacitor Cd has a timing signal φd.
It is reset (discharged) by the receiving MOSFET Qd 'prior to addressing. As above, the capacitor Cd
Has a capacitance value set to about half the capacitance value of the capacitor Cs, thus forming a reference voltage equal to about half the read signal from the memory cell MC.

In the figure, SA is a sense amplifier that expands such a potential change difference caused by the addressing to a sense period determined by a timing signal (sense amplifier control signal) φpa, and is a pair of complementary data arranged in parallel. Line D
The input / output node is connected to L, ▲ ▼. This sense amplifier SA is composed of a pair of cross-connected MOSFETs Q1, Q2.
, And by these positive feedback actions, the complementary data line DL,
The small signal appearing in ▲ ▼ is amplified differentially.

The number of memory cells coupled to each of the complementary data lines DL, ▲ ▼ is made equal to each other in order to improve detection accuracy. One dummy cell is coupled to each of the complementary data lines DL and ▲ ▼. Each memory cell MC is coupled between one word line WL and one of the complementary pair data lines. When each word line WL intersects both of the data line pairs, the noise component given to each data line via the undesired coupling capacitance when the potential of the word line WL is changed is a common mode noise. It is regarded. Such common mode noise is substantially ignored by the differential sense amplifier SA.

As a result of addressing, complementary data line pair DL, ▲
One of the pair of dummy word lines DWL, ▲ ▼ is selected so that when the memory cell MC connected to one of the ▼ is selected, the dummy cell DC is always connected to the other data line.

During the above addressing, the stored information in the memory cell MC which is about to be destroyed is restored by directly receiving the high level or low level potential obtained by the sensing operation. However, if the high level falls below a certain level with respect to the power supply voltage Vcc as described above, a malfunction occurs where it is read as a logic "0" during repeated reading and rewriting. The active restore circuit AR is provided to prevent this malfunction. This active restore circuit AR
Has a function of selectively boosting the voltage of the power supply voltage Vcc to only the high level signal without affecting the low level signal by the timing signal φrs.

Complementary data line pair D shown as a representative in FIG.
L, ▲ ▼ are selectively coupled to the common complementary data lines CDL, ▲ ▼ via the column switch circuit CW. That is, the complementary data lines DL, ▲ ▼ and the common complementary data line C
Column switch MOSFETs Q3, Q4 controlled by the output of the column decoder C-DCR are provided between DL and ▲ ▼. Other similar complementary data lines are also provided with MOSFETs Q5 and Q6 similar to the above.

The common complementary data line pair CDL, ▲ ▼ is coupled to the output terminal of the data input buffer DIB and the input terminal of the data output buffer DOB including the main amplifier. The input terminal of the data input buffer DIB is coupled to the external terminal Din to which write data is supplied. The output terminal of the data output buffer DOB is coupled to the external terminal Dout for sending the read data.

The data input buffer DIB and the data output buffer DOB are composed of CMOS static circuits, although not particularly limited thereto. The data input buffer DIB is activated by the timing signal φrw during the write operation,
In the operating state, the write signal supplied from the external terminal Din is transmitted to the common complementary data line CDL, ▲ ▼.
Also, for read operation, the data input buffer DIB is
The output is brought to a high impedance state by the timing signal φrw. The data output buffer DOB is brought into an operating state at the time of the reading operation by the timing signal rw, and in the operating state, the read data signal is sent from the external terminal Dout.

The row decoder R-DCR and the column decoder C-DCR receive an internal complementary address signal formed by the row address buffer R-ADB and the column address buffer C-ADB, and receive one word line, a dummy word line, and a column switch. Form a selection signal to be supplied to That is, these decoders R-DCR and C-DCR perform addressing of memory cells and dummy cells. The row address buffer R-ADB outputs a row address strobe signal ▲
Is activated by the timing signal φar formed by ▼, and in that operating state, the address signals AX0 to AXi supplied from the external terminals in synchronization with the row address strobe signal ▲ ▼ are taken in and held, and the row decoder Tell R-DCR. Row decoder RD
The CR decodes the transmitted address signal and performs a predetermined word line / dummy word line selection operation according to the word line selection timing signal φx.

On the other hand, the column address buffer C-ADB is not particularly limited, but is composed of a CMOS static type circuit, its operation is controlled by the timing signal φac formed by the column address strobe signal ▲ ▼, and the address supplied from the external terminal is used. Accepts signals AY0-AYi. The internal complementary address signal formed by the column address buffer C-ADB is transmitted to the column decoder C-DCR which is also composed of a CMOS static type circuit. The operation of the column decoder C-DCR is controlled by the data line selection timing signal φy, the address signal transmitted thereto is decoded, and the data line selection operation is performed in synchronization with the data line selection timing signal φy.

The timing control circuit TC receives the row address strobe signal ▲ ▼, the column address strobe signal ▲ ▼ and the write enable signal ▲ ▼ supplied through the external terminals, and forms various internal timing signals.

FIG. 2 shows a circuit diagram of an embodiment of the input circuit of the write enable signal () included in the timing control circuit TC.

Write enable signal supplied from the external terminal ▲ ▼
Is taken into an internal circuit via a NOR gate circuit G1 although not particularly limited. The RAS system timing signal 1 is supplied to the other input of the gate circuit G1. The timing signal 1 is a signal that is set to a low level when the row address strobe signal () is set to a low level. As a result, the write enable signal ▲ ▼ is fetched only in the chip selection state, in other words, in the memory access state.

On the one hand, the output signal WE of the gate circuit G1 is inverted by the inverter circuit IV and delayed via the delay circuit DEL. Delay signal by this delay circuit DEL ▲ ▼
Is supplied to one input of the NOR gate circuit G2. On the other hand, the output signal WE of the gate circuit G1 is supplied to one input of a NOR gate circuit G3. The other inputs of the two NOR gate circuits G2 and G3 and their outputs are cross-connected. This allows two NOR gate circuits G2 and G3
Are connected in a latch configuration.

An internal write signal W1 is formed from the output terminal of the NOR gate circuit G2. Although not particularly limited, the write signal W1 is supplied to the pulse width expansion circuit PG, where the write signal W2 having the expanded pulse width is formed. The write operation using the two write signals W1 and W2 will be apparent from the description below.

FIG. 3 is a timing chart showing an example of the write operation of this embodiment.

When the row address strobe signal ▲ ▼ changes from high level to low level, the timing control circuit TC
A timing signal φar (not shown) is generated. The row address buffer R-ADB fetches the address signal supplied from the external terminal by the timing signal φar,
Hold it. This address signal is applied to the row decoder R-
Supplied to DCR. The row decoder R-DCR decodes the address signal to synchronize one word line WL and a dummy word line (not shown) corresponding thereto with a word line selection timing signal φx (not shown). The high level selection state. As a result, the operation of selecting one word line and the dummy word line is performed. After this, timing signals φpa1 and φa2 (not shown) for the sense amplifier
(Not shown) is formed, and the sense amplifier SA operates to amplify the stored information of the memory cell read to the complementary data line DL, ▲ ▼.

Next, when the column address strobe signal ▲ ▼ changes from the high level to the low level, the timing control circuit TC sets the timing signal φac (not shown) to the high level. By the high level of the tamming signal φac, the address buffer is brought into the operating state and the address signal supplied from the external terminal at that time is fetched.

The column decoder C-DCR is a column address buffer C.
-By decoding the internal complementary address signal supplied from ADB, the data line selection timing signal φy
A data line selection signal is formed in synchronization with (not shown).

At this time, for example, if the write enable signal ▲ ▼ is a high-level read operation, the data output circuit DOB is brought into the operating state, and the first output signal D0 is read to the external terminal Dout. However, when the write enable signal ▲ ▼ is temporarily set to a low level due to pulse noise as shown in FIG.
In response to this, the output signal WE of G1 is temporarily set to the high level. As a result, the output node of the NOR gate circuit G3
N1 is temporarily set to low level. However, the NOR gate circuit G2 has a delay signal ▲ ▼ of the delay circuit DEL.
Output signal W1 is maintained at a low level. In other words, the delay circuit DEL
The low level of the write enable signal ▲ ▼ having a pulse width equal to or less than the delay time Td of 1 is regarded as noise, and its capture is prohibited.

On the other hand, as shown by the dotted line in the figure, when the write enable signal ▲ ▼ is set to the low level over the delay time Td, after the delay time Td, the inputs of the NOR gate circuit G2 are both at the low level (logic " 0 "), and its output signal W1 rises to high level. After that, even if the write enable signal ▲ ▼ is set to the high level, the output signal N1 of the NOR gate circuit G3 is maintained at the low level by the high level of the output signal W1, so that the output signal W1 remains at the high level. To be done. Then, when the delay signal ▲ ▼ is set to the high level due to the rise of the signal ▲ ▼ to the high level, the output signal W1
Is set to low level. That is, once the latch circuit is set (the output W1 is at the high level), the output signal W1 is at the high level for at least the delay time Td.

The pulse expansion circuit PG receives the timing signal W1 and
Form the stretched pulse signal W2. For example, the data input buffer DIB is in the operating state during the period t1 in which both the write signals W1 and W2 are at the high level. The write operation is completed by the low level of the write signal W1, the data input buffer DIB is made inactive, and its output is brought to a high impedance state. Further, the column switch circuit CW is also deactivated. Then, the write signal W1
Of the common complementary data lines CDL, ▲
A write recovery operation is performed in which ▼ is short-circuited. By such a write recovery operation,
The next write operation / read operation that is subsequently performed can be performed at high speed.

[Effect]

(1) By providing a latch circuit that is set by an operation mode signal supplied from an external terminal and its delay signal and reset by the delay signal, and by fetching a signal in the set state of the latch circuit as an internal operation mode signal It is possible to prevent an erroneous operation due to the input of a pulse having a delay time or less in the delay circuit.

(2) When the operation mode signal supplied from the external terminal is used as a signal for instructing a read / write operation, it is possible to prevent an erroneous operation in which a write operation is performed during the read operation. To be

(3) By applying the present invention to a dynamic RAM having a continuous access mode function such as a column static mode, it is possible to reliably prevent erroneous writing which is likely to occur in a memory access state for a relatively long time. The effect that can be obtained is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, the specific circuit configuration of the latch circuit is set when the delay signal of the operation mode signal supplied from the external terminal and the signal supplied from the external terminal are both set to a level indicating the same operation mode. Anything can be used as long as it is reset when the delay signal is set to the level instructing the cancellation. Further, in FIG. 1, the column address selection circuit may also be configured by a dynamic type circuit. Even in this case, a continuous access function such as page mode can be realized. Further, the continuous access mode function is not particularly required. Further, the operation mode signal may be an output enable signal in addition to the one for instructing the write / read operation.

[Field of application]

In addition to dynamic RAM, this invention is a static R
It can be similarly applied to AM.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of a dynamic RAM according to the present invention, and FIG. 2 is an implementation of a write enable signal input circuit included in a timing control circuit TC thereof. FIG. 3 is a circuit diagram showing an example, and FIG. 3 is a timing diagram showing an example of the operation. MARY ... Memory array, MC ... Memory cell, DC ... Dummy cell, CW ... Column switch, SA ... Sense amplifier,
AR ... Active restore circuit, R-DCR ... Row decoder, C-DCR ... Column decoder, R-ADB ... Row address buffer, C-ADB ... Column address buffer, DOB ... Data output buffer, DIB ... … Data input buffer, TC… Timing control circuit, G1 to G3… NOR gate circuit, IV… Inverter circuit, DEL… Delay circuit, P
G: Pulse width expansion circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-56-85930 (JP, A) "Nikkei Electronics" No. 369 (Published May 20, 1985 Nikkei McGraw-Hill Company) PP. 195-219

Claims (1)

[Claims] 1. A memory array in which dynamic memory cells are arranged in a matrix at intersections of a plurality of word lines and data lines, and a selection signal for the word lines and data lines of the memory array is formed and at least data lines of the data lines are formed. An address selection circuit in which a column circuit that forms a selection signal is configured by a static type circuit, a data input buffer that performs a write operation to the memory cell selected by the address selection circuit, and a selection circuit selected by the address selection circuit The data output buffer that outputs the read signal from the memory cell and the address strobe signal and the write enable signal that are supplied from the external pin determine the operation mode and generate the timing signal necessary for the specified operation mode. With a timing control circuit to The timing control circuit is set by the delay signal and the write enable signal supplied from the external terminal,
A latch circuit that is reset by the delay signal to form a write control signal; and a pulse width expansion circuit that receives the write control signal output from the latch circuit and expands the pulse width thereof. A semiconductor memory characterized in that a data input buffer is activated to perform a write operation, and a signal transmission path for transmitting a write signal formed by the data input buffer is short-circuited during an expansion time by the pulse width expansion circuit. apparatus.