JPH0750707B2 - Method for forming interlayer insulating film through hole - Google Patents
Method for forming interlayer insulating film through holeInfo
- Publication number
- JPH0750707B2 JPH0750707B2 JP24500888A JP24500888A JPH0750707B2 JP H0750707 B2 JPH0750707 B2 JP H0750707B2 JP 24500888 A JP24500888 A JP 24500888A JP 24500888 A JP24500888 A JP 24500888A JP H0750707 B2 JPH0750707 B2 JP H0750707B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- hole
- interlayer insulating
- window
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title description 22
- 239000011229 interlayer Substances 0.000 title description 17
- 229920001721 polyimide Polymers 0.000 claims description 39
- 239000004065 semiconductor Substances 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 239000010410 layer Substances 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 8
- 239000007789 gas Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 4
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置の層間絶縁膜にスルーホー
ルを形成方法に関する。The present invention relates to a method for forming a through hole in an interlayer insulating film of a semiconductor integrated circuit device.
〔従来の技術〕 従来、半導体集積回路装置の多層配線を形成する場合、
配線層間には層間絶縁膜を形成して互いに絶縁を図り、
接続する部分のみ層間絶縁膜に窓、いわゆるスルーホー
ルを開けて、そのスルーホールを金属層で埋めて層間の
配線を接続していた。また、この層間絶縁膜として、通
常、二酸化シリコン膜が多く使用されている。しかしな
がら、この二酸化シリコン膜を形成する際に、半導体基
板をかなり高温に熱する必要があり、この高い温度のた
めにアルミニウム金属蒸着層にヒロックなどの微小突起
を生じ、層間絶縁膜に多数をピンホールを発生させる問
題がある。また、この層間絶縁膜を厚く形成するため
に、科学的気相成長法等で膜を成長すると、アルミニウ
ムとの膨張係数の違いにより層間絶縁膜に亀裂を生じた
りする等問題がある。従って、この二酸化シリコン膜の
代りに、例えば、特公昭51−44871号にはポリイミド樹
脂層を層間絶縁膜として使用することが提案されてい
る。このポリイミド樹脂層にスルーホールを開ける場合
には、酸素プラズマを用いた等方性プラズマエッチング
法でスルーホールを開けている。[Prior Art] Conventionally, when forming a multilayer wiring of a semiconductor integrated circuit device,
An interlayer insulating film is formed between the wiring layers to insulate each other,
A window, a so-called through hole, is opened in the interlayer insulating film only at the connecting portion, and the through hole is filled with a metal layer to connect the wiring between the layers. A silicon dioxide film is often used as the interlayer insulating film. However, when forming this silicon dioxide film, it is necessary to heat the semiconductor substrate to a considerably high temperature. Due to this high temperature, minute projections such as hillocks are generated in the aluminum metal vapor deposition layer, and a large number of pins are formed in the interlayer insulating film. There is a problem of generating holes. Further, when a film is grown by a chemical vapor deposition method or the like to form the interlayer insulating film thick, there is a problem that a crack is generated in the interlayer insulating film due to a difference in expansion coefficient with aluminum. Therefore, in place of this silicon dioxide film, for example, Japanese Patent Publication No. 51-44871 proposes to use a polyimide resin layer as an interlayer insulating film. When forming a through hole in this polyimide resin layer, the through hole is formed by an isotropic plasma etching method using oxygen plasma.
上述した従来のスルーホール形成方法では、下地の表面
の段差形状や寸法の違いにより局所的に膜厚に差がある
ため、膜厚の薄い所にスルーホールを形成する場合に
は、エッチング時間の影響で他のスルーホールより大き
なスルーホールが開けられるという問題点がある。ま
た、別法として、異方性エッチング法、例えば、リアク
ティブエッチング法によりスルーホールを形成する場合
には、開けられたスルーホールの断面形状が急峻にな
り、コンタクトとなる金属の接着力が弱く剥れを引起し
導通不良となる問題がある。In the above-described conventional through-hole forming method, since the film thickness is locally different due to the difference in the step shape and the size of the surface of the underlayer, when forming the through-hole in the place where the film thickness is thin, the etching time As a result, there is a problem that a larger through hole can be opened than other through holes. Alternatively, when a through hole is formed by an anisotropic etching method, for example, a reactive etching method, the cross-sectional shape of the opened through hole becomes steep, and the adhesive force of the metal serving as the contact becomes weak. There is a problem that it causes peeling and causes poor conduction.
本発明の目的は、層間絶縁膜と接着力のより高いコンタ
クトが得られるとともに安定した寸法のスルーホールが
得られる層間絶縁膜スルーホール形成方法を提供するこ
とにある。An object of the present invention is to provide a method of forming an interlayer insulating film through hole, which can obtain a contact having a higher adhesive force with an interlayer insulating film and can obtain a through hole having a stable size.
本発明の層間絶縁膜スルーホール形成方法は、一主面上
の配線を含めた半導体基板表面にシリコンを含んだ第１
のホリイミド膜と前記第１のポリイミド膜上に重ねてシ
リコンを含まない第２のポリイミド膜を形成してなる層
間絶縁膜形成工程と、前記第１のポリイミド膜に第１の
窓を形成するとともに前記第２のポリイミド膜に前記第
１の窓より所定の大きさだけ大きく且つ前記第１の窓と
同一中心軸をもつ第２の窓を形成する工程とを含んで構
成される。The interlayer insulating film through-hole forming method of the present invention is a first method that includes silicon on the surface of a semiconductor substrate including wiring on one main surface.
And an interlayer insulating film forming step of forming a second polyimide film containing no silicon on the polyimide film and the first polyimide film, and forming a first window in the first polyimide film. Forming a second window in the second polyimide film that is larger than the first window by a predetermined size and has the same central axis as the first window.
次に、本発明について図面を参照して説明する。第１図
は本発明の第１の実施例を説明するための半導体チップ
の工程順に示した半導体チップの断面図である。この実
施例は、２ミクロン程度の設計ルールにおけるLSIに適
用した場合である。まず、第１図（ａ）に示すように、
半導体基板１上に、公知の方法により、例いば、４μｍ
程度の幅をもつアルミニウムの第１の配線２を形成す
る。次に、アルミニウムの第１の配線２を含む半導体基
板１の表面にシリコンを含んだポリイミド溶液をスピン
コータにより半導体基板に摘下してポリイミドの塗布膜
を形成し、窒素雰囲気中約200℃以下の温度で乾燥して
厚さ0.8μｍの第１のポリイミド膜３を形成する。次
に、第１図（ｂ）に示すように、シリコンを含まないポ
リイミド液をスピンコータにより半導体基板に摘下し、
厚さ0.8μｍのポリイミド塗布膜を形成し、窒素雰囲気
中で段階的に温度上昇させ、約400℃以下で熱処理して
約1.0μｍ程度の第２のポリイミド膜４に成膜する。次
に、第１図（ｃ）に示すように、第２のポリイミド膜４
の上に、第２のポリイミド膜４より厚い約２μｍの厚さ
のホトレジスト膜５を形成し、ホトリソグラフィ法によ
り窓６を開ける。次に、第１図（ｄ）に示すように、四
ふっ化炭素（CF4）ガスと酸素との混合ガスで圧力5Paに
て異方性エッチング法である逆反応性エッチングを行
い、窓６の底部のポリイミド膜３及び４を除去して窓６
を窓6aに深く形成する。次に、第１図（ｅ）に示すよう
に、ホトリソグラフィ法により窓6aのホトレジスト膜５
を窓6aより大きく除去して、窓6bを形成する。このホト
レジスト膜５をマスクにして、四ふっ化炭素（CF4）ガ
スと酸素との混合ガスで圧力5Paにて異方性エッチング
法である逆反応性エッチングを行い、第１及び第２のポ
リイミド膜３及び４を除去する。このとき、第２のポリ
イミド膜４のみエッチング除去され、第１のポリイミド
膜３はエッチングが進行せず、もとの形状を保つことに
なる。次に、第１図（ｆ）に示すように、通常の溶媒に
てホトレジスト膜５を除去し、金属蒸着法によりアルミ
ニウムの第２の配線７を形成して第１の配線２と接続す
る。このように、スルーホールである窓を段階状にエッ
チングして作れば、第１のポリイミド膜に膜厚の段差が
あっても横方向のエッチングが進まないので、ばらつき
の少ない窓の寸法が得られるだけではなく、配線である
蒸着金属層と層間絶縁膜であるポリイミド膜との密着面
積をより増大させたことになる 第２図は本発明の第２の実施例を説明するための半導体
チップの工程順に示した半導体チップの断面図である。
この実施例は第１の実施例のホトレジスト膜の代りにシ
リコン酸化膜を用いた例である。この実施例の工程は、
第１の実施例の第１図（ｂ）までは同じである。まず、
第２図（ａ）で示すように、圧力100Pa程度のシラン（S
iH4）と酸化窒素（N2O）との混合ガス雰囲気中で、半導
体基板温度を約300℃に加熱し、プラズマ酸化して第２
のポリイミド膜４の上に厚さ0.2μｍのシリコン酸化膜
８を形成する。次に、第２図（ｂ）に示すように、ホト
レジスト膜をシリコン酸化膜８の上に形成し、ホトリソ
グラフィ法によりホトレジスト膜を選択的に除去してホ
トマスクであるホトレジスト膜５を形成する。次に、四
ふっ化炭素（CF4）ガスを主体にした逆反応性エッチン
グを行い、ホトレジスト膜５及びシリコン酸化膜８にス
ルーホールであ窓6cを開ける。次に、第２図（ｃ）に示
すように、第１の実施例の第１図（ｄ）及び（ｅ）で説
明した工程と同じ方法で行い、第１及び第２のポリイミ
ド膜３及び４を選択的に除去してスルーホールである窓
6cをエッチングして窓6dに形成する。このとき、第２の
ポリイミド膜の横方向のエッチングが他の層より進むの
で、第２のポリイミド膜のみ大きい穴が形成される。次
に、第２図（ｄ）に示すように、ふっ化水素（HF）でシ
リコン酸化膜８を徐去し、金属蒸着法により、アルミニ
ウムを蒸着し、アルミニウム金属蒸着層を選択的にエッ
チング除去して、第２の配線７を形成して下層のアルミ
ニウム第１の配線２と接続する。Next, the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a semiconductor chip showing the process sequence of the semiconductor chip for explaining the first embodiment of the present invention. This embodiment is applied to an LSI having a design rule of about 2 μm. First, as shown in FIG. 1 (a),
For example, 4 μm is formed on the semiconductor substrate 1 by a known method.
A first wiring 2 made of aluminum having a width of the order of magnitude is formed. Next, a polyimide solution containing silicon is squeezed onto the semiconductor substrate by a spin coater on the surface of the semiconductor substrate 1 including the first wiring 2 made of aluminum to form a polyimide coating film. It is dried at a temperature to form a first polyimide film 3 having a thickness of 0.8 μm. Next, as shown in FIG. 1 (b), a polyimide solution containing no silicon is dropped on the semiconductor substrate by a spin coater,
A 0.8 μm thick polyimide coating film is formed, the temperature is raised stepwise in a nitrogen atmosphere, and heat treatment is performed at about 400 ° C. or less to form a second polyimide film 4 of about 1.0 μm. Next, as shown in FIG. 1C, the second polyimide film 4
A photoresist film 5 having a thickness of about 2 μm, which is thicker than the second polyimide film 4, is formed thereon, and a window 6 is opened by a photolithography method. Next, as shown in FIG. 1 (d), reverse reactive etching, which is an anisotropic etching method, was performed with a mixed gas of carbon tetrafluoride (CF 4 ) gas and oxygen at a pressure of 5 Pa, and the window 6 Removing the polyimide films 3 and 4 on the bottom of the window 6
Are formed deep in the window 6a. Next, as shown in FIG. 1 (e), the photoresist film 5 of the window 6a is formed by photolithography.
Are removed larger than the window 6a to form the window 6b. Using this photoresist film 5 as a mask, reverse reactive etching, which is an anisotropic etching method, is carried out with a mixed gas of carbon tetrafluoride (CF 4 ) gas and oxygen at a pressure of 5 Pa, to obtain the first and second polyimides. Membranes 3 and 4 are removed. At this time, only the second polyimide film 4 is removed by etching, the etching of the first polyimide film 3 does not proceed, and the original shape is maintained. Next, as shown in FIG. 1 (f), the photoresist film 5 is removed with an ordinary solvent, a second wiring 7 made of aluminum is formed by a metal deposition method, and the second wiring 7 is connected to the first wiring 2. In this way, if the window that is a through hole is etched stepwise, even if there is a step difference in the thickness of the first polyimide film, the etching in the lateral direction does not proceed, so a window size with less variation can be obtained. In addition to the above, the contact area between the vapor-deposited metal layer which is the wiring and the polyimide film which is the interlayer insulating film is further increased. FIG. 2 is a semiconductor chip for explaining the second embodiment of the present invention. FIG. 6 is a cross-sectional view of the semiconductor chip shown in the order of steps.
This embodiment is an example in which a silicon oxide film is used instead of the photoresist film of the first embodiment. The process of this example is
The same applies up to FIG. 1 (b) of the first embodiment. First,
As shown in Fig. 2 (a), silane (S
In a mixed gas atmosphere of iH 4 ) and nitric oxide (N 2 O), the temperature of the semiconductor substrate is heated to about 300 ° C., plasma oxidation is performed, and the second
A 0.2 μm thick silicon oxide film 8 is formed on the polyimide film 4 of FIG. Next, as shown in FIG. 2B, a photoresist film is formed on the silicon oxide film 8, and the photoresist film is selectively removed by the photolithography method to form the photoresist film 5 as a photomask. Next, reverse reactive etching mainly using carbon tetrafluoride (CF 4 ) gas is performed to open a window 6c as a through hole in the photoresist film 5 and the silicon oxide film 8. Next, as shown in FIG. 2 (c), the first and second polyimide films 3 and 3 are formed by the same method as the steps described in FIGS. 1 (d) and (e) of the first embodiment. Window that is a through hole by selectively removing 4
6c is etched to form window 6d. At this time, since the lateral etching of the second polyimide film proceeds more than other layers, a large hole is formed only in the second polyimide film. Next, as shown in FIG. 2 (d), the silicon oxide film 8 is gradually removed with hydrogen fluoride (HF), aluminum is deposited by a metal deposition method, and the aluminum metal deposition layer is selectively removed by etching. Then, the second wiring 7 is formed and connected to the aluminum first wiring 2 in the lower layer.
なお、この実施例で使用したホトレジスト膜は第１の実
施例に用いたレジスト膜と比較してより薄いホトレジス
ト膜て済む。その理由は、通常、四ふっ化炭素（CF4）
ガスを主体にした逆反応性エッチングでは、レジスト膜
は膜減りしないからである。このことは、逆に言えば、
ホトリソグラフィによりレジスト膜に比較的に微細な開
口を形成出来ることが言えるので、この実施例は第１の
実施例よりは利点がある。The photoresist film used in this embodiment is thinner than the resist film used in the first embodiment. The reason is usually carbon tetrafluoride (CF 4 ).
This is because the resist film is not reduced by the reverse reactive etching mainly using gas. To put it the other way around,
Since it can be said that a relatively fine opening can be formed in the resist film by photolithography, this embodiment has an advantage over the first embodiment.
以上説明した実施例以外に、エッチングマスクとして、
ホトレジスト膜やシリコン酸化膜以外に、例えば、アル
ミニウムやチタニウムのような金属膜を使用しても良
く、この場合のエッチング方法は塩素ガスを用いた逆反
応性エッチングを行うことよりスルーホールを形成出来
る。また、これらの金属膜を除去するには、アルミニウ
ムの場合は、温化されたりん酸液に侵けることにより除
去される。チタニウムの場合は、アンモニア水と過酸化
水素水の混合液に侵けることにより除去出来る。Other than the examples described above, as an etching mask,
Other than the photoresist film and the silicon oxide film, for example, a metal film such as aluminum or titanium may be used. In this case, the through hole can be formed by performing the reverse reactive etching using chlorine gas. . To remove these metal films, aluminum is removed by immersing it in a heated phosphoric acid solution. Titanium can be removed by immersing it in a mixed solution of aqueous ammonia and aqueous hydrogen peroxide.
以上説明したように本発明は、シリコンの含むポリイミ
ド膜の上にシリコンの含まないポリイミド膜を重ねて形
成し層間絶縁膜とし、シリコンを含むポリイミド膜に小
さい穴を開けてなるスルーホールを設けたので、シリコ
ンを含まないポリイミド膜に大きい穴を、シリコンを含
むポリイミド膜は横方向のエッチングが進まないので、
このポリイミド膜の膜厚に段差があっても、ばらつきの
少ない穴が得られる。また、二つのポリイミド膜の穴の
大きさでなる段差を設けることにより金属と層間絶縁膜
との接着面積を増加することが出来る。従って、層間絶
縁膜とコンタクトとの密着力をより高められるともに安
定した寸法のスルーホールが得られるという効果があ
る。As described above, according to the present invention, a polyimide film containing no silicon is overlaid on a polyimide film containing silicon to form an interlayer insulating film, and a through hole formed by forming a small hole in the polyimide film containing silicon is provided. So, make a large hole in the polyimide film that does not contain silicon, because the polyimide film that contains silicon does not allow lateral etching.
Even if there is a step in the film thickness of the polyimide film, a hole with less variation can be obtained. Further, by providing a step formed by the size of the holes of the two polyimide films, the adhesion area between the metal and the interlayer insulating film can be increased. Therefore, there is an effect that the adhesion between the interlayer insulating film and the contact can be further enhanced and a through hole having a stable size can be obtained.
第１図は本発明の第１の実施例を説明するための半導体
チップの工程順に示した半導体チップの断面図、第２図
は本発明の第２の実施例を説明するための半導体チップ
の工程順に示した半導体チップの断面図である。 １……半導体基板、２……第１の配線、３……第１のポ
リイミド膜、４……第２のポリイミド膜、５……ホトレ
ジスト膜、６、6a、6b、6c、6d……窓、７……第２の配
線、８……酸化膜。FIG. 1 is a cross-sectional view of a semiconductor chip showing the process sequence of a semiconductor chip for explaining the first embodiment of the present invention, and FIG. 2 is a semiconductor chip for explaining the second embodiment of the present invention. It is sectional drawing of the semiconductor chip shown in order of process. 1 ... Semiconductor substrate, 2 ... First wiring, 3 ... First polyimide film, 4 ... Second polyimide film, 5 ... Photoresist film, 6, 6a, 6b, 6c, 6d ... Window , 7: second wiring, 8: oxide film.
Claims (1)
シリコンを含んだ第一のポリイミド膜と前記第１のポリ
イミオ膜上に重ねてシリコンを含まない第２のポリイミ
ド膜を形成してなる層間絶縁膜形成工程と、前記第１の
ポリイミド膜に第１の窓を形成するとともに前記第２の
ポリイミド膜に前記第１の窓より所定の大きさだけ大き
く且つ前記第１の窓と同一中心軸をもつ第２の窓を形成
する工程とを含んだことを特徴とする層間絶縁膜スルー
ホール形成方法。1. A first polyimide film containing silicon and a second polyimide film containing no silicon are formed on the surface of a semiconductor substrate including wiring on one main surface and on the first polyimide film. And a step of forming a first window in the first polyimide film and forming a second window in the second polyimide film that is larger than the first window by a predetermined size. And a step of forming a second window having the same central axis.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24500888A JPH0750707B2 (en) | 1988-09-28 | 1988-09-28 | Method for forming interlayer insulating film through hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24500888A JPH0750707B2 (en) | 1988-09-28 | 1988-09-28 | Method for forming interlayer insulating film through hole |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0290616A JPH0290616A (en) | 1990-03-30 |
| JPH0750707B2 true JPH0750707B2 (en) | 1995-05-31 |
Family
ID=17127203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24500888A Expired - Lifetime JPH0750707B2 (en) | 1988-09-28 | 1988-09-28 | Method for forming interlayer insulating film through hole |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0750707B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102004009296B4 (en) * | 2004-02-26 | 2011-01-27 | Siemens Ag | Method for producing an arrangement of an electrical component |
| JP2010067650A (en) * | 2008-09-09 | 2010-03-25 | Sharp Corp | Semiconductor device, manufacturing method for the semiconductor device, and power module |
-
1988
- 1988-09-28 JP JP24500888A patent/JPH0750707B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0290616A (en) | 1990-03-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS62295437A (en) | Forming method for multilayer interconnection | |
| JPH0750707B2 (en) | Method for forming interlayer insulating film through hole | |
| JPS607737A (en) | Manufacture of semiconductor device | |
| JPH04127454A (en) | Semiconductor device | |
| JPH05206282A (en) | Manufacturing method of multilayer wiring structure of semiconductor device | |
| JPH0653134A (en) | Method for manufacturing semiconductor device | |
| JPH0428231A (en) | Manufacture of semiconductor device | |
| JPH06244286A (en) | Manufacture of semiconductor device | |
| JP2882065B2 (en) | Method for manufacturing semiconductor device | |
| JPS6035825B2 (en) | Manufacturing method of semiconductor device | |
| JPS6254427A (en) | Manufacture of semiconductor device | |
| JP2770653B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
| JP2873759B2 (en) | Pretreatment method for wet etching of semiconductor device | |
| JPS63182839A (en) | Semiconductor device | |
| JPS6378552A (en) | Formation of throughhole | |
| JP2998719B2 (en) | Semiconductor device | |
| JPS6056295B2 (en) | Manufacturing method of semiconductor device | |
| JPS5932153A (en) | Manufacture of semiconductor device | |
| JPS61154148A (en) | Manufacture of semiconductor device | |
| JPH02151052A (en) | Manufacture of semiconductor device | |
| JPS6193629A (en) | Manufacture of semiconductor device | |
| JPH05308068A (en) | Manufacture of semiconductor device | |
| JPH06349828A (en) | Manufacture of integrated circuit device | |
| JPS60147137A (en) | Forming process of multilayered metallic wiring | |
| JPH01302750A (en) | Semiconductor device |