JPH0750732B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a semiconductor integrated circuit device, and in particular to a large-scale integrated circuit for a specific purpose or a dedicated purpose (hereinafter "Hybrid LSI")
Regarding the pattern layout of.

[Conventional technology]

FIG. 2 is a diagram showing the structure of a conventional hybrid LSI. In the figure, reference numeral 1 denotes a semiconductor substrate, on which a general-purpose functional block WU which is a general-purpose large-scale integrated circuit, and a dedicated functional block SU which is an integrated circuit having a logic storage function for specialization are provided. Is provided, and a bonding pad BP is provided so as to surround these general-purpose function block WU and dedicated function block SU. Then, a wire (not shown) such as a gold wire is connected to the bonding pad BP and a lead frame (not shown).

The conventional hybrid LSI is configured as described above, and the general-purpose functional block WU and the dedicated functional block SU exchange signals with the outside via the bonding pads BP, wires and lead frames.

As described above, since the conventional hybrid LSI has a planar structure, there is a problem that the chip area increases as the number of functions carried by one chip increases.

Therefore, in order to suppress the increase in chip area, mixed LS
It is considered that I has a laminated structure. For example, it is possible to form a hybrid LSI by stacking a plurality of layers in which the general-purpose function block WU and the dedicated function block SU are mixed.

However, such a hybrid LSI having a laminated structure has a new problem that the manufacturing process becomes complicated and the manufacturing period becomes long. The reason is,
The above-mentioned mixed-purpose LSIs for specific purposes or dedicated purposes tend to be different products for each user, in other words, they tend to be in high-mix, low-volume production. This is because different process steps are required for each. For example, considering a mask pattern used in a process step, it means that a mask corresponding to each different product type must be designed from the beginning to prepare a mask.

Therefore, in order to solve the above-mentioned drawbacks, by finishing the layer in which the general-purpose functional integrated circuit unit is formed and the layer in which the dedicated functional integrated circuit unit is formed into a different laminated structure,
A hybrid LSI has been proposed in which at least only the general-purpose function integrated circuit unit can be efficiently manufactured by the same manufacturing process even when there are many kinds of products, and the manufacturing period can be shortened.

FIG. 3 is a diagram showing an embodiment of this proposal. In FIG. 1, reference numeral 1 denotes a P-type semiconductor substrate, a general-purpose functional block WU such as a general-purpose memory or a general-purpose microprocessor is provided at a substantially central portion of the P-type semiconductor substrate 1, and the outer periphery of the general-purpose functional block WU is further provided. A bonding pad BP1 for connection, which serves as a connection point with a dedicated functional block (which will be described later in detail), is provided in the portion to form the first layer FL. This first layer FL can be manufactured by conventional process steps. Reference numeral 2 is an interlayer insulator, and the interlayer insulator 2 is formed by being laminated on the first layer FL. However, in the figure, the P-type semiconductor substrate 1 and the interlayer insulator 2 are shown separately for convenience of description. Then, a dedicated function block SU made up of an integrated circuit having a logical function, a memory function, etc. is provided in a substantially central portion on the interlayer insulator 2, and a bonding pad BP is provided so as to surround the dedicated function block SU, The second layer SL is formed. CT is a connection point provided on the dedicated function block SU corresponding to the bonding pad BP1 for connection for electrical connection between the general purpose function block WU and the dedicated function block SU.
The CT is electrically connected to the bonding pad BP1 for connection.

FIG. 4 is a partial sectional view for further clarifying the laminated structure of FIG. In the figure, n ⁺ diffusion parts 3, 4 for forming a source or a drain on the P-type semiconductor substrate 1
Are formed, and the n ⁺ diffusion portions 3 and 4 are respectively metal-wired by the contact holes CH1 and CH2 and electrically connected to other elements. These contact holes
Except for CH1 and CH2, P-type semiconductor substrate 1 and n ⁺ diffusion parts 3, 4
A field oxide film FO1 is formed on top of it.
Then, a polysilicon gate PG1 is formed by stacking on the field oxide film FO1 so as to correspond to the region of the P-type semiconductor substrate 1 sandwiched between the n ⁺ diffusion parts 3 and 4.
G1 is metal-wired through a contact hole CH3 and electrically connected to other elements. And contact hole CH
Except for 1 to CH3, the insulator layer IL1 is formed by stacking on the field oxide film FO1 and the polysilicon gate PG1, and thus the N-channel transistor which is one element of the general-purpose functional block WU is formed. The above is the configuration of the first layer FL, and the interlayer insulator 2 is laminated and formed on this first layer FL. Then, a dedicated functional block SU is placed on this interlayer insulator 2.
The P-type semiconductor portion 5 and the n ⁺ diffusion portions 6 and 7 are formed to have a constant region in order to form one element constituting
^{The +} diffusion portions 6 and 7 are metal-wiring by contact holes CH4 and CH5, respectively, and are electrically connected to other elements. An oxide film OF is formed so as to surround the P-type semiconductor portion 5 and the n ⁺ diffusion portions 6 and 7 except for the contact holes CH4 and CH5, and corresponds to the P-type semiconductor portion 5 on the oxide film OF. A polysilicon gate PG2 is formed by stacking it at a position to be formed. This polysilicon gate PG2 has a contact hole CH6
With this, metal wiring is performed and electrically connected to other elements.
In addition, interlayer insulation except for contact holes CH4 to CH6
2, Insulator layer I on oxide film OF and polysilicon gate PG2
The L2 is formed by stacking to form an N-channel transistor which is one element of the dedicated function block SU. The above is the second
It is a configuration of the layer SL. Further, the insulating layer IL3 is formed by laminating on the second layer SL, and further the glass coat GC is formed by laminating for device protection.

As described above, the first layer FL is used as a layer for providing only the general-purpose functional block WU, and the connection with the second layer SL is performed by the bonding pad BP1 for connection. Can manufacture this first
Second with dedicated function block SU as described above on layer FL
By providing the layer SL, a hybrid LSI for a specific purpose or a dedicated purpose can be manufactured. In this way, since the hybrid LSI is formed by dividing the layer in which the general-purpose function integrated circuit section is provided and the layer in which the dedicated function integrated circuit section is provided, at least only the general-purpose function integrated circuit section is provided even if there are many types of products. The same manufacturing process enables efficient manufacturing, and the manufacturing period can be shortened.

[Problems to be solved by the invention]

Since the proposed hybrid LSI with a laminated structure is configured as described above, it is necessary to inspect the general-purpose function block WU provided on the first layer FL when the functions of the integrated circuit become complicated. There was a problem that it became difficult.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor integrated circuit device capable of individually inspecting the function of each integrated circuit portion while having a laminated structure. .

[Means for solving problems]

A semiconductor integrated circuit device according to the present invention includes a first layer having a general-purpose function integrated circuit section and a second layer having a dedicated function integrated circuit section.
In a semiconductor integrated circuit device having a plurality of layers and a plurality of bonding pads for electrically connecting to the outside in the uppermost layer, an integrated circuit part of another layer is provided in the uppermost layer. A plurality of bonding pads for inspection are provided which are electrically connected to the integrated circuit portion of the other layer to individually inspect the function of the integrated circuit portion.

[Action]

The semiconductor integrated circuit device according to the present invention is provided with a plurality of inspections for individually inspecting the function of the integrated circuit layer of the other layer by being electrically connected to the integrated circuit portion of the other layer on the outer peripheral portion of the integrated circuit section of the uppermost layer. The bonding pad for use is provided, a signal or the like under a certain condition is applied to the inspection bonding pad, and then the signal or the like output from the bonding pad for inspection is checked to determine the quality of the integrated circuit portion of each layer.

〔Example〕

FIG. 1 is a diagram showing an embodiment of the present invention. In the figure, the first layer FL has the same structure as that of the conventional general-purpose functional integrated circuit, that is, it is connected to the general-purpose functional block WU in the same layout as that of the conventional general-purpose integrated circuit. A bonding pad BP1 is provided. An inspection bonding pad BP2 is provided on the interlayer insulator 2 so as to surround the dedicated functional block SU corresponding to the connection bonding pad BP1. Bonding pad BP1 for connection is bonding pad B for inspection
It is electrically connected to P2 and has a dedicated function block SU
Is electrically connected to a predetermined position of the general-purpose functional block WU through the bonding pad BP2 for inspection.
And the dedicated function block SU are electrically connected to each other. However, in the figure, the P-type semiconductor substrate 1 and the interlayer insulator 2 are shown separately for convenience of description.

Next, a procedure for inspecting only the function of the general-purpose function block WU will be described. First, the general-purpose function block WU from the IC tester (not shown) via the bonding pad BP2 for inspection.
General-purpose function block while applying signals under certain conditions to the
A signal or the like output from the WU via the bonding pad BP2 for inspection is taken out to the IC tester, and based on these signals or the like, the quality of the general-purpose functional block WU is determined in the IC tester. In addition, as a result of the above inspection, when it is determined that the general-purpose functional block WU is good, further, a signal of a certain condition is applied to the semiconductor chip from the IC tester through the bonding pad BP, and output from the semiconductor chip. Captured signals etc. are taken into the IC tester via the bonding pad BP. At this time, the output signal etc. for the input signal etc. is examined, and when the expected output signal etc. for the input signal etc. is obtained, it is determined that the dedicated functional block SU is also good and it is expected. When a different output signal or the like is obtained, it is already determined that the general-purpose function block WU is good, and therefore it is determined that the dedicated function block SU is bad.
In this way, not only the quality of the general-purpose function block WU but also the quality of the dedicated function block SU can be determined.

In the above embodiment, the bonding pad BP1 for connection is provided on the first layer and the bonding pad BP2 for inspection is provided at a position corresponding to the bonding pad BP1 for connection. However, the quality of the general-purpose functional block WU is good or bad instead of the bonding pad BP1 for connection. It is also possible to provide a connection point necessary for determining the above and electrically connect to the bonding pad for inspection BP2, and the same effect as the above-mentioned embodiment can be obtained.

Further, in the above embodiment, the dedicated functional block SU may be configured by a gate array.

Further, in the above embodiment, the inspection bonding pad BP2 and the bonding pad BP are provided so as to surround the dedicated functional block WU.
2. The bonding pad BP can be provided at any position in the second layer SL.

Further, in the above-described embodiment, the two-layer structure in which the second layer SL is laminated on the first layer FL is shown, but a two-layer structure in which the first layer FL is laminated on the second layer SL may be used. Further, it may have a laminated structure of three or more layers.

〔The invention's effect〕

As described above, according to the semiconductor integrated circuit device of the present invention, the functions of the integrated circuit parts of other layers are individually connected to the outer peripheral part of the integrated circuit part of the uppermost layer by being electrically connected to the integrated circuit parts of other layers. Since a plurality of inspection bonding pads for inspection are provided, the function of the integrated circuit portion of each layer can be individually inspected.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment according to the present invention, FIG. 2 is a diagram showing a conventional embodiment, FIG. 3 is a diagram showing a hybrid LSI having a proposed laminated structure, and FIG. FIG. 3 is a partial sectional view of FIG. 3. In the figure, BP2 is a bonding pad for inspection, FL is a first layer, SL is a second layer, SU is a dedicated function block, and WU is a general purpose function block. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (4)

[Claims] 1. A first layer provided with a general-purpose function integrated circuit section and a second layer provided with a dedicated function integrated circuit section are formed in a plurality of layers, and the uppermost layer is electrically connected to the outside. In a semiconductor integrated circuit device having a plurality of bonding pads for performing the above, a plurality of semiconductor integrated circuit units electrically connected to an integrated circuit unit of another layer at the uppermost layer for individually testing the functions of the integrated circuit unit of another layer are provided. 2. A semiconductor integrated circuit device having a bonding pad for inspection of 1. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a two-layer structure in which the second layer is laminated on the first layer. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the dedicated function integrated circuit portion is composed of a gate array. 4. An electrical connection between the inspection bonding pad and the general-purpose function integrated circuit section is made via a connection bonding pad provided in the first layer. The semiconductor integrated circuit device according to item 2 or 3.