JPH0750778B2 - Image sensor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor used in a facsimile, a scanner, etc., and more particularly to an image sensor having a wiring structure in which electrical influence between wirings is reduced.

(Prior Art) There is a conventional image sensor, in particular, a contact image sensor that projects image information of a document or the like on a one-to-one basis and converts it into an electric signal. In this case, the projected image is divided into a large number of pixels (light receiving elements), and the charges generated in each light receiving element are temporarily stored in the capacitance between the wirings in specific block units using the thin film transistor switch element (TFT). There is a TFT drive type image sensor that sequentially reads out as an electric signal in time series at a speed of several hundred KHZ to several MHZ. Since this TFT drive type image sensor can read by a single drive IC by the operation of the TFT, the number of drive ICs that drive the image sensor is reduced.

The TFT drive type image sensor, for example, as shown in the equivalent circuit diagram of FIG. 10, corresponds to a line-shaped light-receiving element array 51 having substantially the same length as the document width and 1: 1 to each light-receiving element 51 ″. A plurality of thin film transistors Ti, j (i = 1 to N, j = 1 to
n) and a matrix-shaped multilayer wiring 53.

The light receiving element array 51 is divided into N blocks of light receiving element groups, and the n light receiving elements 51 ″ forming one light receiving element group include photodiodes Pi, j (i = 1 to N, j = 1 to
It can be represented equivalently by n). Each light receiving element 51 ″
Are respectively connected to the drain electrodes of the thin film transistors Ti, j. The source electrodes of the thin film transistors Ti, j are connected to the common signal lines 54 (n lines) for each light receiving element group via the multilayer wirings 53 connected in a matrix, and the common signal lines 54 are connected to the driving IC 55. It is connected to the.

The gate electrode of each thin film transistor Ti, j is connected to a gate pulse generation circuit 56 so as to be conductive in each block. The photocharges generated by each photodetector 51 ″ are accumulated for a certain period of time in the parasitic capacitance of the photodetector and the overlap capacitance between the drain and gate of the thin film transistor, and then the thin film transistor Ti, j is used as a charge transfer switch for each block. Are sequentially transferred to and accumulated in the wiring capacitance Ci (i = 1 to n) of the multilayer wiring 53.

That is, from the gate pulse generation circuit 56 to the gate signal line Gi
Gate pulse φG1 transmitted via (i = 1 to n)
Turns on the thin film transistors T1,1 to T1, n in the first block, and the charges generated in each light receiving element 51 ″ in the first block are transferred and accumulated in each wiring capacitance Ci. Then, each wiring capacitance Ci The electric potential of each common signal line 54 changes due to the electric charge accumulated in the analog switch SW in the driving IC 55.
i (i = 1 to n) is sequentially turned on and extracted to the output line 57 in time series.

Then, similarly, by the gate pulses φG2 to φGn, the thin film transistors T2,1 to T2, n of the second to Nth blocks to TN, 1 to
By turning on up to TN, n, the charges on the light receiving element side are transferred for each block, and by sequentially reading, an image signal of one line in the main scanning direction of the original is obtained, and an original feeding means (not shown) such as a roller. ), The original is moved and the above operation is repeated to obtain the image signal of the entire original (see Japanese Patent Laid-Open No. 63-9358).

As for the structure of the above-mentioned matrix-shaped multilayer wiring 53, as shown in a plan explanatory view thereof in FIG. 11 and a sectional explanatory view thereof in FIG. 12, the multilayer wiring 53 includes a lower signal line 31, an insulating layer 33 on a substrate 21. The upper layer signal line 32 is sequentially formed. The lower layer signal line 31 and the upper layer signal line 32 are arranged so as to be orthogonal to each other, and a contact hole 34 is provided to connect the upper and lower signal lines to each other.
Is provided.

(Problems to be Solved by the Invention) However, in the configuration of the image sensor as described above, the multilayer wiring portions are in a matrix shape, and the signal lines in the upper and lower layers are shown in the cross-sectional explanatory view of the multilayer wiring in FIG. As described above, since they intersect through the insulating layer 33, a coupling capacitance (coupling capacitance) exists at the intersection of the lower layer signal line 31 and the upper layer signal line 32, and as a result, at the intersection of the signal lines, The problem is that the output from one signal line is affected by the potential difference from the output from the other signal line, causing crosstalk, which makes it impossible to read accurate charges and deteriorates the gradation reproducibility of the image sensor. was there.

Therefore, a light receiving element array having a plurality of light receiving elements as one block, a plurality of switching elements for transferring charges generated in the light receiving elements for each block, and a driving IC for outputting the charges as an image signal In the image sensor having, the switching element in the block and the switching element in the adjacent block are connected by wiring in the order of decreasing distance, and the switching elements in the block to the switching elements in both adjacent blocks are connected. The wirings are connected so as to be located on opposite sides with respect to the lengthwise direction of the light-receiving element array, and the wirings are arranged in ascending order of the light-receiving element array in ascending order of length of the connected wirings. Image sensors are being considered.

In this image sensor, the wiring structure is conventionally provided only on one side of the light receiving element array with respect to the main scanning direction, but the wiring structure is provided on both sides of the light receiving element array. The wiring is arranged alternately in the main scanning direction for each adjacent block, and each switching element connected to each light receiving element in the block and each switching element connected to each light receiving element in the adjacent block The wirings between and are connected in the order in which the distance between the switching element in the block and the switching element in the adjacent block is shorter, and the shorter wiring is connected to the light receiving element array side in order. Therefore, the signal lines do not intersect with each other, so that the wirings do not affect each other, and the electric charge accumulated in the wiring capacitance is positive. It is those that can be read in.

However, with the above-described image sensor configuration, the wiring structure is such that the light receiving element array is sewn, that is, the wiring must pass between the light receiving element and the adjacent light receiving element. In this case, if the wiring layer that passes between the light receiving elements is formed of the same layer as the conductive layer that constitutes the light receiving elements, the wiring layer must be sufficiently spaced between the light receiving element and the adjacent light receiving element. Cannot be provided. For that purpose, the size of the light receiving element of the light receiving element is left as it is, or the space between the light receiving element and the adjacent light receiving element is widened, or the size of the light receiving section of the light receiving element is reduced to reduce the size of the light receiving element. It is conceivable to widen the space between adjacent light receiving elements. In any case, there is a problem that the resolution of the image sensor is reduced and the performance of the image sensor is reduced.

If the wiring layer that passes between the light receiving elements is formed of the same layer as the conductive layer that constitutes the light receiving element, the conductive layer of the light receiving element is too close to the wiring layer of the light receiving element. There is also a problem that a coupling capacitance is generated between the wiring portion and the wiring portion, and the charge accumulated in the wiring capacitance cannot be accurately read.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image sensor that does not reduce the resolution and that can accurately output charges from wirings.

(Means for Solving the Problem) The invention according to claim 1 for solving the problems of the above-mentioned conventional example is a light-receiving element array having a plurality of blocks, each of which has a plurality of light-receiving elements having upper and lower electrode layers. A plurality of switching elements that are connected to the plurality of light receiving elements that transfer the charge generated in the light receiving elements for each block, and a plurality of wirings that are connected to the plurality of switching elements that output the charges as an image signal, In the image sensor having the above-mentioned, the plurality of wirings are respectively passed between the light receiving elements in the light receiving element array and the adjacent light receiving elements, and the wiring portion to be passed is a layer above the upper and lower electrode layers forming the light receiving elements. It is characterized in that it is formed by using the metal layer of.

The invention according to claim 2 for solving the problem of the above-mentioned conventional example provides a light receiving element array having a plurality of blocks with a plurality of light receiving elements having upper and lower electrode layers as one block, and an electric charge generated in the light receiving element. In an image sensor having a plurality of switching elements that are connected to the plurality of light receiving elements that are transferred for each block, and a plurality of wirings that are respectively connected to the plurality of switching elements that output the charges as image signals, Wirings are respectively passed between the light receiving elements in the light receiving element array and adjacent light receiving elements, and the wiring portion to be passed is formed by using a metal layer lower than the upper and lower electrode layers forming the light receiving elements. Is characterized by.

(Operation) According to the first aspect of the invention, the metal layer above the upper and lower electrode layers forming the light receiving element is used to form the wiring that passes between the light receiving element and the adjacent light receiving element. Therefore, the distance between the light receiving element and the adjacent light receiving element is not widened, and therefore the resolution of the image sensor is not lowered and the performance of the image sensor is not lowered, and the conductive layer and the wiring portion of the light receiving element are not reduced. The generation of the coupling capacitance between and becomes small, the electric charge accumulated in the wiring capacitance can be read out accurately, and the manufacturing can be performed without significantly changing the conventional manufacturing process.

According to the second aspect of the invention, since the metal layer below the upper and lower electrode layers forming the light receiving element is used to form the wiring for passing between the light receiving element and the adjacent light receiving element, The distance between the light receiving element and the adjacent light receiving element is not widened, so that the resolution of the image sensor is not lowered and the performance of the image sensor is not lowered, and between the conductive layer of the light receiving element and the wiring portion. The generation of coupling capacitance is reduced, the charges accumulated in the wiring capacitance can be accurately read out, and the manufacturing can be performed without significantly changing the conventional manufacturing process.

(Example) An example of the present invention will be described with reference to the drawings.

FIG. 1 is an equivalent circuit diagram of an image sensor according to an embodiment of the present invention, and FIG. 2 (a) shows a light receiving element, a charge transfer unit, and a wiring structure of the image sensor according to an embodiment of the present invention. Part of the plan explanatory view and FIG. 2 (b) are cross-sectional explanatory views of the portion AA ′ in FIG. 2 (a).

In the image sensor, n sandwich type light receiving elements (photodiodes P) 11 ″ arranged in parallel on an insulating substrate such as glass are used as one block, and a light receiving element array 11 having N blocks is provided. (P1,1 to PN, n) and each light receiving element
Thin film transistors T1,1 to TN, n connected to 11 ″ respectively
Charge transfer unit 12 and the charge transfer unit 12 in the adjacent block
Wiring group 13 for connecting each other and wiring group 13 from charge transfer unit 12
N common signal lines 14 corresponding to each light receiving element group in the block, and a driving IC 15 connected to the common signal line 14,
The potentials of the n common signal lines 14 in the driving IC 15 are output lines 17
(COM) Analog switch S for time-series extraction
It is composed of W1 to SWn.

As shown in FIGS. 2 and 3, the light receiving element 11 ″ includes an insulating layer 26, an a-Si: H layer, and an n ⁺ a-Si: H layer formed on a substrate 21 such as glass, and the like. , A strip-shaped metal electrode 22 made of chromium (Cr2) or the like serving as a common electrode under the light receiving element 11 ″, and hydrogenated amorphous silicon (a-Si: H) formed separately for each light receiving element 11 ″ (bit by bit). ) Photoconductive layer 23 consisting of
Similarly, an upper transparent electrode 24 made of indium tin oxide (ITO), which is similarly divided, is sequentially laminated to form a sandwich type.

Here, the lower metal electrode 22 is formed in a strip shape in the main scanning direction, the photoconductive layer 23 is discretely formed on the metal electrode 22, and the upper transparent electrode 24 is also discretely formed. The photoconductive layer is formed by dividing it into individual electrodes.
A portion sandwiching 23 between the metal electrode 22 and the transparent electrode 24 constitutes each light receiving element 11 ″, and the collection thereof forms the light receiving element array 11.

Then, a constant voltage VB is applied to the metal electrode 22. Further, one end of the wiring 30a made of aluminum or the like is connected to one end of the transparent electrode 24 which is discretely formed, and the other end of the wiring 30a is connected to the drain electrode 41 of the thin film transistor TN, n of the charge transfer section 12. There is.

Further, in the light receiving element 11 ″, it is also possible to use CdSe (cadmium selenium) or the like as the photoconductive layer instead of hydrogenated amorphous silicon. In this way, the photoconductive layer 23 and the transparent electrode 24 are individualized. This is because when the a-Si: H photoconductive layer 23 is a common layer, the photoelectric conversion action that occurs in a specific light receiving element 11 ″ may cause interference with the adjacent light receiving element 11 ″. This is to reduce interference.

In addition, the thin film transistor Ti, j forming the charge transfer unit 12
As shown in FIGS. 2A and 4, (i = 1 to N, j = 1 to n) is a chromium layer (Cr1) as the gate electrode 25 on the substrate 21 and a gate insulating film. A silicon nitride film as the insulating layer 26, a hydrogenated amorphous silicon (a-Si: H) layer as the semiconductor active layer 27, a silicon nitride film as the top insulating layer 29 provided so as to face the gate electrode 25,
An n ⁺ hydrogenated amorphous silicon (n ⁺ a-Si: H) layer as the ohmic contact layer 28, a drain electrode 41 and a chromium layer (Cr2) as the source electrode 42 are sequentially laminated, and an insulating layer such as polyimide is formed thereon. Aluminum layer wiring through
Inverted staggered transistor 30 is connected.

Here, the ohmic contact layer 28 is the drain electrode 41.
The portion 28a that contacts the layer and the portion 28b that contacts the source electrode 42
Layer and chrome layer (Cr2) formed on it separately
Also, the drain electrode 41 and the source electrode 42 are separately formed. The drain electrode 41 is connected to the aluminum wiring 30a from the transparent electrode 24 of the light receiving element 11 ″, and the source electrode 42 is connected to the aluminum wiring 30b of the wiring group 13.

Further, the configuration of the wiring group 13 will be described in detail with reference to FIGS. 1 to 5.

For example, as shown in FIG. 1, the wiring group 13 has a common signal line 14 (signal lines 1 ′ to n ′) derived from a driving IC located on the lower side of the first block. '~ N'
On the way, the source electrodes 42 of the thin film transistors T1,1 to T1, n of the first block are connected via the aluminum wiring 30b, respectively, and the light receiving element and the thin film transistor of FIG. As shown in signal line 35
Is provided on the polyimide or the like covering the light receiving element 11 ″,
The signal lines 1'-n 'extend in the second block direction above the light-receiving element array so as to pass between the light-receiving element 11 "and the adjacent light-receiving element 11". And the like, and is connected to the source electrodes 42 of the thin film transistors T2, n to T2,1 of the second block on the way.

Specifically, the signal line 1'is connected to the source electrode 42 of the first block thin film transistor T1,1 and is connected to the source electrode 42 of the second block thin film transistor T2, n, and to the signal line 2 '. Are connected to the source electrodes 42 of the thin film transistors T1 and T2 of the first block and are connected to the source electrodes 42 of the thin film transistors T2 and n−1 of the second block, so that the source electrodes 42 of the thin film transistors T are arranged in the order of increasing distance in the adjacent blocks. They are connected to each other via a signal line, and the thin film transistor T of the first block is connected to the signal line n '.
The source electrodes 42 of 1, n are connected, and the source electrodes 42 of the thin film transistors T2,1 of the second block are connected. Conversely, in the adjacent blocks, the source electrodes 42 of the thin film transistors T, which are close to each other, are sequentially connected by the signal line.

In this case, as shown in FIG. 5, the wirings of the connected signal lines are arranged closer to the light receiving element array 11 along the light receiving element array 11 (in the main scanning direction) in ascending order of distance. Place it on the upper side. That is, specifically explaining between the first block and the second block, the shortest signal line n ′ is arranged closest to the light receiving element array 11,
Next, the signal line n'-1 is arranged second closest to the light receiving element array 11, and thus the longest signal line 1'is arranged in the wiring group.
It will be placed on the outermost side of the 13. With the above configuration, signal lines do not intersect between the first block and the second block, and there is no concern about crosstalk.

Next, a specific configuration of the wiring group 13 between the second block and the third block will be described. The source electrodes 42 of the thin film transistors T2,1 to T2, n of the second block and the source electrodes 42 of the thin film transistors T3, n to T3,1 of the third block are arranged below the light receiving element array. Signal line n '
.About.1 'respectively. In particular,
The source electrode 42 of the thin film transistor T2,1 of the second block is connected to the signal line n ', the source electrode 42 of the thin film transistor T3, n of the third block is also connected, and the second block is connected to the signal line n'-1. Source electrode 42 of thin film transistor T2,2
, And the source electrode 42 of the thin film transistor T3, n−1 of the third block is also connected.

When the source electrodes 42 of the thin film transistors T are connected to each other by signal lines in the order of increasing distance in the adjacent blocks,
That is, the source electrode 42 of the thin film transistor T2, n of the second block and the source electrode 42 of the thin film transistor T3,1 of the third block are connected by the signal line 1 '.
Conversely speaking, the source electrodes 42 of the thin film transistors T having a short distance in the adjacent blocks are sequentially connected by the signal line.

Regarding the wiring group 13 between the second block and the third block, as shown in FIG. 5, the wiring is arranged along the light receiving element array 11 in the ascending order of distance (in the main scanning direction). The light-receiving element array 11 should be placed close to 11 and below the light-receiving element array 11. That is, in the wiring between the second block and the third block, the closest signal line 1'is arranged closest to the light receiving element array 11, and then the signal line 2'is placed.
The second longest signal line n'is arranged in this way, and thus the longest signal line n'is arranged at the outermost side in the wiring group 13. With the above configuration, signal lines do not intersect between the second block and the third block, and there is no concern about crosstalk.

FIG. 5 is a schematic view showing the whole state. When connecting from an odd block to an even block with a wiring group 13, the wiring group 13 is arranged above the light-receiving element array 11 and from the even block to the odd block. When connecting with, the light receiving element array
It is placed under 11. Therefore, the wiring group 13 from the odd-numbered block to the even-numbered block and the wiring group 13 from the even-numbered block to the odd-numbered block do not intersect, and there is no concern about crosstalk.

In the present embodiment, assuming that the Nth block is an even block, the driving IC 15b is provided below the Nth block of the even blocks, similarly to the case where the driving IC 15a is provided below the first block. . Here, the analog switches SW1 to SWn in the driving IC 15a are connected in the order of the signal lines 1'to n '. Then, the thin film transistor T of the Nth block
The signal lines to which the source electrodes 42 of N, 1 to TN, n are respectively connected are connected to the driving IC 15b, and the analog switches SW1 to SWn in the driving IC 15b are connected to the signal lines continuing from the driving IC 15a. The signal lines n'to 1'are connected in this order.

The n common signal lines 14 connected to the analog switches SW1 to SWn in the driving ICs 15a and 15b are extracted from the wiring group 13 and co-communicate by the charges accumulated in the wirings of the signal lines of the wiring group 13. The potential of the signal line 14 changes, and this potential value is extracted to the output line 17 (COM1, 2) by the operation of the analog switch. Here, in the driving ICs 15a and 15b, the potential value of the signal line is read out in the order of the analog switches SW1 to SWn.

Next, a method of manufacturing the image sensor of this embodiment will be described. Chromium (Cr1) is deposited on the substrate 21 such as glass by the DC sputtering method, and the gate electrode 25 of the thin film transistor (TFT) of the charge transfer unit 12 is formed. A pattern is formed by photolithography, and an insulating layer 26 to be a gate insulating layer of a TFT, a semiconductor active layer 27 of an a-Si: H layer and a top insulating layer 29 are formed on the pattern so as to correspond to the gate electrode 25. A pattern of the top insulating layer 29 is formed.

An n ⁺ a-Si: H layer of the ohmic contact layer 28 is deposited thereon, and further, a drain electrode 41 and a source electrode 42 of the TFT, and a chromium layer (Cr2) to be the metal electrode 22 of the light receiving element portion is deposited thereon. .

Then, the photoconductive layer 23 in the light receiving element portion, the transparent electrode 24 is deposited, the transparent electrode 24 and the photoconductive layer 23 are individualized by photolithographic etching, and then the metal electrode 22, the drain electrode 41 and the source electrode 42 are photolithographically etched. Pattern Cr2, T
When the FT part is etched with a mixed gas of HF ₄ and O ₂ ,
And the portion without the insulating layer is etched, and the semiconductor active layer 27 of the a-Si: H layer and the ohmic contact layer 2 of the n ⁺ a-Si: H layer 2
8 patterns are formed.

An insulating layer made of polyimide is formed thereon, and contact holes are provided at necessary portions, and a wiring group 13 made of aluminum is formed.

In the present embodiment, the wiring group 13 is formed of aluminum on the insulating layer of polyimide because it is the uppermost layer of the metal layers, so that it is possible to increase the film thickness and reduce the sheet resistance. This is because such a long wiring is advantageous for suppressing the resistance value.

Next, a driving method of the image sensor according to the embodiment of the present invention will be described.

When a document (not shown) arranged on the light-receiving element array 11 is irradiated with light from a light source (not shown), the reflected light irradiates the light-receiving element (photodiode PD), and the density of the document is changed. A corresponding charge is generated and accumulated in the parasitic capacitance of the light receiving element 11 ″. The thin film transistor T is turned on based on the gate pulse φG transmitted from the gate pulse generation circuit (not shown) via the gate signal line Gn. In this state, the photodiode PD and the common signal line 14 side are connected and the light receiving element 1
The charge accumulated in the 1 ″ parasitic capacitance or the like is transferred and accumulated in the wiring capacitance of the wiring group 13. Specifically, a case where the charges are generated in the photodiodes P1,1 to P1, n of the first block will be described. When the gate pulse φG1 is applied from the gate pulse generation circuit, the thin film transistors T1,1 to T1, n are turned on, and the charges generated in the photodiodes P1,1 to P1, n are evenly distributed across the wiring group 13. The charges of the photodiodes P1,1 are distributed to the wiring capacitance of the entire signal line 1 ', the charges of the photodiodes P1,2 are distributed to the wiring capacitance of the entire signal line 2', and the photodiodes P1 are distributed. The charges of n are transferred to and accumulated in the wiring capacitance of the entire signal line n '.

Next, as shown in FIG. 1 and FIG. 5, since two driving ICs 15a and 15b are provided in this embodiment, two driving ICs are provided.
The operation relationship between 15a and 15b will be described. Two driving ICs 15
The a and 15b are respectively connected as shown in FIG. 6, and the driving IC 15a is configured to read the start signal φs for starting the reading of the potential generated in the wiring capacitance from the outside. Signal reading terminal ST1
Read in, the potential of the wiring capacitance related to the first block is read into the driving IC 15a and the switch SW in the driving IC 15a is read.
By sequentially turning on 1 to SWn, the charges generated in the photodiodes P1,1 to P1, n of the first block and accumulated in the wiring capacitances of the signal lines 1'to n'are read out from COM1.

When the reading of the first block is completed, the signal is for driving
The driving IC 15b, which is transmitted from the signal generation terminal CR1 in the IC 15a to the signal reading terminals ST2 and CS2 in the driving IC 15b and receives the signal, sequentially turns on the switches SW1 to SWn in the driving IC 15b to generate the second block. Photodiodes P2, P2,
The charges generated in 2 and accumulated in the wiring capacitances of the signal lines 1'-n 'are read out from COM2. Terminal ST2 and terminal CS2
Is internally connected to the OR circuit, so when a signal is input to one of them, the driving IC 15b becomes operable and operates to read the electric charge of one block (here, the second block). To do.

Further, when the reading of the second block is completed, the signal is transmitted from the signal generation terminal CR2 in the driving IC 15b to the signal reading terminal CS1 in the driving IC 15a, and the driving IC 15a that receives the signal is in the third block. Charge on com 1
More will be read. When a signal is transmitted to the terminal CS1 as in the case of the terminal CS2, the driving IC 15a becomes in a special state and operates to read the electric charge of one block (here, the third block).

In this way, the charges from the first block to the Nth block of the light receiving element array 11 are transferred to the COM1 and the driving I of the driving IC 15a.
It is supposed to read from CON2 of Cb alternately, and the terminal CR
When a signal is generated from 1, the output from COM1 is turned off until a signal is input to terminal CS1. Similarly, when a signal is generated from terminal CS2, the output from COM2 is turned off until a signal is input to terminal CS2. Become.

Clock pulses φCK are sent from the outside to the driving ICs 15a and 15b at regular intervals, and the charges of the Nth block are read by the alternating output operation from the COM1 and COM2 to drive the driving ICs. The operation ends, and the reading of one line of the document ends.

Then, by connecting COM1 and COM2, the image signal alternately output from COM1 and COM2 to COM is from the first block to the Nth block.
It becomes the entire image signal up to the block.

In this way, the driving IC 15a reads out the charges related to the odd-numbered blocks and the driving IC 15b reads out the charges related to the even-numbered blocks because the order (direction) of reading the charges in the odd-numbered even-numbered blocks shown in FIG. 7 is opposite. Because. That is, the driving IC 15a is connected to the signal line 1 '
Since the charges accumulated in ~ n 'are read by the analog switches SW1 to SWn in the order of the signal lines 1'to n'and output from COM1, the charges of the first block to the Nth block are read out. If so, in the odd-numbered blocks, the first to n-th charges of the photodiode PD are accumulated in the signal lines 1'-n ', so that the signal lines 1'-n' are read out in this order. , Photodiode PD in even block
Since the 1st to nth charges are accumulated in the signal lines n'to 1'and read out in the order of the signal lines n'to 1 ', the signal reading order is reversed in the even block.
Therefore, in the driving IC 15a, only the charges in the odd blocks are selectively read out.

On the contrary, the drive IC 15b normally reads out the charges in the even blocks. That is, in the even-numbered blocks, the 1st to nth charges of the photodiode PD are accumulated in the signal lines n'to 1 ', but in the driving IC 15b, the charges of the signal lines n'to 1'are read in this order, and then in COM2. Since it is designed to be output, the charges generated at the first to nth photodiodes PD in the even-numbered blocks are output to COM2 as an image signal. On the contrary, in the odd-numbered blocks, the charges generated at the nth to 1st of the photodiode PD are output as an image signal. Therefore, the driving IC 15b selectively reads only the charges in the even blocks.

As described above, the driving ICs 15a and 15b selectively output odd-numbered and even-numbered blocks from COM1 and COM2, respectively, and by alternately combining them and outputting from COM, as shown in COM in FIG. The image signals of the block to the Nth block can be sequentially output.

According to the present embodiment, the plurality of light receiving elements 11 ″ are set as one block, and the wiring is alternately connected to adjacent blocks in the main scanning direction.
The wiring between the source electrode 42 of the thin film transistor connected to 11 ″ and the source electrode 42 of the thin film transistor connected to each light receiving element 11 ″ in the block adjacent to the thin film transistor in the block adjacent to the source electrode 42 of the thin film transistor in the block The thin film transistors are connected in the order of decreasing distance from the source electrode 42, and the shorter wiring is connected to the light receiving element array 11
Since the signal lines do not intersect with each other, the wiring groups 13 do not affect each other, and the charges accumulated in the wiring capacitance of the wiring groups 13 can be accurately read because they are arranged in order on the side. And prevent the occurrence of crosstalk,
This has the effect of improving the gradation reproducibility of the image sensor.

Further, in this embodiment, two driving ICs are provided so that one driving IC 15a reads out the charge generated in the odd block and the other driving IC 15b reads out the charge generated in the even block. Since the outputs from both the driving ICs are combined to form the image signal, there is an effect that the output processing is easier than when the image signal is output by one driving IC.

Also, as shown in the equivalent circuit of FIG.
It is also possible to output and process the image signal. In this case, when an image signal is output by one driving IC as described above, the order (direction) of reading charges in the odd-numbered block and the even-numbered block becomes opposite, so that the external circuit memory (not shown) It is necessary to change the output order of the image signals and output them in time series. According to this embodiment, the number of driving ICs is reduced from two to one, so that the cost can be reduced, the space of the sensor portion can be reduced, and the yield can be improved by reducing the number of wire bondings.

Further, in addition to the above configuration, if the ground line is wired in parallel between the respective signal lines, it is possible to eliminate the influence of crosstalk between the parallel signal lines, and increase the wiring capacity of the signal lines. Is possible.

Further, according to the present embodiment, since the aluminum layer above the transparent electrode 24 above the light receiving element 11 ″ is used to form the wiring for passing between the light receiving element and the adjacent light receiving element, And the adjacent light receiving element is not widened, so that the resolution of the image sensor is not lowered and the performance is not lowered, and the coupling capacitance between the electrode of the light receiving element and the wiring portion 30b is not increased. Is less likely to occur, the charges accumulated in the wiring capacitance of the wiring group 13 can be read out accurately, and the manufacturing can be performed without significantly changing the conventional manufacturing process.
As 13 is made of aluminum, wiring group is made of chrome
Since the resistance value is lower than that of forming 13 and the wiring layer of the wiring group 13 is the uppermost layer of the metal layers, it is possible to increase the film thickness and reduce the sheet resistance, especially when the wiring is long. Has the effect of suppressing the resistance value.

As another embodiment, as shown in FIG. 9 (a) and a plan explanatory view of FIG. 9 (a) and FIG. 9 (b) which is a cross-sectional explanatory view of a portion BB ′ of FIG. 9 (a), a substrate 21 is provided. Chromium (Cr1), which will be the gate electrode 25 of the TFT, is formed on the upper surface of the wiring group 13. At the same time, the wiring portion 30c of the wiring group 13 for passing between the light receiving element and the adjacent light receiving element is made of chromium ( The wiring group 13 other than the above may be formed by providing a contact portion 36 on the insulating layer 26 and forming a wiring layer using aluminum on the insulating layer such as polyimide. The manufacturing method of this wiring group 13 is
When Cr1 is deposited on the substrate 21 and the pattern of the gate electrode 25 of the TFT is formed, the wiring portion 30c that passes between the light receiving element and the adjacent light receiving element is also patterned by photolithography to form the light receiving element. After forming 11 ″ and the charge transfer portion 12, the contact portion 36 is provided, and the other wiring layer 30 is formed of aluminum on the insulating layer such as polyimide.

According to this alternative embodiment, the chromium layer (Cr1) lower than the metal electrode 22 above the light receiving element 11 ″ is used to form the wiring for passing between the light receiving element and the adjacent light receiving element. , Without increasing the distance between the light receiving element and the adjacent light receiving element, so that the resolution of the image sensor is not lowered and the performance is not lowered, and between the electrode of the light receiving element and the wiring portion 30c. The generation of coupling capacitance is reduced, the electric charge accumulated in the wiring capacitance of the wiring group 13 can be accurately read, and further, there is an effect that it can be manufactured without significantly changing the conventional manufacturing process. Since the wiring passes under the metal electrode 22 of the element, the wiring width of the wiring portion 30c can be freely set.
Since a constant bias voltage is applied to 2, the metal electrode 22 has an effect of shielding the influence (crosstalk) of the voltage change of the adjacent light receiving element on the wiring portion 30c passing between the light receiving elements. .

(Effect of the invention) According to the invention described in claim 1, the metal layer above the upper and lower electrode layers forming the light receiving element is used to configure the wiring for passing between the light receiving element and the adjacent light receiving element. Therefore, the distance between the light receiving element and the adjacent light receiving element is not widened, so that the resolution of the image sensor is not lowered and the performance of the image sensor is not lowered. The generation of the coupling capacitance with the wiring portion is reduced, the electric charge accumulated in the wiring capacitance can be read out accurately, and the manufacturing process can be performed without significantly changing the conventional manufacturing process.

According to the second aspect of the invention, since the metal layer below the upper and lower electrode layers forming the light receiving element is used to form the wiring for passing between the light receiving element and the adjacent light receiving element, The distance between the light receiving element and the adjacent light receiving element is not widened, so that the resolution of the image sensor is not lowered and the performance of the image sensor is not lowered, and between the conductive layer of the light receiving element and the wiring portion. The generation of the coupling capacitance is reduced, the charges accumulated in the wiring capacitance can be read out accurately, and the manufacturing can be performed without significantly changing the conventional manufacturing process.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of an image sensor according to an embodiment of the present invention, and FIG. 2A is a part of a light receiving element, a charge transfer unit and a wiring group of the image sensor according to the embodiment of the present invention. FIG. 2 (b) is a cross-sectional explanatory view of the AA ′ portion of FIG. 2 (a), FIG. 3 is a cross-sectional explanatory view of the light receiving element portion, and FIG.
FIG. 5 is a cross-sectional explanatory view of the charge transfer portion, FIG. 5 is a schematic view of a wiring group of the image sensor according to one embodiment of the present invention, and FIG. 6 is a driving IC of the image sensor according to one embodiment of the present invention. Connection configuration diagram, FIG. 7 is an output explanatory diagram from the driving IC of FIG. 6,
FIG. 8 is an equivalent circuit diagram of an image sensor according to another embodiment of the present invention, and FIG. 9 (a) is one example of a light receiving element, a charge transfer section and a wiring group of an image sensor according to another embodiment of the present invention. FIG. 9 (b) is a cross-sectional explanatory view of the BB ′ portion of FIG. 9 (a), FIG. 10 is an equivalent circuit diagram of a conventional image sensor, and FIG. 11 is FIG. FIG. 12 is a plan view of the multilayer wiring structure in FIG. 11, and FIG. 12 is a cross-sectional view of CC ′ in FIG. 11. 11, 51 …… Photosensor array 12, 52 …… Charge transfer unit 13, …… Wiring group 14, 54 …… Common signal line 15, 55 …… Driving IC 17, 57 …… Output line 21 …… Substrate 22 …… Metal electrode 23 …… Photoconductive layer 24 …… Transparent electrode 25 …… Gate electrode 26 …… Insulating layer 27 …… Semiconductor active layer 28 …… Ohmic contact layer 29 …… Top insulating layer 30 …… Wiring layer 31 …… … Lower layer signal line 32 …… Upper layer signal line 33 …… Insulating layer 34 …… Contact hole 35 …… Contact part 41 …… Drain electrode 42 …… Source electrode 53 …… Multilayer wiring

Claims (2)

[Claims] 1. A plurality of light receiving elements having upper and lower electrode layers
A light-receiving element array having a plurality of blocks as blocks, a plurality of switching elements each connected to the plurality of light-receiving elements for transferring the charge generated in the light-receiving element for each block, and a plurality of the plurality of switching elements for outputting the charges as an image signal. In an image sensor having a plurality of wirings each connected to a switching element, the plurality of wirings are respectively passed between a light receiving element in the light receiving element array and an adjacent light receiving element, and a wiring portion to be passed is the light receiving element. An image sensor formed by using a metal layer above an upper and lower electrode layers forming an element. 2. A plurality of light-receiving elements having upper and lower electrode layers
A light-receiving element array having a plurality of blocks as blocks, a plurality of switching elements each connected to the plurality of light-receiving elements for transferring the charge generated in the light-receiving element for each block, and a plurality of the plurality of switching elements for outputting the charges as an image signal. In an image sensor having a plurality of wirings each connected to a switching element, the plurality of wirings are respectively passed between a light receiving element in the light receiving element array and an adjacent light receiving element, and a wiring portion to be passed is the light receiving element. An image sensor formed by using a metal layer lower than upper and lower electrode layers forming an element.