JPH0750786B2 - Thin film transistor - Google Patents

Description

The present invention relates to a MOS type thin film transistor (hereinafter abbreviated as TFT) formed on an insulating substrate or an insulating film.

[Conventional technology]

Conventionally, the planar pattern shape of a TFT has been such that one TFT normally has only one channel region, like a MOSFET formed on a silicon substrate. This is because the current-voltage characteristics of TFTs formed on the same substrate are usually inversely proportional to or proportional to the length and width of the channel region. For example, in order to increase the ON current of the TFT, the width of the channel region may be increased, or the channel length may be further shortened. If there is no limitation in the pattern layout, one TFT is 1 It was formed of two channel areas.

On the other hand, since TFTs usually use amorphous silicon or polysilicon as semiconductors in the channel section, they have lower mobility and therefore slower speed compared to MOSFETs formed on single crystal silicon substrates, and a sufficient ON current. I can't take it. In order to increase the ON current, the channel width may be increased as described above, but it is not so effective in terms of speed. This is because if the channel width is increased, the area of the gate electrode is increased in proportion thereto, and accordingly the gate capacitance formed by the gate electrode is increased.

[Problems to be Solved by the Present Invention]

In the conventional TFT semiconductor device, in order to manufacture a circuit having a higher speed, it is necessary to change the manufacturing conditions of the semiconductor device such as thinning the gate insulating film or increasing the mobility. In other words, TFT
It is extremely difficult to form a higher-speed circuit by devising the TFT pattern once the manufacturing conditions of are decided.

In addition, as described above, the semiconductor substrate forming the TFT is polysilicon, amorphous silicon, or the like, and the speed is essentially slow due to the low carrier mobility. Although there are some TFT manufacturing techniques for speed-up, the object of the present invention is to propose a speed-up means by devising a pattern.

[Means for solving problems]

The thin film transistor of the present invention is a MOS type thin film transistor formed on an insulating material and having a plurality of channel parts with respect to one gate electrode, wherein each channel width of the channel parts is 4 μm or less, and Both end portions in the width direction of the channel portion are characterized by forming sloped portions.

[Action]

In the TFT according to the present invention, compared with the conventional TFT, the ON current increases when the transistor size is similar. Further, in the integrated circuit device composed of the TFT according to the present invention,
The operating speed is higher than that of an integrated circuit device composed of a conventional TFT.

〔Example〕

FIG. 1 is a basic pattern of a conventional TFT.
1 is a semiconductor layer such as polysilicon, 2 is a gate electrode in which polysilicon is heavily doped with phosphorus, 3, 3'is source and drain regions, 4, 4 ', 5 are source / drain and gate electrodes A contact hole is shown. w ₀ ,
₀ indicates the channel width and the channel length, respectively.

FIG. 2 shows an embodiment of the TFT pattern according to the present invention. 11 to 15 in FIG. 2 correspond to 1 to 5 in FIG. 1, respectively. The channel in FIG. 2 is composed of two 11, 11 ', and the two channels are arranged in parallel,
The source 13 and the drain 13 'are connected in parallel and share the gate electrode 12. The TFT channel length in Figure 2 is
The channel width is the sum of two parallel channels w ₁ + w ₂ (=
W).

In each TFT that constitutes a normal TFT integrated circuit, the channel length is made constant and the channel width is changed according to the required circuit characteristics. FIG. 3 is a conventional TF corresponding to FIG.
The cross-sectional structure of T is shown. In FIG. 3, 20 is an insulating substrate, 21 is a semiconductor layer of a channel portion, 22 is a gate insulating film,
Reference numeral 23 is a gate electrode. When the channel section 21 is finely classified, the cross section of the semiconductor layer is divided into a slope section, that is, regions 21a and 21a 'at both ends of the channel section which are tapered, and a region 21b where the semiconductor layer has a constant thickness. The taper of the semiconductor layer is, for example, when a polysilicon film is formed as the semiconductor layer, etching of polysilicon is usually performed by wet etching with a mixed acid of hydrofluoric acid and nitric acid or dry etching with Freon plasma, but these etchings are isotropic. It is formed to have.

FIG. 4 shows the relationship between the channel width and the drain current with the channel length kept constant in the conventional TFT shown in FIG. The relationship between the two is approximately proportional as a whole, but in the region where the channel width is small, there is a deviation from the proportional relationship. This deviation is a downwardly convex curve.

The cause of the deviation is the channel of the tapered portion in FIG.
This is because the current flowing through the regions 21a and 21a 'is larger than the current flowing through the channel region 21b. In a TFT on an insulating substrate, the voltage applied to the gate electrode causes the energy band of the semiconductor layer to bend, and the thinner the semiconductor layer is, the more the band bends. That is, at the same gate voltage, the channel portions 21a and 21a 'in FIG.
It is thinner than 1b, so the bending of the band becomes deeper, more carriers are induced, and a large current flows. Looking at this phenomenon in relation to the total channel current, that is, the drain current,
As the channel width becomes narrower, the ratio of the current flowing through the channel portions 21a and 21a 'in FIG. 3 becomes equal to or larger than the current flowing through the channel portion 21b. Therefore, as shown in FIG. 4, a deviation from the proportional relationship occurs.

The increase of the ON current in the present invention is positively owed to the phenomenon of the deviation. This is because, in the TFT pattern of FIG. 2 according to the present invention, two channels are arranged in parallel, so that the ratio of the channel region of the taper portion that causes the deviation increases with respect to the entire channel width. Of course, if two or more channels are arranged in parallel, the effect of the present invention becomes more remarkable.

〔The invention's effect〕

As described above, according to the configuration of the invention of the present application, (1) the ON current and the operation speed are improved with the same film quality and film thickness as the conventional transistor only by changing the arrangement in the element. There is no need to make drastic changes in film quality, new control of film quality or film thickness.

(2) Since the ON current is improved even if the total width of the channel widths arranged in parallel in one element is the same as or slightly smaller than the conventional channel width W ₀ , it is not necessary to increase the channel width, and the gate width is reduced. Since parasitic capacitance such as capacitance does not increase,
The operation speed is improved.

(3) When hydrogen plasma treatment is performed in a later step, hydrogen easily enters the central portion of the channel as compared with the conventional structure.
The ON current can be further improved.

It has a remarkable effect.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 ... A diagram showing a TFT pattern according to a conventional technique. FIG. 2 ... A diagram showing a TFT pattern according to the present invention. Fig. 3 …… TFT sectional structure diagram. FIG. 4 ... A diagram showing the relationship between the channel width and the drain current. 1,11,11 ′, 21 …… Semiconductor layer 2,12,23 …… Gate electrode 3,3 ′, 13,13 ′ …… Source and drain 4,4 ′, 5,14,14 ′, 15 …… Contact holes 21a, 21a ′, 21b …… Channel section 22 …… Gate insulation film

Claims (1)

[Claims] 1. In a MOS type thin film transistor made of a silicon semiconductor having a plurality of channel portions with respect to one gate electrode formed on an insulating material, each channel portion has a channel width of 4 μm or less. ,
A thin film transistor characterized in that both end portions in the width direction of the channel portion are formed with sloped portions, and a gate insulating film and a gate electrode are formed on the channel portion including the sloped portions.