JPH0750878B2 - Scramble processing method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a scramble processing system, and more particularly to a scramble processing system used in an orthogonal polarization digital wireless communication line provided with a cross polarization interference canceling circuit.

[Conventional technology]

In the microwave and quasi-millimeter wave band digital wireless communication lines, the bipolar-formed digital multiplexed signal transmitted from the multiplexing terminal device is first converted into a unipolar signal in the transmission signal processing device provided on the transmitting terminal side. Converted and speed converted to insert parity check bits for wireless section monitoring, additional bits such as frame synchronization signals, and scramble processing to facilitate flattening of transmission spectrum and reproduction of bit synchronization on the receiving side. After receiving it, it is sent to the modulator of the transmitter.

This scrambling process is generally performed by obtaining a modulo 2 sum of a pseudo-random code and an input signal obtained from a m-sequence (longest linear code sequence) code sequence generator using a shift register, and receiving The terminal side performs descrambling processing with the same pseudo-random code as the transmitting terminal side, and restores the original signal.

In the conventional digital wireless communication system, an interleaved frequency arrangement is used in which the carrier frequencies of two orthogonal polarizations are arranged such that the carrier frequencies of the respective polarizations are in the middle of the carrier frequencies of opposite polarizations. In order to simplify the device configuration and improve mass productivity, the same transmission signal processing device is used for each digital multiplexed signal, and therefore the same pseudo-random code is used for scrambling processing.

[Problems to be solved by the invention]

In recent years, in order to make the use of frequency bands even more effective,
Two-channel frequency allocation using orthogonal polarization has received attention,
Research and development for practical use are being actively conducted. One of them is the problem of removing cross-polarization interference that occurs between orthogonal polarizations due to rainfall or the like, and various methods have been proposed. The method proposed in Japanese Patent Laid-Open No. 55-133156 is digital. It attracts attention as a method suitable for wireless communication systems.
This method detects cross-polarization interference by calculating the correlation from the demodulated baseband signals of the two polarized waves without using the pilot signal, and the data signal transmitted in two orthogonal polarized waves is It is based on the premise that they are independent and uncorrelated. This precondition holds when the data signals are normally input to the two polarizations, and therefore the interference canceller operates normally.

However, if the same scrambling process as in the conventional method is performed, if both the V and H polarization multiplexed terminal equipment from the multiplexed terminal equipment are disconnected, or the input of the multiplexed terminal equipment is If all of them are "0", the problem occurs.
That is, as will be described in detail later, in the above case, the same code sequence is sent to both V and H polarized waves from the transmission signal processing device that performs the scrambling process, and the reception system including the interference cancellation circuit malfunctions. There is a problem.

And while such conditions occur during line operation, they are a particular problem during line tests during construction.

The object of the present invention is to eliminate the above-mentioned problems, and in any case, the same code sequence is not output in the same phase from the transmission signal processing device for both V and H polarized waves, and a reception system including an interference cancellation circuit is provided. An object of the present invention is to provide a scramble processing method in which malfunction does not occur.

[Means for solving problems]

According to the invention, two orthogonal to each other at the carrier frequency
A non-modulated signal for orthogonal polarization digital wireless communication line that transmits separate information in one polarization (V polarization and H polarization) in order to flatten the transmission spectrum and reproduce bit synchronization on the receiving side. In the scramble processing method for performing scrambling on the first baseband signal, the transmitting side scrambles the first baseband signal to be transmitted with the V polarization transmitted from the multiplexing terminal device with the first pseudo random code. A first scramble circuit for performing a process and a second scramble process by a second pseudo-random code for a second baseband signal to be transmitted in the H polarization similarly sent from the multiplexing terminal device. A second pseudo-random code connected to the second scramble circuit and one of the output of the first scramble circuit and the output of the second scramble circuit And a second self-scramble circuit or a first self-scramble circuit connected to the other of the two outputs for performing a self-scramble process by a fourth pseudo-random code. V of the first delay circuit that gives a delay equivalent to the delay time of the circuit and the two outputs of the output of the first self-scramble circuit and the output of the second self-scramble circuit or the first delay circuit
A first modulation circuit that modulates a first baseband output signal that should be transmitted by polarization and a second modulation circuit that modulates a second baseband output signal that should be transmitted by H polarization. A first demodulation circuit for demodulating the modulated signal transmitted and received by the V-polarized wave and the H-polarized wave. Of the output signal of the first demodulation circuit and the output signal of the second demodulation circuit, the reception section that includes the second demodulation circuit that demodulates the received modulated signal that has been transmitted For the output signal to which the scramble circuit is connected, the first self-descramble circuit that performs self-descramble processing with the same pseudo-random code as the first self-scramble circuit is provided, and the second self-descramble circuit is provided on the transmission side. Rumble circuit Is a second self-descramble circuit or a first self-descrambler that performs self-descramble processing with the same pseudo-random code as the second self-scramble circuit for the output signal to which the first delay circuit is connected. A scramble processing system is obtained which is configured to include a second delay circuit that gives a delay equivalent to the delay time of the circuit.

〔Example〕

 Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of a transmission signal processing device on the side of a transmitting terminal of an orthogonal polarization digital wireless communication line. In FIG. 1, 1v and 1h are code conversion circuits for converting bipolar signals 100v and 100h input from a multiplexing terminal device (not shown) into unipolar signals 101v and 101h, and 2v and 2h are unipolar signals “1”. Parity counting circuit that counts "or" 0 "to determine whether it is odd or even, 3v and 3h are speed conversion circuits that insert frame synchronization signals, parity check bits, etc. by stuffing operation, 4v and 4h are Speed converted signal 10
2v and 102h are scramble circuits for scrambling, 5v and 5h are the same code sequence generators that generate the same pseudo-random code (m-sequence linear code) 103v and 103h for scrambling. To form transmission signal processing devices 6v and 6h.

7h is one of the scrambled data signals 10
Self-scramble circuit that further scrambles 4h, 7v is the other side of the scrambled signal 1
This is a delay circuit that delays 04v by the same number of bits as 7h, and the modulator input signals 105v and 105h that are the outputs of both circuits are sent to the modulator of the transmitter (not shown) of each polarization. . The bit clock generator 8 and the frame clock generator 9 are clock generators that commonly control the transmission signal processing devices 6v and 6h for V and H polarized waves and the transmission signal processing devices for other carrier frequencies. Note that if these clock generators operate the V and H polarization systems with independent clocks, the delay circuit 7v is not necessary.

FIG. 2 shows an example of the configuration of a receiving circuit provided with an interference canceling circuit according to the correlation method proposed in Japanese Patent Laid-Open No. 55-133156, which cancels cross-polarization interference by utilizing the correlation of demodulated baseband signals. It is a block diagram. In Fig. 2, the detector 10v,
The detection outputs 106v and 106h of the V and H polarizations detected in 10h are split into two, one of which is sent to the waveform equalizers 11v and 11h that are composed of transversal filters, and the other of which is the reverse polarization. Interference cancellation circuit (composed of transversal filter) 12h, 12v. The output of the waveform equalizer 11v and the output of the interference cancellation circuit 12v are combined and added to the discrimination and judgment circuit 13v, where they are decoded and the baseband signal 1
Output 07v, output of waveform equalizer 11h and interference canceller 12h
The outputs of 1 are combined and added to the discrimination / determination circuit 13h, where they are decoded to output the baseband signal 107h. 16h is a self-descramble circuit, which descrambles the signal 107h that is self-scrambled on the transmitting side,
6v is a delay circuit that delays the baseband signal 107v by the same number of bits as 16h. Then, the output signals 108v and 108h are sent to a reception signal processing device (not shown).

The waveform equalizing correlators 15v and 15h and the interference control correlators 14v and 14h are
Baseband signals 107v and 107h of each polarization and their ± n bits (n is an integer 1, 2 ... And the upper limit is determined by the number of stages of the transversal filter. This will be explained later.) Shifted signal and discrimination judgment By obtaining the correlation with the error signals 109v and 109h from the circuits 13v and 13h, the waveform distortion and the cross polarization interference component are detected, and the waveform equalizers 11v and 11h and the interference are detected so that each error component is minimized. It is configured to control the removal circuits 12v, 12h.

That is, the waveform distortion component included in the error signal 109v of the V polarization discrimination circuit 13v is a waveform equalization correlator using the V polarization baseband signal 107v and the reference signal shifted by ± n bits.
It is detected at 15v and is equalized by controlling the waveform equalizer 11v.
On the other hand, the interference component from the H polarized wave is detected by the interference control correlator 14v by the baseband signal 107h of the H polarized wave and the reference signal shifted by ± n bits, and the interference canceling circuit 12v is detected.
Controlled to be removed. Dual-polarized baseband signal 107v
If 107h and 107h are uncorrelated, the waveform distortion component and the cross polarization interference component can be separated and detected from the error signal 109v, but 107v and 107h have the same code sequence and almost the same phase ( Within 2n bits shift), since the waveform equalization correlator 15v and the interference control correlator 14v have the same reference signal, it becomes impossible to detect the waveform distortion component and the cross polarization component separately and the The operation stops.

In FIG. 1, self-scramble circuit 7h, delay circuit 7V
Considering the case where no signal is inserted, such a state occurs when the bipolar signals 100v and 100h are both disconnected. At this time, input of scramble circuit 4v, 4h 102v, 102h
Since both are continuous "0" or "1", the pseudo random codes 103v and 103h are output as they are from the scramble circuits 4v and 4h, and the pseudo random codes generated by the code sequence generators 5v and 5h are the same. And the converter input signals 105v and 105h are the same. Even if the bipolar signals 100v and 100h are not broken, the same state occurs if the same code sequence is input. Even in the multiplexing terminal equipment that sends out the bipolar signals 100v and 100h, the scrambling process is usually performed to facilitate the reproduction of the bit synchronization signal when there is no input signal, and all the inputs of the multiplexing terminal equipment are processed. When the line is not used, the same code sequence for scrambling may be sent. In order to prevent such a situation from occurring, as shown in Fig. 1, either V polarization or H polarization has a self-scramble function added to one or both of them.
Together with the scramble circuits 4v and 4h in the previous stage, the code sequences of V and H polarizations are uncorrelated.

FIG. 3 is a diagram showing one embodiment of the transmitting side self scramble circuit 7h and the receiving side self descramble circuit 16h. First, on the transmitting side, 20 is an n-stage shift register, 2
Reference numerals 1 and 22 denote circuits which give a sum of modulo 2 as a result, that is, an exclusive OR circuit, which outputs the exclusive OR signal 204 of the output signals 202 and 203 from the j and n stages of the shift register 20 and the transmission signal processing. Input data signal 200 (1
An exclusive OR output (corresponding to 04h), that is, a scramble output signal 201 (corresponding to 105h) is sent to a modulator (not shown) as a modulator input signal of the transmitter.

Next, on the receiving side, it is necessary to perform the reverse operation of scrambling. Therefore, 23 is an n-stage shift register having the same number of stages as 20, and 24 and 25 are exclusive OR circuits.
Of the output signals 207 and 208 from the j-th and n-th stages and the exclusive-OR output of the input data signal 206 from the cross interference elimination circuit (not shown), that is, the descramble output signal 210 (equivalent to 108h) ) Is sent to the reception signal processing device as an input signal of the reception signal processing device (not shown). Note that 205 and 211 are clock signals and must be synchronized.

When providing a self-scramble circuit and a descramble circuit for both VH polarized waves, use shift registers with different numbers of stages, or change the output signal stage from the register so that the scrambling sequence for both polarized waves is different. To do.

Although FIG. 2 shows an example in which the interference elimination circuit is provided in the base band, it may be provided in the IF band and the same applies when quadrature modulation is used.

〔The invention's effect〕

As described in detail above, according to the scramble processing method of the present invention, in the orthogonal polarization digital wireless communication line equipped with the cross polarization interference canceller by the correlation method, the input signals of both V and H polarizations are simultaneously transmitted. Even if a disconnection occurs or a signal of the same code sequence is input, there is no concern that a malfunction will occur on the receiving end station side, and there is an effect that normal operation is guaranteed.

Further, when the system of the present invention is introduced into a line which is currently used, there is no need to change the reception signal processing device, the reception signal processing device, and the cross polarization interference cancellation circuit, and it can be easily added. There is also an effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a transmission signal processing device on the transmitting terminal side of an orthogonal polarization digital wireless communication line to which the present invention is applied, and FIG. 2 is interference cancellation and waveform equalization on the receiving terminal side. FIG. 3 is a block diagram showing a circuit configuration example, and FIG. 3 is a block diagram of an embodiment of a self-scramble circuit and a self-descramble circuit. Explanation of symbols: 1v, 1h are code conversion circuits, 2v, 2h are parity counting circuits, 3v, 3h are speed conversion circuits, 4v, 4h are scramble circuits, 5
v, 5h is a code sequence generator, 6v, 6h is a transmission signal processor, 7v is a delay circuit, 7h is a self-scramble circuit, 8 is a bit clock generator, 9 is a frame clock generator, 10v, 10h are detectors, 11v and 11h are waveform equalizers, 12v and 12h are interference cancellers, 13v and 1
3h is an identification judgment circuit, 14v and 14h are interference control correlators, 15v and 15h are waveform equalization correlators, 16v is a delay circuit, 16h is a self-descramble circuit, 20 and 23 are n-stage shift registers, 21, 22 and 24 and 25 respectively represent exclusive logic circuits.

Claims (1)

[Claims] 1. An orthogonal polarization digital wireless communication line for transmitting separate information in two polarized waves (V polarized wave and H polarized wave) orthogonal to each other at a carrier frequency, wherein a flat transmission spectrum and bits on a receiving side are provided. In order to facilitate the reproduction of synchronization, in the scramble processing method in which the non-modulated signal is scrambled, the transmitting side transmits the first baseband signal to be transmitted in the V polarization transmitted from the multiplexing terminal device. A first scramble circuit that scrambles a signal with a first pseudo-random code, and a second baseband signal to be transmitted with H polarization similarly sent from the multiplexing terminal device. A second scramble circuit for performing scramble processing by the second pseudo-random code, an output of the first scramble circuit, and an output of the second scramble circuit. A first self-scramble circuit connected to one of the two outputs for performing a self-scramble process by a third pseudo-random code, and a self-scramble process by a fourth pseudo-random code connected to the other of the two outputs. The first self delay circuit that gives a delay equivalent to the delay time of the second self scramble circuit or the first self scramble circuit, the output of the first self scramble circuit, and the second self scramble circuit or the first self scramble circuit. Of the two outputs, the output of the delay circuit, V
A first modulation circuit that modulates a first baseband output signal that should be transmitted by polarization and a second modulation circuit that modulates a second baseband output signal that should be transmitted by H polarization. A first demodulation circuit for demodulating the modulated signal transmitted and received by the V-polarized wave and the H-polarized wave. Of the output signal of the first demodulation circuit and the output signal of the second demodulation circuit, the reception section including the second demodulation circuit that demodulates the transmitted and received modulated signal, the first self-scramble on the transmission side. For the output signal to which the circuit is connected, a first self-descramble circuit that performs self-descramble processing with the same pseudo-random code as the first self-scramble circuit is provided, and the second self-scrambling circuit is provided on the transmission side. The circuit Is a second self-descramble circuit or a first self-descrambler that performs self-descramble processing with the same pseudo-random code as the second self-scramble circuit for the output signal to which the first delay circuit is connected. A scramble processing method comprising: a second delay circuit that gives a delay equivalent to the delay time of the circuit.