JPH0752416B2 - Microcomputer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention is a microcomputer system, in which a peripheral circuit is provided with a control unit, and the control unit controls the peripheral circuit in accordance with a bus control command to transfer data. It speeds up and reduces the number of bytes of instructions stored in memory.

[Industrial application field]

The present invention relates to a microcomputer system, and more particularly to a microcomputer system in which a central processing unit (hereinafter referred to as “CPU”) and a plurality of peripheral circuits are connected by a bus line.

The microcomputer system, as shown in FIG.
CPU10, ROM11, RAM12, floating point arithmetic circuit (hereinafter "FPC")
13, timer circuit 14, I / O interface circuit 15
And other peripheral circuits. A bus line 16 connects the CPU 10 and each peripheral circuit.

[Conventional technology]

In a conventional microcomputer system, CPU10
Data is exchanged between the peripheral circuit and each peripheral circuit by the CPU 10 executing a transfer instruction. Data transmission / reception between the two peripheral circuits, such as the RAM 12 and the I / O interface circuit 15, is performed as data transmission / reception between the CPU 10 and RAM 12 and data transmission / reception between the CPU 10 and I / O interface circuit 15.

Of course, it is possible to directly transfer data between the RAM 12 and the I / O interface circuit 15, for example, by providing a DMA (Direct Memory Access) controller, but DMA transfer can transfer a large amount of data continuously. It is effective only when transferring a small amount of data and is not used when transferring a small amount of data.

[Problems to be solved by the invention]

In the above conventional computer system, for example, CP
Numerical data stored in the first and second registers in U10
Consider the case of trying to multiply A and B by FPC13.

In this case, the CPU 10 reads the write instruction from the ROM 11 in the first cycle, decodes this instruction in the second cycle, and writes the numerical data A in the source register of the FPC 13 in the third cycle. The write instruction is 1 byte instruction code and FPC13
The address consists of 1 byte. Next, similarly, the numerical data B is written in the destination register of the FPC 13 by a write command.

Next, the CPU 10 reads the no-operation instruction from the ROM 11 twice in succession. No operation instruction is instruction code 1
It is only a byte, and the CPU 10 waits here for two cycles, during which the FPC 13 performs floating point multiplication of the numerical data A and B, and stores the multiplication result data in the destination register.

Next, the CPU 10 reads the read instruction from the ROM 11 in the first cycle, decodes this instruction in the second cycle, and reads the numerical data of the source register of the FPC 13 into the first register in the CPU 10 in the third cycle. Next, similarly, a read instruction is used to read the numerical data in the destination register into the second register in the CPU 10.

As described above, data transfer by a write command, a read command, etc. requires 3 cycles each, and 14 cycles are required for the above-mentioned entire operation, resulting in a slow execution speed. In addition, each of the write instruction and the read instruction has 2 bytes, which requires 10 bytes for the entire operation, and there is a problem that the number of instruction bytes occupying the ROM 11 is large.

The present invention has been made in view of the above points, and an object of the present invention is to provide a microcomputer system capable of performing data transfer at high speed and reducing the number of instruction bytes occupying the ROM 11.

[Means for solving problems]

The microcomputer system of the present invention is a bus control for designating an arbitrary peripheral circuit (22-25) and instructing a plurality of times of data input / output to / from a bus line (26) of the designated peripheral circuit (22-25). Instructions are stored in the memory (21), and control units (22a to 2) provided in each of the plurality of peripheral circuits (22 to 25).
5a) and the central processing unit (20) hold the operation sequence, and the bus control command read from the memory (21) to the bus line (26) controls the control unit (22a to 25a) and the central processing unit (20).
Each of them detects and executes an operation sequence according to the designation of the bus control instruction and the instruction, and the central processing unit (20) and the designated peripheral circuits (22 to 25) are simultaneously operated in parallel by the bus control instruction to perform mutual operation. Send and receive data to and from.

[Action]

In the present invention, when the bus control instruction is read from the memory (21), the control units (22a) of the peripheral circuits (22 to 25) respectively.
25a), the one specified in the bus control instruction executes the operation sequence according to the instruction of the bus control instruction to perform the data input / output operation a plurality of times, and the CPU (20) executes this bus control instruction. A corresponding operation sequence is executed to perform an operation according to the data input / output operation of the peripheral circuits (22 to 25) a plurality of times. This allows the CPU (2
0) and peripheral circuits (22 to 25) are exchanged multiple times.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the microcomputer system of the present invention. In the figure, 20 is a CPU, and this C
A bus line 26 connects the PU 20 and peripheral circuits such as the ROM 21, RAM 22, FPC 23, timer circuit 24, and I / O interface circuit 25.

The ROM 21 stores a program of instructions executed by the CPU 20. This program uses bus control instructions in addition to ordinary data transfer instructions, arithmetic instructions, bit manipulation instructions, and the like.

The bus control instruction is a 2-byte instruction as shown in FIG. The first byte is a specific instruction code 30 for identifying a bus control instruction. The upper 4 bits of the next 2nd byte is a resource number 31 that designates peripheral circuits (resources) such as the RAM 22, FPC 23, timer circuit 24, I / O interface circuit 25, etc., and the lower 4 bits of the designated peripheral circuit. Operation number 32 to instruct multiple data input / output operations
Is.

For example, when the value of the resource number is "3" and the FPC 23 is instructed, the FPC 23 sequentially executes the operation sequence corresponding to the operation number as shown in FIG. In the operation sequence in FIG. 3, “R” represents data writing, “W” represents data reading, and “X” represents data calculation. In the operation sequence column, each operation is sequentially executed in one cycle from left to right.

Each of the RAM 22, FPC 23, timer circuit 24, and I / O interface circuit 25 has a data transfer control unit 22a, 23a, 24a, 25a.

The data transfer control units 22a to 25a have substantially the same configuration, and the FPC2
The data transfer control unit 23a of 3 will be described as an example with reference to FIG.

In FIG. 4, the terminal 40 is connected to the bus line 26. Instructions, data, etc. transmitted through the bus line 26 come in from the terminal 40 and are supplied to the code detection circuit 41, the latch circuit 42 in the data transfer control unit 23a, the source register 43 of the FPC 23, and the destination register 44, respectively. To be done.

In the code detection circuit 41, the first byte of the instruction coming from the bus line 26 matches the instruction code 30 of the bus control instruction, and the upper 4 bits of the second byte specify the resource number 31 (value "3") that specifies the FPC 23. ) Is detected, and when they match, a latch instruction signal is supplied to the latch circuit 42.

The latch circuit 42 is supplied with the lower 4 bits of the second byte of the instruction coming from the bus line 26, and latches the operation number 32 of the lower 4 bits by supplying the latch instruction signal. The operation number 32 latched by the latch circuit 42 is supplied to the decoder 45, where it is decoded and supplied to the sequencer 46.

The sequencer 46 uses the FPC2 depending on the decoding result of the decoder 45.
A control signal is supplied to each of the source register 43, the destination register 44, and each of the other circuits constituting the 3 to control their operations.

Here, when the CPU 20 sequentially reads the instructions in the program from the ROM 21 and executes them, the value of the resource number is "3".
It is assumed that the bus control instruction having the operation number value "2" is read from the ROM 21 in the first cycle. In this case, CPU20
Decodes the bus control instruction in the second cycle, sends the numerical data A stored in the first register in the CPU 20 to the bus line 26 in the third cycle, and in the fourth cycle, CPU2
The numerical data B of the second register within 0 is sent to the bus line 26.

At the same time, the sequencer 46 in the FPC 23 instructs the source register 43 to store the numerical data A coming from the terminal 40 in the third cycle according to the decoding result of the decoder 45 in the second cycle, and the destination register 44 in the fourth cycle. To store the numerical data B coming from the terminal 40.

Thereafter, the sequencer 46 causes the numerical data A of the source register 43 and the numerical data B of the destination register 44 to be calculated in the fifth cycle and the sixth cycle, and the calculation result data is stored in the destination register.
Store in 44. During this time, the CPU 20 is waiting.

The sequencer 46 sends the numerical data of the source register 43 to the bus line 26 from the terminal 40 in the seventh cycle, and sends the operation result data of the destination register 44 to the bus line 26 from the terminal 40 in the eighth cycle. With this
The CPU 20 stores the numerical data coming from the bus line 26 in the first register in the seventh cycle, and stores the operation result data coming from the bus line 26 in the second register in the eighth cycle.

In this way, when the 2-byte bus control instruction is sent from the ROM 21 to the bus line 26, the floating point calculation is completed in the subsequent 8 cycles. In other words, the processing that previously required 14 cycles can be executed at a high speed of 8 cycles,
Further, the above processing is executed only by the 2-byte bus control instruction, and the number of instruction bytes of the program stored in the ROM 21 can be reduced.

Similarly, the data transfer control unit corresponding to the bus control command
22a, 24a, 25a and CPU20 operate in parallel,
Data can be exchanged at high speed with peripheral circuits such as the AM 22, the timer circuit 24, and the I / O interface circuit 25.

If necessary, a data transfer control unit may be provided in the ROM 21 to transfer data between the CPU 20 and the ROM 21 at high speed, and the present invention is not limited to the above embodiment.

〔The invention's effect〕

As described above, according to the microcomputer system of the present invention, data can be exchanged between the CPU and the peripheral circuit at high speed, and the number of bytes of the instruction stored in the memory can be reduced. Above all very useful.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a microcomputer system of the present invention, FIG. 2 is a diagram for explaining the configuration of bus control instructions, FIG. 3 is a diagram for explaining operation numbers, and FIG. FIG. 5 is a block system diagram of an embodiment of a data transfer control unit, and FIG. 5 is a block diagram of an example of a conventional system. In the drawing, 20 is a central processing unit (CPU), 21 is a ROM, 22 is a RAM, 22a, 23a, 24a and 25a are data transfer control units, 23 is a floating point arithmetic circuit (FPC), 24 is a timer circuit, and 25 is It is an I / O interface circuit.

Claims (1)

[Claims] 1. A bus line () between a central processing unit (20) and a plurality of peripheral circuits (21 to 25) including a memory (21) storing instructions executed by the central processing unit (20). In the microcomputer system connected in step 26), specify any peripheral circuit (22-25) and instruct multiple times of data input / output to the bus line (26) of the specified peripheral circuit (22-25) A bus control command to be stored in the memory (21), and a control unit (22a) provided in each of the plurality of peripheral circuits (22 to 25).
To 25a) and the central processing unit (20) hold the operation sequence, and the bus control command read from the memory (21) to the bus line (26) is transferred to the control unit (22a to 25a) and the central processing unit. (20) Each of them detects and executes an operation sequence according to the designation of the bus control instruction and the instruction, and the central processing unit (20) and the designated peripheral circuits (22-25) are executed by the bus control instruction. A microcomputer system characterized by operating in parallel at the same time and exchanging data with each other.