JPH0752775B2 - Input protection circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input protection circuit device provided in a semiconductor integrated circuit device, and more particularly, to an input protection circuit having a reduced layout area and a measure against electrostatic breakdown directly below a pad electrode. Regarding circuit devices.

[Conventional technology]

An example of an input protection circuit device in a conventional MOS semiconductor integrated circuit device is shown in FIG. Here, the input protection circuit device is an example in which an N-type impurity layer is used on a P-type semiconductor substrate, and FIG. 7A is a layout diagram thereof and FIG.
Is an electric circuit diagram.

In the figure, a pad 2 is formed of a metal layer on a P-type semiconductor substrate 1, and N-type impurity layers 5 and 6 are formed side by side at positions adjacent to the pad 2. Then, a part of the pad 2 is connected to the N-type impurity layer 5 via the contact 7, and the N-type impurity layer 5 is electrically connected to the polycrystalline silicon wiring 4 via the contact 3 to form a first-stage circuit (not shown). Electrically connected to.

Further, a part of the pad 2 is provided on the position adjacent to the N-type impurity layers 5 and 6, and the pad 2 serves as a gate,
A MOS transistor 22 having 6 as a source / drain is configured. The N-type impurity layer 5 and the P-type semiconductor substrate 1 form a diode 23. The N-type impurity layer 6 is electrically connected to the ground wiring 9 via the contact 8.
Further, 10 is a cover opening.

With this configuration, the protection circuit of FIG. 3B is configured, and when an abnormally high voltage such as static electricity is applied to the input terminal 21 from the outside, the MOS transistor 22 having a high threshold value is turned on, Moreover, the surge current is released to the substrate by the breakdown current of the diode 23, the voltage of the node between the input terminal 21 and the input first stage transistor is reduced, and the electric field strength applied between the gate of the input first stage transistor and the semiconductor substrate is reduced to reduce the input first stage. This prevents damage to the gate oxide film of the transistor.

[Problems to be Solved by the Invention]

The above-mentioned conventional input protection circuit device uses a diode in order to release the charge against an abnormally high voltage applied to the input terminal 21 so as not to destroy the input protection circuit device itself.
It is necessary to make the PN junction area of 23 and the channel width of the MOS transistor 22 sufficiently large. Normally, the width of the N-type impurity layers 5 and 6 is required to be 10/20 μm, and the channel width of the MOS transistor 22 is required to be approximately 50 to 100 μm. Therefore, the N-type impurity layers 5 and 6 forming the diode 23 and the MOS transistor 22 are formed.
Of the input protection circuit device increases, which is not preferable in terms of high integration. Also, pad 2
There is also a problem in that the abnormal voltage applied to the input terminal 21 causes dielectric breakdown of the interlayer film below the pad 2, causing the pad 2 to short-circuit with the semiconductor substrate 1 and causing a defect.

An object of the present invention is to provide an input protection circuit device that reduces the occupied area and prevents the dielectric breakdown of pad underwear.

[Means for Solving the Problems]

The input protection circuit device of the present invention is provided with a single reverse type electrode over a substantially entire surface of a pad, which is formed on a semiconductor substrate of one conductivity type with an interlayer insulating film interposed therebetween, directly below the pad as an input terminal. In addition to forming a conductivity type impurity layer, a part of another opposite conductivity type impurity layer connected to ground is extended, and these two opposite conductivity type impurity layers form the source / drain of the MOS transistor. A diode is composed of the one impurity layer of opposite conductivity type and the semiconductor substrate, and the pad and one impurity layer of opposite conductivity type are electrically connected to each other through a contact hole provided at one corner of the pad.

[Action]

In the above-described configuration, the MOS transistor and the diode are formed in the region just below the pad, and the occupied area is reduced.
Further, the N-type impurity layer provided immediately below the pad is kept at the same potential as the pad to prevent dielectric breakdown of the insulating film below the pad.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows the first embodiment of the present invention, and FIG.
Is a plan layout diagram, and FIG. 6B is a circuit diagram. .

In FIG. 1A, a pad 2 is formed on the P-type semiconductor substrate 1 with a metal layer such as aluminum, and a part of this pad 2 is electrically connected to the polycrystalline silicon wiring 4 through a contact 3 and is not shown in the figure. It is electrically connected to the first stage circuit. An N-type impurity layer 5 is formed immediately below the pad 2, and an N-type impurity layer 6 is formed adjacent to the N-type impurity layer 5 and a part of which is located directly below the pad 2. ing. The N-type impurity layer 5 is electrically connected to the pad 2 by the contact 7, and the N-type impurity layer 6 is electrically connected to the ground wiring 9 by the contact 8. Reference numeral 10 is a cover opening for exposing the surface of the pad 2, which is opened in an insulating film (not shown) provided thereon.

With this configuration, as shown in FIG.
The type impurity layers 5 and 6 form a MOS transistor 22 having the pad 2 as a gate, the N-type impurity layer 5 as a drain, and the N-type impurity layer 6 as a source. Directly below the pad 2, the N-type impurity layer 5 and the P-type semiconductor substrate 1 form a diode 23. Then, a circuit is constructed in which the gate and source of the MOS transistor 22 and the cathode of the diode 23 are connected to the pad 2 and the initial stage circuit, and the drain and anode are grounded.

Therefore, in this circuit, during normal operation, the input terminal 21
From the pad 2 through the contact 3 and the polycrystalline silicon wiring 3 to reach the first-stage circuit. Input terminal 21
When an abnormally high voltage is applied to, the MOS transistor 22 having a high threshold, which does not normally operate, is turned on, and a breakdown current flows through the diode 23, so that the charge of the pad 2 is released to the semiconductor substrate 1. Operate. As a result, the first-stage circuit is protected from damage due to high bias application. Further, since the pad 2 has the N-type impurity layer 5 of the same potential immediately below it, the strength of the electric field with respect to the semiconductor substrate 1 is remarkably reduced, and the interlayer immediately below the pad 2 due to an abnormally high voltage applied to the input terminal 21. Dielectric breakdown of the film is prevented.

Needless to say, the occupied area can be reduced by disposing the N-type impurity layer 5 immediately below the pad 2.

FIG. 2 shows a second embodiment of the present invention. FIG. 2A is a plan layout diagram and FIG. 2B is a circuit diagram thereof. In addition,
Parts equivalent to those in FIG. 1 are designated by the same reference numerals.

In this embodiment, polycrystalline silicon is formed on a region adjacent to the N-type impurity layer 5 formed immediately below the pad 2 and the N-type impurity layer 6 located adjacent to the N-type impurity layer 5 and partially located directly below the pad 2. A film 11 is formed to form a MOS transistor 22A having the polycrystalline silicon film 11 as a gate. The polycrystalline silicon film 11 is electrically connected to the ground wiring 9 via the contact 12.

With this configuration, the circuit configuration shown in FIG.
The S transistor 22A is protected by using the breakdown current between the source and drain. Therefore,
In this embodiment as well, the first-stage circuit can be protected from an abnormally high voltage as in the embodiment of FIG. 1, and by providing the N-type impurity layer 5 forming the diode 23 immediately below the pad 2. It is possible to prevent dielectric breakdown directly below the pad 2. Further, since the N-type impurity layer 5 and the like are formed immediately below the pad 2, the occupied area can be reduced.

The present invention can be similarly applied to a semiconductor device using an N-type semiconductor substrate.

〔The invention's effect〕

As described above, the present invention reduces the occupation area of the input protection circuit device and increases the integration of the semiconductor device by forming the MOS transistor and the diode that form the input protection circuit device substantially in the region directly below the pad. To realize. Also, by maintaining the N-type impurity layer provided directly under the pad at the same potential as the pad, the electric field between the pad and the semiconductor substrate is mitigated, and the dielectric breakdown of the lower insulating film is prevented to prevent the short circuit of the pad. There is an effect that can be done. In addition, in the present invention, the interlayer insulating film located immediately below the pad can prevent moisture that has entered the pad from the outside from reaching the semiconductor substrate directly below, and can improve the water resistance of the semiconductor substrate. Needless to say.

[Brief description of drawings]

1 shows a first embodiment of the present invention, FIG. 1 (a) is a plan layout diagram, FIG. 1 (b) is an electric circuit diagram, and FIG. 2 shows a second embodiment of the present invention. (A) is a plane layout diagram, (b) is an electric circuit diagram, (3) shows a conventional input protection circuit device, (a) is a plane layout diagram, (b) is an electric circuit diagram. Is. 1 ... P-type semiconductor substrate, 2 ... pad, 3 ... contact, 4 ... polycrystalline silicon wiring, 5,6 ... N-type impurity layer, 7,8 ... contact, 9 ... ground wiring, 10 …… Cover opening, 11 …… Polycrystalline silicon film, 12 …… Contact,
21 …… Input terminal, 22,22A …… MOS transistor, 23 ……
diode.

Claims (1)

[Claims] 1. Immediately below a pad as an input terminal formed on a semiconductor substrate of one conductivity type with an interlayer insulating film interposed therebetween, one impurity of opposite conductivity type is provided over the substantially entire surface of the pad with the interlayer insulating film being separated. Forming a layer and extending a part of another opposite conductivity type impurity layer connected to the ground, these two opposite conductivity type impurity layers constitute the source / drain of the MOS transistor, and An input protection circuit characterized in that a diode is constituted by a conductivity type impurity layer and a semiconductor substrate, and the pad and one opposite conductivity type impurity layer are electrically connected by a contact hole provided at one corner of the pad. apparatus.