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JPH0752809B2 - FM demodulation circuit - Google Patents
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JPH0752809B2 - FM demodulation circuit - Google Patents

FM demodulation circuit

Info

Publication number
JPH0752809B2
JPH0752809B2 JP59257574A JP25757484A JPH0752809B2 JP H0752809 B2 JPH0752809 B2 JP H0752809B2 JP 59257574 A JP59257574 A JP 59257574A JP 25757484 A JP25757484 A JP 25757484A JP H0752809 B2 JPH0752809 B2 JP H0752809B2
Authority
JP
Japan
Prior art keywords
circuit
signal
output
outputs
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59257574A
Other languages
Japanese (ja)
Other versions
JPS61136308A (en
Inventor
正樹 野田
敬郎 新川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59257574A priority Critical patent/JPH0752809B2/en
Publication of JPS61136308A publication Critical patent/JPS61136308A/en
Publication of JPH0752809B2 publication Critical patent/JPH0752809B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Circuits Of Receivers In General (AREA)

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、FM変調信号を復調するFM復調回路の構成に係
り、特に衛星放送等の弱電界での復調に好適な位相ロッ
クループ(Phase Locked Loop;以下PLLと略称)FM復調
回路に関するものである。
The present invention relates to a configuration of an FM demodulation circuit for demodulating an FM modulated signal, and particularly to a phase locked loop (Phase Locked Loop) suitable for demodulation in a weak electric field such as satellite broadcasting. Loop; hereinafter abbreviated as PLL) The present invention relates to an FM demodulation circuit.

〔発明の背景〕[Background of the Invention]

従来PLL・FM復調回路のスレッショルドレベルを改善す
る方法しとて、例えば特開昭57−171808号公報に示され
るように、中高電界時には最適な回路定数により広帯域
な検波特性を確保し、雑音の問題となる弱電界時にはPL
Lのアンプゲインを制御することにより、復調帯域を狭
帯域化するものが知られている。ここに示された例はFM
ラジオ放送の受信機に関するものであるが衛星放送用受
信機においても同様である。しかし、よりスレッショル
ドレベルを改善するには復調帯域の狭帯域化前のスレッ
ショルドレベルを向上させ合わせて狭帯域化の手段を用
いる必要があった。また、衛星放送用受信機では映像の
S/NがFM復調回路に入力される信号の電界レベルではな
くアンテナで受信したマイクロ波信号のC/Nでほぼ決定
されるため、例に示されている復調帯域の狭帯域化切換
へを信号の電界レベルによる方法ではなく信号のC/Nに
よって動作させる問題があった。
As a method of improving the threshold level of a conventional PLL / FM demodulation circuit, for example, as disclosed in Japanese Patent Laid-Open No. 57-171808, a wide band detection characteristic is secured by an optimum circuit constant in a medium and high electric field, and noise of PL in case of weak electric field
It is known that the demodulation band is narrowed by controlling the amplifier gain of L. The example shown here is FM
Although it relates to a radio broadcast receiver, the same applies to a satellite broadcast receiver. However, in order to further improve the threshold level, it is necessary to improve the threshold level of the demodulation band before narrowing the band and use a means for narrowing the band. In addition, satellite receivers
Since the S / N is almost determined not by the electric field level of the signal input to the FM demodulation circuit but by the C / N of the microwave signal received by the antenna, the narrowing band switching of the demodulation band shown in the example can be used. There was a problem of operating by the C / N of the signal instead of the method by the electric field level of the signal.

〔発明の目的〕[Object of the Invention]

本発明の目的は、上記したPLL・FM復調回路の欠点を解
消し、簡単な構成で弱電界時のスレッショルドレベルの
改善が得られるFM復調回路を提供することにある。
An object of the present invention is to solve the above-mentioned drawbacks of the PLL / FM demodulation circuit and to provide an FM demodulation circuit which can improve the threshold level in a weak electric field with a simple configuration.

〔発明の概要〕 本発明では、復調回路内で復調信号を帰還させ復調帯域
でのPLLのループ利得を増加させることでスレッショル
ドレベルの向上を図り、さらに雑音の問題になる弱電界
時には入力C/Nに対応して上記帰還を制御することでPLL
のループ利得を制御しスレッショルドレベルの改善を行
なう。
[Summary of the Invention] In the present invention, the threshold level is improved by increasing the loop gain of the PLL in the demodulation band by feeding back the demodulation signal in the demodulation circuit, and input C / PLL by controlling the above feedback corresponding to N
The loop gain is controlled to improve the threshold level.

〔発明の実施例〕Example of Invention

以下、本発明の一実施例を第1図により説明する。入力
端子1からFM中間周波信号を入力し位相検波器2,差動増
幅器3,ループフィルタ4と電圧制御発振器5の閉ループ
によりPLL・FM復調回路を形成し、差動増幅器3の他方
の出力を増幅器6を介して差動増幅器3の定電流源に帰
還し、ループフィルタ4の出力を分岐してループ利得制
御回路7に接続し、ループ利得制御回路7の出力を増幅
器6に印加し、ループフィルタ4の出力のもう一方の分
岐から出力端子8より復調されたテレビ信号を取り出す
構成である。位相検波器2の出力は差動増幅器3と増幅
器6から成る帰還増幅器により増幅器6のもつ周波数特
性で帯域整形を受け増幅される。また、ループフィルタ
4の出力、すなわち復調出力よりループ利得制御回路7
を通して得られる受信信号のC/Nに対応したコントロー
ル電圧を増幅器6に入力して、PLL・FM復調回路の復調
帯域幅を制御する。
An embodiment of the present invention will be described below with reference to FIG. The FM intermediate frequency signal is input from the input terminal 1 to form the PLL / FM demodulation circuit by the closed loop of the phase detector 2, the differential amplifier 3, the loop filter 4 and the voltage controlled oscillator 5, and the other output of the differential amplifier 3 It is fed back to the constant current source of the differential amplifier 3 via the amplifier 6, the output of the loop filter 4 is branched and connected to the loop gain control circuit 7, the output of the loop gain control circuit 7 is applied to the amplifier 6, and the loop The demodulated television signal is taken out from the output terminal 8 from the other branch of the output of the filter 4. The output of the phase detector 2 is band-shaped by the feedback amplifier including the differential amplifier 3 and the amplifier 6 with the frequency characteristic of the amplifier 6 and amplified. In addition, the loop gain control circuit 7 outputs from the output of the loop filter 4, that is, the demodulation output.
A control voltage corresponding to the C / N of the received signal obtained through is input to the amplifier 6 to control the demodulation bandwidth of the PLL / FM demodulation circuit.

第2図は第1図のブロック図における差動増幅器3と増
幅器6から成る帰還増幅器の一回路例を示すもので、差
動増幅器3はトランジスタQ3の定電流源をもつトランジ
スタQ1とQ2の差動増幅回路とトランジスタQ6のエミッタ
・ホロワから構成され、トランジスタQ1のベース9に位
相検波器2の出力を接続し、トランジスタQ2のベースを
接地し、トランジスタQ1のコレクタからトランジスタQ6
のエミッタ・ホロワを介して信号を出力しこの出力端子
10をループフィルタ4へ接続し、トランジスタQ2のコレ
クタを増幅器6の入力に接続する。増幅器6はトランジ
スタQ4とQ5からなる増幅回路で構成され、差動増幅器3
の出力はフィルタ11を通してトランジスタQ4のベースに
接続され、トランジスタQ4のコレクタはトランジスタQ5
のベースに接続され、トランジスタQ5のコレクタ出力す
なわち増幅器6の出力は差動増幅器3のトランジスタQ3
のベースに接続される。また、トランジスタQ4のコレク
タはコンデンサ12とダイオード13で接地し、コンデンサ
12とダイオード13の接続点にはループ利得制御回路7の
出力が端子14より短絡制御回路15を介して印加される。
この回路においてはトランジスタQ2のコレクタ電圧が増
幅器6を介してトランジスタQ3のベースに印加されるこ
とからトランジスタQ3のベース電圧はトランジスタQ2
コレクタ電圧に比例して変動し、従ってトランジスタQ3
のコレクタ電流も同様に変動し、トランジスタQ2のコレ
クタ電圧に対してはその変動を抑圧する方向へ、トラン
ジスタQ1のコレクタ電圧すなわち差動増幅器3の出力は
変動が増加する方向へ、換言すると利得が増大する動作
を行なう。利得の増大する割合は増幅器6の利得が十分
大きいとすると、増幅器6による帰還をかけないものに
比較し約2倍の利得が得られる。この帰還動作によって
フィルタ11と後段のループフィルタ4と合わせて急峻な
帯域特性が得られる。
FIG. 2 shows a circuit example of a feedback amplifier composed of the differential amplifier 3 and the amplifier 6 in the block diagram of FIG. 1. The differential amplifier 3 has transistors Q 1 and Q having a constant current source of transistor Q 3. It consists of the differential amplifier circuit of 2 and the emitter / follower of the transistor Q 6. The output of the phase detector 2 is connected to the base 9 of the transistor Q 1 , the base of the transistor Q 2 is grounded, and the collector of the transistor Q 1 is connected. Transistor Q 6
This output terminal outputs a signal through the emitter follower of
Connect 10 to loop filter 4 and connect the collector of transistor Q 2 to the input of amplifier 6. The amplifier 6 is composed of an amplifier circuit composed of transistors Q 4 and Q 5 , and has a differential amplifier 3
The output of is connected to the base of transistor Q 4 through filter 11, and the collector of transistor Q 4 is connected to transistor Q 5
Is connected to the base of the transistor Q 5 , and the collector output of the transistor Q 5 , that is, the output of the amplifier 6 is connected to the transistor Q 3 of the differential amplifier 3.
Connected to the base of. Also, the collector of transistor Q 4 is grounded by capacitor 12 and diode 13,
The output of the loop gain control circuit 7 is applied to the connection point between the diode 12 and the diode 13 from the terminal 14 via the short circuit control circuit 15.
In this circuit, since the collector voltage of the transistor Q 2 is applied to the base of the transistor Q 3 via the amplifier 6, the base voltage of the transistor Q 3 fluctuates in proportion to the collector voltage of the transistor Q 2. 3
Similarly, the collector current of the transistor Q 2 also fluctuates with respect to the collector voltage of the transistor Q 2 , and the collector voltage of the transistor Q 1 , that is, the output of the differential amplifier 3 increases. Performs an operation that increases the gain. Assuming that the gain of the amplifier 6 is sufficiently large, the rate of increase in gain is about twice as high as that of the amplifier 6 without feedback. By this feedback operation, a steep band characteristic can be obtained by combining the filter 11 and the loop filter 4 in the subsequent stage.

第3図は、PLLの開ループ特性を示した図で、縦軸にPLL
の開ループ利得を横軸に周波数を示し、増幅器6による
帰還をかけない特性15とかけた特性16である。増幅器6
による帰還をかけた場合閉ループ利得が増大しても帯域
のスカート特性が広がらず雑音帯域幅を狭まくでき、通
常の受信電界では広帯域な復調特性を得ると共にスレッ
ショルドレベルの向上も図られる。ここで雑音が問題に
なるスレッショルド付近の弱電界時には、増幅器6によ
る帰還を止めることでPLLの閉ループ利得は特性15の低
利得となり、復調範囲を狭帯域にしてさらにスレッショ
ルドレベルの改善を行なうことができる。本実施例にお
いて増幅器6の帰還を止めるには、ループ利得制御回路
7からの信号のC/Nに対応して発生する制御電圧が適当
な閾値を越えると短絡制御回路15により直流電圧がダイ
オード13に印加されダイオード13を導通させ信号をコン
デンサ12で接地することにより簡単に行なえ、コンデン
サ12の容量は復調信号に対して十分接地できる容量、例
えば1000PF以上あればよい。なお、ダイオード13とコン
デンサ12の配置はトランジスタQ4のベースあるいはトラ
ンジスタQ5のコレクタ等のほか、増幅器6で信号が検出
される部分に配置しても同様な効果が得られる。また、
フィルタ11の配置もトランジスタQ5のベースあるいはト
ランジスタQ5のコレクタに配置しても効果は同じであ
る。
Figure 3 shows the open loop characteristics of the PLL, with the vertical axis representing the PLL.
The open loop gain is represented by the frequency on the abscissa, and is a characteristic 15 in which feedback by the amplifier 6 is not applied and a characteristic 16 in which feedback is not applied. Amplifier 6
When the feedback is applied by, the skirt characteristic of the band is not widened even if the closed loop gain is increased, and the noise bandwidth can be narrowed, and the demodulation characteristic of a wide band is obtained in a normal reception electric field and the threshold level is improved. In a weak electric field near the threshold where noise is a problem, the closed loop gain of the PLL becomes a low gain of characteristic 15 by stopping the feedback by the amplifier 6, and the demodulation range can be narrowed to further improve the threshold level. it can. In order to stop the feedback of the amplifier 6 in this embodiment, when the control voltage generated corresponding to the C / N of the signal from the loop gain control circuit 7 exceeds an appropriate threshold value, the short circuit control circuit 15 changes the DC voltage to the diode 13 Can be easily performed by turning on the diode 13 and grounding the signal with the capacitor 12, and the capacity of the capacitor 12 may be sufficient to ground the demodulated signal, for example, 1000 PF or more. The diode 13 and the capacitor 12 may be arranged at the base of the transistor Q 4 , the collector of the transistor Q 5 , or the like, or at a portion where a signal is detected by the amplifier 6 to obtain the same effect. Also,
Placement of the filter 11 effects be disposed to the collector of the base or the transistor Q 5 of the transistor Q 5 are the same.

第4図は、ループ利得制御回路7の一具体例を示すもの
で端子17に入力された復調信号は分岐され、一方は同期
パルス発生回路18に入力されその出力ともう一方の復調
信号とはサンプリング回路19に入力され、増幅回路20を
通して、検波回路21によりコントロール電圧を発生し増
幅器6を制御する。
FIG. 4 shows a specific example of the loop gain control circuit 7. The demodulated signal input to the terminal 17 is branched, one is input to the synchronization pulse generation circuit 18, and its output and the other demodulated signal are It is input to the sampling circuit 19, and a detection circuit 21 generates a control voltage through the amplification circuit 20 to control the amplifier 6.

第5図は、第4図のループ利得回路7の動作原理図で、
雑音を含んだ復調信号aより同期パルス発生回路18で同
期信号に一致したパルス信号bを発生し、パルス信号b
によってサンプリング回路19で復調信号aより同期信号
に重畳された雑音成分22を抜取り、増幅回路20で雑音成
分22を増幅し、検波回路21で増幅された雑音成分を検波
し受信信号のC/Nに対応した直流電圧を発生する。本実
施例では、水平同期信号を用いたが、垂直同期信号も同
様に用いることができることは明らかである。
FIG. 5 is an operation principle diagram of the loop gain circuit 7 of FIG.
From the demodulated signal a containing noise, a pulse signal b matching the synchronizing signal is generated by the synchronizing pulse generating circuit 18, and the pulse signal b
The sampling circuit 19 extracts the noise component 22 superimposed on the synchronization signal from the demodulation signal a, the amplification circuit 20 amplifies the noise component 22, and the detection circuit 21 detects the amplified noise component to detect the C / N of the received signal. DC voltage corresponding to is generated. Although the horizontal synchronizing signal is used in this embodiment, it is obvious that the vertical synchronizing signal can be used as well.

第6図は、差動増幅器3と増幅器6から成る帰還増幅回
路の別の具体例で、第2図と同一符号は同一または相当
部分を示し、トランジスタQ4のコレクタをコンデンサ12
と可変容量ダイオード23で接地し、コンデンサ12と可変
容量ダイオード23との接続点にループ利得制御回路7か
ら受信信号のC/Nに対応した直流電圧を印加する。可変
容量ダイオード23の容量を変化させることで接地容量を
変え、第3図に示したPLLの開ループ利得の特性16から
特性15への変化が連続に行なわれ画質の急激な変化を防
止することができる。なお、コンデンサ12と可変容量ダ
イオード23の配置はトランジスタQ4のベースあるいはト
ランジスタQ5のコレクタ等のほか、増幅器6で信号が検
出される部分に配置しても同様な効果が得られる。
FIG. 6 shows another specific example of the feedback amplifier circuit including the differential amplifier 3 and the amplifier 6. The same reference numerals as those in FIG. 2 denote the same or corresponding portions, and the collector of the transistor Q 4 is connected to the capacitor 12
And the variable capacitance diode 23 to ground, and a DC voltage corresponding to C / N of the received signal is applied from the loop gain control circuit 7 to the connection point between the capacitor 12 and the variable capacitance diode 23. The ground capacitance is changed by changing the capacitance of the variable capacitance diode 23, and the open loop gain of the PLL shown in FIG. 3 is continuously changed from the characteristic 16 to the characteristic 15 to prevent a sharp change in the image quality. You can The same effect can be obtained by arranging the capacitor 12 and the variable capacitance diode 23 not only at the base of the transistor Q 4 or the collector of the transistor Q 5 but also at a portion where a signal is detected by the amplifier 6.

〔発明の効果〕〔The invention's effect〕

本発明によれば、復調回路内で復調信号を帰還させるこ
とで復調帯域でのPLLのループ利得を増加させスレッシ
ョルドレベルの向上を図り、雑音の問題になる弱電界時
には入力C/Nに対応して上記帰還を制御することでPLLの
ループ利得を制御しスレッショルドレベルの改善を行な
い良好な画質が得られる効果がある。
According to the present invention, by feeding back the demodulation signal in the demodulation circuit, the loop gain of the PLL in the demodulation band is increased to improve the threshold level, and the input C / N is dealt with in the weak electric field which causes a noise problem. By controlling the feedback described above, the loop gain of the PLL is controlled, the threshold level is improved, and good image quality can be obtained.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明によるFM復調回路の一実施例を示すブロ
ック図、第2図は帰還増幅器の一例を示す回路図、第3
図はPLLの開ループ利得を示す特性図、第4図はループ
利得制御回路の一例を示すブロック図、第5図はループ
利得制御回路の動作原理図、第6図は帰還増幅器の別の
例を示す回路図である。 2……位相検波器 3……差動増幅回路 4……ループフィルタ 5……電圧制御発振器 6……増幅回路 7……ループ利得制御回路
FIG. 1 is a block diagram showing an embodiment of an FM demodulation circuit according to the present invention, FIG. 2 is a circuit diagram showing an example of a feedback amplifier, and FIG.
Fig. 4 is a characteristic diagram showing the open loop gain of the PLL, Fig. 4 is a block diagram showing an example of the loop gain control circuit, Fig. 5 is an operation principle diagram of the loop gain control circuit, and Fig. 6 is another example of the feedback amplifier. It is a circuit diagram showing. 2 ... Phase detector 3 ... Differential amplification circuit 4 ... Loop filter 5 ... Voltage controlled oscillator 6 ... Amplification circuit 7 ... Loop gain control circuit

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】電圧制御発振器と、復調すべきFM信号と前
記電圧制御発振器からの発振信号とを入力し、両信号の
位相を比較し、その差に応じた信号を出力する位相検波
器と、該検波器の出力を取込み増幅して出力する差動増
幅器と、該差動増幅器からの差動出力の一方を取込みフ
ィルタ処理して前記電圧制御発振器の発振周波数制御電
圧として該電圧制御発振器へ供給するループフィルタ
と、を備え、前記ループフィルタ出力から復調された信
号を取り出すフエースロックドループ方式のFM復調回路
において、 前記差動増幅器からの差動出力の他方を取込みフィルタ
処理して出力するフィルタ回路と、該フィルタ回路の出
力を取込み増幅して出力する増幅回路と、該増幅回路か
らの増幅出力を、前記差動増幅器を構成する定電流源
へ、帰還して復調の帯域特性を制御する帰還回路と、 前記ループフィルタの出力を分岐して取込み、復調すべ
き前記FM信号のC/Nを検出し、該C/Nに対応した制御電圧
を出力するループ利得制御回路と、該ループ利得制御回
路からの制御電圧が或る閾値を越えるとそのことを検出
して前記帰還回路を交流的に短絡する短絡回路と、 を具備したことを特徴とするFM復調回路。
1. A voltage-controlled oscillator, and a phase detector which inputs an FM signal to be demodulated and an oscillation signal from the voltage-controlled oscillator, compares the phases of both signals, and outputs a signal according to the difference. A differential amplifier that takes in and amplifies and outputs the output of the detector, and one of the differential outputs from the differential amplifier is taken in and filtered to the voltage controlled oscillator as an oscillation frequency control voltage of the voltage controlled oscillator. A loop filter for supplying, and a phase-locked loop type FM demodulation circuit for extracting a demodulated signal from the output of the loop filter, in which the other of the differential outputs from the differential amplifier is filtered and output. A circuit, an amplifier circuit that takes in and amplifies and outputs the output of the filter circuit, and an amplified output from the amplifier circuit is fed back to a constant current source that constitutes the differential amplifier. A feedback circuit that controls the band characteristic of demodulation, the output of the loop filter is branched and taken in, the C / N of the FM signal to be demodulated is detected, and a loop gain that outputs a control voltage corresponding to the C / N An FM demodulation circuit comprising: a control circuit; and a short circuit that detects when the control voltage from the loop gain control circuit exceeds a certain threshold value and short-circuits the feedback circuit in an alternating current manner. .
【請求項2】電圧制御発振器と、復調すべきFM信号と前
記電圧制御発振器からの発振信号とを入力し、両信号の
位相を比較し、その差に応じた信号を出力する位相検波
器と、該検波器の出力を取込み増幅して出力する差動増
幅器と、該差動増幅器からの差動出力の一方を取込みフ
ィルタ処理して前記電圧制御発振器の発振周波数制御電
圧として該電圧制御発振器へ供給するループフィルタ
と、を備え、前記ループフィルタ出力から復調された信
号を取り出すフエースロックドループ方式のFM復調回路
において、 前記差動増幅器からの差動出力の他方を取込みフィルタ
処理して出力するフィルタ回路と、該フィルタ回路の出
力を取込み増幅して出力する増幅回路と、該増幅回路か
らの増幅出力を、前記差動増幅器を構成する定電流源
へ、帰還して復調の帯域特性を制御する帰還回路と、 前記ループフィルタの出力を分岐して取込み、復調すべ
き前記FM信号のC/Nを検出し、該C/Nに対応した制御電圧
を出力するループ利得制御回路と、 前記帰還回路を交流的に短絡するための短絡用接地容量
であって、前記ループ利得制御回路からの制御電圧を印
加され、その印加電圧値に依存してその容量値が連続的
に可変する前記短絡用接地容量と、 を具備したことを特徴とするFM復調回路。
2. A voltage-controlled oscillator, and a phase detector which inputs an FM signal to be demodulated and an oscillation signal from the voltage-controlled oscillator, compares the phases of both signals, and outputs a signal according to the difference. A differential amplifier that takes in and amplifies and outputs the output of the detector, and one of the differential outputs from the differential amplifier is taken in and filtered to the voltage controlled oscillator as an oscillation frequency control voltage of the voltage controlled oscillator. A loop filter for supplying, and a phase-locked loop type FM demodulation circuit for extracting a demodulated signal from the output of the loop filter, in which the other of the differential outputs from the differential amplifier is filtered and output. A circuit, an amplifier circuit that takes in and amplifies and outputs the output of the filter circuit, and an amplified output from the amplifier circuit is fed back to a constant current source that constitutes the differential amplifier. A feedback circuit that controls the band characteristic of demodulation, the output of the loop filter is branched and taken in, the C / N of the FM signal to be demodulated is detected, and a loop gain that outputs a control voltage corresponding to the C / N A control circuit and a grounding short-circuit capacitance for AC short-circuiting the feedback circuit, to which a control voltage from the loop gain control circuit is applied, and the capacitance value is continuous depending on the applied voltage value. An FM demodulation circuit, comprising:
【請求項3】特許請求の範囲第1項又は第2項に記載の
FM復調回路において、前記ループ利得制御回路が、当該
FM復調回路で復調されたビデオ信号における水平同期信
号又は垂直同期信号に重畳されている雑音成分を取り出
し検波して、その雑音レベルに対応した電圧を、制御電
圧として出力する回路から成ることを特徴とするFM復調
回路。
3. The method according to claim 1 or 2
In the FM demodulation circuit, the loop gain control circuit
It is composed of a circuit that extracts and detects the noise component superimposed on the horizontal sync signal or vertical sync signal in the video signal demodulated by the FM demodulation circuit and outputs the voltage corresponding to the noise level as a control voltage. FM demodulator circuit.
JP59257574A 1984-12-07 1984-12-07 FM demodulation circuit Expired - Lifetime JPH0752809B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59257574A JPH0752809B2 (en) 1984-12-07 1984-12-07 FM demodulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59257574A JPH0752809B2 (en) 1984-12-07 1984-12-07 FM demodulation circuit

Publications (2)

Publication Number Publication Date
JPS61136308A JPS61136308A (en) 1986-06-24
JPH0752809B2 true JPH0752809B2 (en) 1995-06-05

Family

ID=17308159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59257574A Expired - Lifetime JPH0752809B2 (en) 1984-12-07 1984-12-07 FM demodulation circuit

Country Status (1)

Country Link
JP (1) JPH0752809B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0681314B2 (en) * 1985-01-28 1994-10-12 ソニー株式会社 PLL demodulation circuit
JPH06216655A (en) * 1993-01-13 1994-08-05 Nec Corp Demodulation circuit
JP4543511B2 (en) * 2000-07-10 2010-09-15 パナソニック株式会社 Horizontal PLL circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS524763A (en) * 1975-06-30 1977-01-14 Mitsubishi Electric Corp Phase modulation receiving device
JPS6027480B2 (en) * 1976-11-29 1985-06-28 日本ビクター株式会社 A processing circuit for input angle modulated wave signals in a demodulation circuit for angle modulated wave signals reproduced from a multi-channel disc record.

Also Published As

Publication number Publication date
JPS61136308A (en) 1986-06-24

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