JPH0752826B2 - Delay circuit and its operation method - Google Patents

Description

FIELD OF THE INVENTION The present invention relates generally to signal delay circuits, and more particularly to programmable delay lines that provide selectable and highly accurate time delays to electronic signals.

B. Prior Art In digital signal processing systems, it is often an important point whether or not it is repeatable and can generate a high time delay (increment) of accuracy. For example, automatic inspection equipment used for inspection of VLSI (Very Large Scale Integrated Circuit) logic circuits and memory arrays is required to have picosecond (ps) accuracy and to be able to generate a selectable time delay.

Such an inspection apparatus is used to inspect a chip having input / output (I / O) pins close to or more than 200 to 500. Therefore, such a high-precision signal delay must be generated in a large amount in proportion to a considerable number of I / O pins. Therefore, the circuit that creates such a delay must not only provide a certain degree of accuracy, but also be of a practical and economical size and cost that can be used in large quantities.

U.S. Pat. No. 4,016,511 shows a programmable variable length digital delay circuit. In this circuit, a variable length shift register delay element for receiving a clock is connected by a digitally controllable switch. The delay is controlled by controlling the switch. However, this circuit has the disadvantage that the time delay increment is limited to the rate at which the registers are clocked. Furthermore, this circuit requires relatively complex and expensive switching mechanisms.

U.S. Pat. No. 3,718,822 shows a circuit for changing the transfer rate and order of data. In this circuit, multiple stages are connected in series, each stage having a pair of parallel delay paths. The time delay differs depending on the delay route. The outputs of each pair of delay paths are connected so that the data transmitted through the different paths are recombined in the desired order. The time delay of each path is not to give an adjustable precision delay,
It is selected to change the speed or order of the processed data as needed.

U.S. Pat. No. 3,526,840 shows a drive / timing circuit. This is one in which a plurality of stages are connected in series, and each stage has a pair of parallel paths, and the time delay differs depending on the paths. The first path is the shortest delay path through the gate and the second path is the longer delay path through the monostable multivibrator. With such a configuration, it is impossible to provide a precise delay time as in the present invention.

U.S. Pat. No. 4,737,670 shows a circuit that produces a constant delay between input and output. This delay is not affected even if the gate delay changes due to fluctuation factors such as temperature and power supply voltage. The ring oscillator included in the circuit is formed on the same semiconductor chip as the variable delay circuit. The frequency of the ring oscillator is measured periodically and used to select the appropriate delay. Therefore, if the frequency of the ring oscillator changes, an appropriate variable delay is selected to keep the delay constant. The device of this patent is designed to provide a fixed delay and not the programmable and selectable delay of the present invention.

U.S. Pat. No. 4,450,749 shows a delayed pulse generator circuit that uses a variable delay in one circuit to provide the desired delay.
The variable delay is connected in the feedback loop so that it oscillates during calibration. The oscillating frequency is measured and the delay in the circuit is calculated and compared with the predetermined delay. Circuitry has been added to adjust the variable delay to provide the required delay. Also,
Binary search routines have been proposed that adjust the variable delay to obtain the desired delay. Like the 4737670 above,
This patent also covers a circuit that is calibrated to give an accurate single delay.

C. Problems to be Solved by the Invention An object of the present invention is to provide an improved delay circuit.

It is an object of the present invention to provide a delay circuit that causes a time delay with high accuracy of nanosecond or less.

It is an object of the present invention to provide a delay circuit of the type mentioned above, with which the time delay can be selected.

It is an object of the present invention to provide a delay circuit of the above type which can be implemented in an integrated circuit using relatively low score and readily available components.

It is an object of the present invention to provide a delay circuit of the above type which is easily and quickly calibrated in absorbing internal variations caused by ambient temperature, supply voltage, manufacturing process variables and the like.

D. Means for Solving the Problems The operation method of the delay circuit according to the present invention is improved so as to give a predetermined delay to an electronic signal, and the delay circuit is
Comprising a plurality of delay stages and means for directing an electronic signal to a selected one of the delay stages, the method of operation consists in measuring the signal delay that actually occurs in each of the delay stages, and in the measuring step. Selecting a delay stage to which the electronic signal is directed based on the signal delay provided.

The delay circuit according to the present invention imparts a predetermined delay to an electronic signal, and a plurality of delay stages, means for directing the electronic signal to a selected stage among the delay stages, and the delay stages actually occur. It includes means for measuring the signal delay and means for selecting the delay stage to which the electronic signal is sent based on the actual signal delay obtained in the measuring step.

E. Example In FIG. 1, circuit 20 provides a selectable, highly accurate time delay to the digital / pulse input electronic signal with reference to the path with the minimum delay. Hereinafter, this time delay is referred to as "additional delay".

The circuit 20 comprises five stages 22, 24, 26, 28 connected in series,
Including 30. Each stage includes a demultiplexer (DEMUX) 22A to 30A, a first path 22B to 30B having a minimum delay, and a second path 22C to 3 having another delay added to the minimum delay.
There are 0C and logical OR gates 22D to 30D. As explained below, the "C" routes 22C to 30C are the corresponding "B" routes.
22B to 30B are connected in parallel between the DEMUX and the OR gate with a pair sandwiching them.

DEMUX 22A receives a digital clock input signal CLOCK and is connected to direct this signal to a selected path, either path 22B or 22C. The logical OR gate 22D is
Selected to receive output from each of paths 22B, 22C. DEMUX 24A receives the output of OR gate 22D and
Connected to either path 24B or 24C to the selected path. Similarly, the DEMUX 26A, 28A, and 30A are connected so as to receive the output of the OR gate from the preceding stage and direct the signal to any one of the succeeding routes.

Output DEMUX 32 is connected to receive and drive the output signal from OR gate 30D. Microprocessor 34
Has inputs connected to receive data from at least two period counters (FIGS. 3 and 5), and outputs have DEMUX 2 for controlling DEMUX in the manner described below.
Connected to each of 2A to 30A and 32.

FIG. 2 shows an embodiment of the delay stage 22. The DEMUX 22A is composed of four logical OR gates 36, 38, 40 and 42. Gate 36
Input is connected to receive the clock signal CLOCK,
The inverting output is connected to the first input of each of the gates 40, 42. The input of the gate 38 is connected to receive the control signal C1 from the microprocessor 34, the inverting output is connected to the second input of the gate 40, and the non-inverting output is connected to the second input of the gate 42. It

Path 22B consists of one logic gate 44 whose input is
It is connected to the inverting output of gate 40 and the output is connected to the input of gate 22D. Path 22C is a series-connected X logic O
It consists of R gates 46 to 46X, the input of the first gate is
Connected to the inverting output of gate 42. The output of the gate 46X is connected in parallel to the respective inputs of the Y parallel-connected gates 48 to 48Y, and is also connected to the second input of the gate 22D.

The delay stages 24 to 30 on the downstream side of the delay path have the same configuration as the embodiment of the delay stage 22 shown and described in FIG. 2, and the series and parallel connection type gates X and Y of the “C” delay path are respectively provided. Only the number is different. The gate configuration of each "C" path is selected to obtain the desired signal delay by the method described below.

In operation, the delay path 22B has a typical time delay d, as illustrated by the notation used for the "B" and "C" delay paths of stage 22.
(N) is provided. Delay path 22C is configured to provide a time delay that is approximately equal to the sum of the delay d (n) and 2 ⁿ x Δ (Δ2 ⁿ ) of signal path 22B. Where Δ is equal to the minimum value (physically realizable delay increment) and n is
It is a power of 2 selected according to a predetermined maximum delay, and is generally a value equal to the number of delay stages of the circuit 20 (except stages such as stages 28 and 30 where the delay is 20 × Δ).

In an embodiment of the present invention, each "C" delay path 22C-28C of delay circuit 20 includes an additional delay equal to a power of 2 times the Δ delay, and each "C" delay path is in ascending binary order relative to each other. / Arranged in descending order. For convenience of explaining the present invention, n = 3 stages (stage 2
2), n = 2 stage (stage 24), n = 1 stage (stage 26), n =
It includes four stages of 0 (stage 28) and a stage of n = 0 (stage 30) added to improve the accuracy of the total delay amount by the method described below. The resulting "C" delay path is commonly referred to in the art as a binary ladder.

Looking at the delay of each stage, the delay path 22C is
Includes a delay of 2 ³ x Δ (Δ 2 ³ ). Delay circuit 24C is route 24B
Including the Δ2 ² of delay with respect. Similarly, delay paths 26C, 28
C and 30C are Δ for the corresponding “B” delay path.
2 ^1, Δ2 ^0, including the delay of Δ'2 ^0. The delay added to the "C" route (relative to the "B" route) is
It is provided through a predetermined gate (X / Y series / parallel connection gates) of the "B" and "C" paths.

For convenience of describing the present invention, a logical OR gate, such as gates 44 and 46, here is used to drive about 160 when driving a single output load.
It shall indicate a picosecond (ps) time delay. In that case,
Each of the series-connected gates such as the gate 46 lengthens the delay time of the signal passing through the “C” path by about 160 ps, and gives a large delay amount. To get a smaller delay amount,
Provide a parallel connection gate such as 48. The delay time of the signal passing through this path is assumed to be about 20 ps.

The gate delay appears to be a function of the gate structure, 160 ps (series) and 20 ps shown to illustrate the operation of the invention.
It is possible that it will change significantly from (parallel).

Furthermore, this is the basis of the present invention, but since there is an uncontrollable variable element in the structure and connection of the logic gate, any logic gate has an accurate delay (here, it is a serial connection gate). 160ps, 20ps with parallel connection gate)
Is unlikely to indicate. As is well known in the art, external conditions, especially variations in ambient temperature and power supply voltage, can also cause changes in gate delay.

Returning to the description of the operation of the present invention, as described above, the circuit 20
= 2 Apart from delay and four delay stages 22, 24, 26, 28 is a minimum of ^{0 Δ}
It is assumed that the configuration has a delay stage 30 that is Also,
It is assumed that a minimum delay Δ of 20 ps is desirable. Delay time 160p
s can be easily implemented with a single series connected gate or multiple parallel connected gates.

With the above parameters, the "B" paths 22B-30B will have typical delays d (3) = d (2) = d (1) = d (0) =
Selected to show d '(0) = 160 ps (approximate).
Such delays are set by selecting the number of gates and connections for each "B" path. The gate of the path 22C is delayed is connected so as to be 160ps + 2 ³ x20ps = 320ps. Route 24C is configured to have a time delay of 160ps + 2 ² x20ps = 240ps, and route 26C, delay is 160ps + 2 ¹ x20ps = 200.
configured to be ps. Similarly, the path 28C, 30C are each configured to minimum delay is 160ps + 2 ⁰ x20ps = 180ps.

As previously mentioned, each delay path cannot be configured to achieve the exact delay desired due to variations in the delay of the individual gates. However, by combining the theoretical calculation and the measured value, each of the "B" and "C" delay paths is configured to be close to the delay that is practically desirable.

Table 1 shows typical delays d from each "C" delay stage to "B" stage.
Subtract (n) = 160 ps to show the theoretical additional delay obtained on paths 22C to 30C.

Table 1 Path theoretical additional delay 22C 2 ³ x20ps = 160ps 24C 2 ² x20ps = 80ps 26C 2 ¹ x20ps = 40ps 28C 2 ⁰ x20ps = 20ps 30C 2 ⁰ x20ps = 20ps 320ps = maximum additional delay As can be seen from the above consideration, By appropriately controlling the DEMUX 22A to 30A by the microprocessor 34 by the method described below, the delay circuit 20 has an additional delay of 20 ps to 320 ps.
It is possible to generate pulses in the range of (increase by 20ps). The delay thus selected or the additional delay is
This is the delay based on the pulse with the minimum delay that propagates only the path “B”.

However, while circuit 20 allows additional delay in very fine increments of about 20 ps, no gate in circuit 20 can be expected to exhibit a theoretically correct delay. Therefore, each of the Δ delay paths 22C to 30C changes slightly from the theoretical delay shown in Table 1.

A method of more accurately calibrating the time delay selectable by the delay circuit 20 will be described below with reference to FIGS. 3 and 4.

In FIG. 3, the calibration circuit 60 calibrates the operation of the delay circuit 20.
This allows the actual added delay to be measured for each of paths 22C-30C. The calibration circuit 60 includes a theoretical OR gate 62, the first input of which is connected to receive the clock signal CLOCK and the output of which is connected to the input of the delay circuit 20. The output of the delay circuit 20 is an optional low precision delay circuit 64 and a first logical OR gate 66.
Connected to both inputs. The output of the low precision delay circuit 64 is
If a much longer delay, which is a multiple of the input clock of the present invention, is required, it is used by a system (not shown) such as an integrated circuit tester.

The second input of the gate 66 receives the calibration enable signal CALENABLE, the non-inverting output is connected to the period counter 68, and the inverting output returns to the second input of the gate 62. Thus, a feedback loop is formed between the input and output of the delay circuit 20 via the gates 66 and 62.

The low precision delay circuit 64 is a circuit that adds a low precision time delay to the relatively precise delay provided by the delay circuit 20. Various configurations of this circuit are known to those skilled in the art. The cycle counter 68 is a conventional cycle counter, and preferably has an accuracy up to about 1/100 of the Δ delay selected in the “C” signal path of the delay circuit 20. Such period counters include Hewlett Packard frequency counters, model HP5
There is a 385A. This has an accuracy of about 0.01ps.

In operation, the calibration enable signal CAL ENABLE is used when the actual delay (relative to the theoretical or typical value) of the signal path of the delay circuit 20 needs to be measured, ie, the minimum delay sum of the “B” signal path and “C”. "Selected when both the delay (including the added delay) of each of the signal paths needs to be measured, which enables gate 66. Such calibration may be performed, for example, after first powering up the delay circuit 20 and thereafter periodically during operation of the circuit.

When both the gate 66 and the period counter 68 are enabled, the period counter accurately counts the periods of the digital pulses successively input to it. The microprocessor 34
Upon initial start-up, controlling DEMUX 22A-30A selects the minimum delay path or "B" signal path for each of stages 22-30. Thus the cycle counter 68
The actual minimum delay of the delay circuit 20 is measured. After this minimum delay is detected, the microprocessor 34 will detect the same DEMUX
To control the relatively long delay or “C” signal path of the delay circuit one at a time.
The "B" signal path is selected by the remaining DEMUX. Therefore, when the "C" signal path is selected,
The actual additional delay for the minimum signal delay is simply determined by subtracting the delay of the selected "C" signal path from the "B" signal path with the minimum delay. This calculation is preferably done by the microprocessor 34. Signal path "C" (22C
To 30C) are selected sequentially, the additional delays that actually occur in these paths are known.

Table 2 shows representative values of the additional delays actually measured on paths 22C to 30C. Such additional delay is obtained using the calibration circuit of FIG. 3 in the manner described above.

Table 2 Delay stage Theoretical additional delay Actual additional delay 22C 160ps 152.5ps 24C 80ps 85.8ps 26C 40ps 36.3ps 28C 20ps 17.2ps 30C 20ps 16.7ps Fig. 4A shows the additional delay actually measured on paths 22C to 30C. Shows a method of determining a signal path through the delay stages 22 to 30. This gives the additional delay closest to the desired delay DD. First, an outline of this method will be described, and then the circuit 20 for giving theoretical and actual additional delays shown in Table 2 will be described as an example.

In general, the method of the present invention allows the selection of a desired delay based on theoretically possible delays (ie, powers of 2 times the additional delay). However, since the actual measured delay at the various signal stages is different from the theoretical delay, the additional delay is generated based on the actual delay and its error is the smallest possible error for the required delay. Is.

Generally, starting from the largest additional delay stage and proceeding in descending order,
Add the actual delay to the previously selected sum of delays. If the error with respect to the required delay is reduced by selecting the actual delay, then that delay stage is selected for generating the additional delay. If the error of the additional delay with respect to the required delay becomes large as a result of selecting the actual delay, that delay is not selected. The actual additional delay, after all the actual delays have been examined and selected as described above, has the smallest possible error relative to the theoretical required delay.

In this method, a bit storage array B having a flag bit for each of the (n + 1) delay stages of circuit 20.
It is assumed that (N) (1x5 array) can be used. The error between the required delay DD and the calculated delay when implementing this method is shown as ERR. The method is typically implemented as a computer program within microprocessor 34.

Table 3 shows the variables used in the method of the present invention.

Table 3 DD-Delay required (seconds) B (n) -bit flag for an array of length n BF-bit flag counter ERR-delay error (seconds) MIN ERR-minimum error (seconds) POS ERR-positive error ( S) N-cycle counter Δ2 ⁿ -actual additional delay in ²ⁿ stages This method first sets the cycle counter N to the number of delay stages in the delay line minus one and the minimum error
This is done by setting MIN ERR to the actual added delay Δ 2 ⁿ of maximum delay.

The required delay DD is input and the positive error POS ERR is set equal to the required delay DD. Additional delay Δ 2 ⁿ is positive error POS ERR
Then, the error ERR is obtained.

A check of the delay error ERR determines if it is greater than zero. First, the operation "greater than 0" will be described.

If the delay error ERR is greater than 0, then n delay stages B
The bit flag associated with (n) is set equal to one. This indicates that an additional delay (“C” signal path) is used and that the positive error POS ERR is set equal to the error ERR.

Examination of the error ERR determines if it is less than the minimum error MIN ERR. If the error ERR is less than the minimum error MIN ERR, then MIN ERR is set equal to ERR and the bit flag counter BF is set to -1. This indicates that the minimum error has occurred when the error ERR is positive.
If the error ERR is greater than the minimum error MIN ERR, then the above steps are not performed. Then it is checked whether N is zero. If N is not 0, N is decremented and the loop is repeated.

Next, when the delay error ERR is smaller than 0 and the additional delay is increased, the delay error ERR increases in the negative direction. Therefore, bit flag B (N) is set to 0 and the current additional delay is not selected (ie, the current "C" delay stage is not selected). Delay error [ERR] is the minimum error MIN
It is determined whether it is less than ERR. If so, the minimum error MIN ERR is set to the value of the delay error ERR and the bit flag counter BF is set to N. This means that for a negative delay error ERR, a minimum error MIN ERR has occurred,
It also shows in which additional delay stage n this occurred. If the delay error [ERR] is not less than the minimum error MIN ERR, then the above steps are not executed. When N is not 0, N is decremented and the loop is repeated.

The above process is repeated as long as N is non-zero (ie greater than zero). When N = 0, the "C" signal path indicated by bit flag B (N) provides a minimum positive error for the required delay. However, the minimum error may occur when the delay error is negative.

In Figure 4B, it is determined whether the bit flag counter BF is equal to -1. If they are equal, this indicates that a minimum error has occurred for a positive delay error,
The "C" signal path indicated by flag B (N) provides the optimum differential delay. The program ends here.

If the bit flag counter BF is not equal to -1,
This means that a minimum error has occurred for negative delay errors,
And N = BF during the loop cycle. Therefore, all delays selected when N> BF remain in the selected state. The delay (BF) is also selected by setting B (BF) to 1. All additional delays with N <BF are deselected. This last step is
It is shown in the bottom loop of Figure 4B. When B (BF) is set to 1, the bit flag counter BF is decremented and it is determined whether it is equal to -1. If not, B (BF) is set to 0 (ie, the additional delay of the "C" stage is deselected) and the bottom loop is repeated. The program ends when it is detected that the bit flag counter BF is equal to -1.

When the process shown in FIGS. 4A and 4B is completed, an optimum path is selected for the delay circuit 20 (FIG. 1), and "C" is added to each delay stage having the bit flag array B (N) = 1. "A route is selected. As can be seen from the examples given below, the above method provides additional delay based on the actually measured Δ delay (closest to the required delay DD) for each “C” path. It will also be appreciated that the routes calculated in this way are different from those calculated on the basis of theoretical Δ delay.

The above process will be described below with respect to two other examples. The first example has a required delay DD of 240 ps and the other example has 100 ps.

Example 1 Table 4 summarizes the values obtained by performing the above process with a required delay DD of 240 ps. The process starts by initializing the cycle counter N to the number of stages of the circuit 20 minus one (N = 5-1 = 4). The minimum error MIN ERR is set to the maximum value of the actual delay (MIN E
RR = Δ2 ³ = 152.5ps --- All actual delays are shown in Table 2 above.
Taken from).

When N = 4, the positive error POS ERR is set to the required delay DD (POS ERR = 240ps). The actual delay Δ2 ⁿ is the positive error PO
The error ERR is obtained by subtracting from S ERR (ERR = 240-152.
5 = 87.5ps). Since the error ERR is greater than 0, the bit flag B (4) is set to 1 and the positive error POS ERR is set equal to ERR (POS ERR = 87.5ps). The error ERR is smaller than the minimum error MIN ERR (87.5 <152.5), so MIN ER
R is set equal to ERR (MIN ERR = 87.5ps) and the bit flag counter BF is set to -1.

When N is decremented and N = 3, ERR = POS ERR−Δ
A ^{2 2 (ERR = 87.5-85.8 = 1.7} ). Since ERR is greater than 0, B (3) is set to 1 and POS ERR = ERR1.7
Becomes Since ERR <MIN ERR (1.7 <87.5), MIN ERR is
Set equal to ERR, bit flag counter BF
Is set to -1 (MIN ERR = 1.7, BF = -1).

When N is decremented N = 2, the ^{ERR = POS ERR-Δ2 1 (} ERR = 1.7-36.3 = -34.6). Since ERR is less than 0, B (2) is set to 0. Absolute error abs (ERR)
Is not less than MIN ERR (ie abs [−34.6]
Is not less than 1.7), N is decremented and the loop is repeated. POS ERR, MIN ERR, and BF remain unchanged.

When N is decremented N = 1, the ^{ERR = POS EER-Δ2 0 (} ERR = 1.7-17-2 = -15.5). Since ERR is less than 0, B (2) is set to 0. abs (ERR) is MIN
Not less than ERR (ie abs [-15.5] is 1.7
N is decremented and the loop is repeated. POS ERR, MIN ERR, and BF remain unchanged.

When N is decremented and N = 0, ERR = POS ERR−Δ2 ⁰ ′
(ERR = 1.7-16.2 = -15). Since ERR is less than 0, B (1) is set to 0. abs (ERR) is MIN ER
Since it is not less than R (ie abs [-15] is not less than 1.7), N is decremented and the loop is repeated. PO
S ERR, MIN ERR, and BF remain unchanged.

Since N is now decremented to 0, the process continues as in Figure 4B. Since the bit flag counter BF is equal to -1, the process ends.

When the contents of the bit flag array B (n) are examined and compared with the circuit 20 of FIG. 1, the uppermost stage (delay stage 22) and the second uppermost stage (delay stage 24) of the circuit 20 are shown. You can see that the "C" route is selected for. In fact, by selecting the “C” path, the additional delay is 23 times the minimum delay of the “B” path.
It will be 8.3ps (152.5 + 85.8).

Example 2 In this example, 100 ps is selected as the required delay. Again, N is initialized to 4 and MIN ERR is initialized to 152.5. The steps shown in FIG. 4A are performed as in Example 1 above, and the results are summarized in Table 5.

In light of the results in Table 5 in the process of FIG. 4B, it can be seen that when the bit flag counter BF is first checked, it is equal to 0 rather than -1. Therefore, if the process continues as in Figure 4B, B (BF) =
B (0) is set to 1. The bit flag counter BF is decremented from 0 to -1, and the process ends.

Examining the contents of the bit flag array B (N), each flag is set to 1 for both the second to the most significant delay and the predetermined least significant delay. Therefore, the “C” path of the circuit 20 of FIG. 1 shown here is Δ2 ²
A "C" path (85.8ps) and Delta] 2 ⁰ of "C" path (16.7ps), the total addition delay becomes 102.5Ps. As can be seen, this is the optimal signal path to get the required delay of 100ps. The only other route close to this was directed 1
The 6.7 ps path turns into a lower first delay 17.2 ps path, which is longer than the desired 100 ps.

As has been made clear by the present invention, by adding a plurality of lower delays (lower stages 28C and 30C of delay circuit 20 in this example), the accuracy with which the required delay is obtained is greatly increased. Actually, assuming that the actually measured delay of each delay stage randomly changes around the theoretically expected delay, by adding a plurality of lower delay stages, nanoseconds within the above range can be obtained. An unexpected effect is obtained in reducing the error that causes the following delay.

In FIG. 5, the loop oscillator circuit 70 is incorporated in the integrated circuit chip 72. Chip 72 consists of delay circuit 20 and calibration circuit 60
Also support. The loop oscillator circuit 70 is configured, for example, by adding a feedback path and a connection line to the period counter 74 to a serially connected logic gate.

In operation, the period of the loop oscillator circuit 70 is
When the logic circuit on 72 is first activated, the cycle counter 74
Measured at. At about the same time the loop oscillator frequency is measured in this manner, delay circuit 20 is initially calibrated as described above. The frequency of loop circuit 70 is then periodically monitored as chip portion 72 continues to operate, producing heat and eventually reaching operating temperature. The loop circuit 70 is a delay circuit
Adjacent to 20 and combined to some extent in a similar fashion, changes in the signal period appearing in loop circuit 70 are considered to be nearly identical to similar changes appearing in delay circuit 20.
Therefore the scaling factor is easily determined,
Changes in gate delay can be reverted to the gate delay measured at start-up (or initial calibration).

According to the present invention, the scaling factor determined by monitoring the frequency of the loop oscillator circuit 70 is
Used to scale the Δ delay measured at each stage of delay circuit 20 during the calibration process described above. Δ of delay circuit 20
This scaling of the delay is preferably done in the microprocessor 34 and its execution time is significantly reduced compared to the time to complete the recalibration as described above.

Table 6 shows the scaling of the measured Δ delay with the scaling factor A selected to compensate for the gate delay.

Table 6 delta scaling ^{Δ2 0 'AxΔ2 0' Δ2 0} AxΔ2 0 Δ2 1 AxΔ2 1 measurements delta delay of the delay ··· ····· Δ2 ⁿ AxΔ2 ⁿ Table 6, a simple linear measured additional delay By multiplication, it can be seen that the scaling factor can be applied easily and quickly.

From here, a programmable delay circuit is provided to generate a time delay in the sub-nanosecond range. In the illustrated embodiment, the minimum delay is determined by the propagation delay of the digital gate, which varies in binary increments. However, it will be appreciated that the invention is not so limited. The delay can be provided by other signal delay means such as conventional delay lines, and need not be provided in the binary ladder format.

The delay produced by the present invention is based on the delay path actually measured in the circuit, as opposed to the theoretically calculated delay. Accordingly, the present invention provides an apparatus for producing highly accurate and highly precise delays with programmable increments. A method of calibrating a delay circuit and selecting a corresponding delay path based on a measured delay value is provided. Also provided is a method of scaling the measured delay with respect to changes due to changes in heat, power supply voltage, and the like. The present invention is particularly suitable for a semiconductor chip inspection machine which requires a large number of highly selectable time delays.

F. Effects of the Invention The present invention provides a programmable delay line that provides a selectable, highly accurate time delay for an electronic signal.

[Brief description of drawings]

FIG. 1 is a block diagram of a delay circuit according to the present invention. FIG. 2 is a schematic diagram showing means for implementing the delay stage of the circuit of FIG. 1 using conventional digital logic circuitry. FIG. 3 is a block diagram showing means for calibrating the delay circuit of FIG. 4A and 4B are flow charts showing the process of operating the delay circuit of FIG. 1 to obtain a highly accurate delay. FIG. 5 is a block diagram showing means for compensating the operation of the delay circuit of FIG. 1 and absorbing fluctuation factors such as heat and power supply voltage.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Dale Eugene Hofmann, Stormveil, New York, United States, 404 A, Boxx 404, Blueberry Lane (no street number) (72) Inventor, Daniel Edwards Scogrand, Watspinger, New York, United States No Falls, North Mission Road (No Address) (72) Inventor Dane Ky Young 36 Hamlets Court, Watspingers Falls, New York, USA

Claims (4)

[Claims] 1. A first signal delay path having a reference delay amount, and a delay amount equal to a sum of the reference delay amount and an additional delay amount approximately equal to a power of 2 times a predetermined minimum delay amount. A method for providing a desired delay amount to an electronic signal by operating a programmable delay circuit having a plurality of signal delay stages configured with two signal delay paths, wherein the plurality of signal delay stages are At least two signal delay stages including second signal delay paths whose power numbers are different from each other.
And a step of measuring a total delay amount passing through all of the first signal delay paths; a step of measuring a delay amount passing through each of the second signal delay paths; The second based on the measurement result of the measurement step.
Calculating an actual additional delay amount through each of the signal delay paths, and determining which combination of the second signal delay paths of the delay stages provides the total additional delay amount that is closest to the desired delay amount. And directing the electronic signal to the combination of the second signal delay paths selected in the determining step. Wherein at least two stages of the delay stage includes a second signal delay path having a 2 ⁰ times the amount of delay of the minimum delay amount,
The method of claim 1. 3. A delay circuit for giving a desired delay amount to an electronic signal, the first signal delay path having a reference delay amount, and the reference delay amount and a predetermined minimum delay amount being approximated to a power of two. At least a signal delay stage including each of the second signal delay paths having a delay amount equal to the sum of the additional delay amounts that are equal to each other and including the second signal delay routes having different powers of 2 from each other. A plurality of signal delay stages having two stages, means for measuring a total delay amount passing through all the first signal delay paths, means for measuring a delay amount passing through each of the second signal delay paths, Which combination of the means for calculating the actual amount of additional delay passing through each of the second signal delay paths based on the measurement results of the two measuring means, and the combination of the second signal delay paths of the delay stages with the desired delay Determine whether to give the total amount of additional delay closest to the amount Stage and said means for directing said electronic signals on a combination of the second signal delay path selected by determining means, become more delay circuits. Wherein at least two stages of the delay stage includes a second signal delay path having a 2 ⁰ times the amount of delay of the minimum delay amount,
The delay circuit according to claim 3.