JPH0752852B2 - Timing control circuit for phase locked loop - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing control circuit for a phase locked loop suitable for transferring serial data to the phase locked loop, and more particularly to a timing for a phase locked loop which facilitates initial setting of the phase locked loop. Regarding the control circuit.

[0002]

2. Description of the Related Art As a timing control circuit for such a phase-locked loop, a circuit shown in FIG. 1 has been proposed. That is, in FIG. 1, 1 is an input terminal to which an up / down signal is supplied, 2 is an up / down controller, 3 is an up / down counter, 4 is an input terminal to which an up / down clock signal is supplied, 5 is a shift register,
6 is an input terminal to which a latch clock signal is supplied, 7 is an AND circuit, 8 is an input terminal to which a serial data signal is supplied, and 9 is an input terminal to which a shift clock signal is supplied.

In the normal mode, the serial data from the input terminal 8 is taken into the shift register 5 by the clock signal from the input terminal 9 and latched by the up / down counter 3 by the clock signal from the input terminal 6, but the up / down counter 3 In the mode, when the up / down signal Sa supplied to the input terminal 1 changes from “0” to “1” as shown in A of FIG. 2, the up / down controller 2 outputs the signal Sb as shown in B of FIG. Up / down counter 3
Is transferred to the shift register 5. The up-down counter 3 is placed in the up mode by the signal Sd shown in FIG. 2D from the up-down controller 2, and at the same time, the AND circuit 7 is sent by the signal Sc shown in FIG. 2C from the up-down controller 2. The gate of is opened, and the output of the AND circuit 7 returns the contents of the shift register 5 to the up / down counter 3 again. Then, the up / down clock signal S from the input terminal 4 as shown in E of FIG.
e is accepted, and the content of the up / down counter 3 is changed.

[0004]

By the way, in the case of the conventional circuit having the configuration as shown in FIG. 1, the lines of the input terminals 6, 8 and 9 are used for serial data transfer, and the input terminal is used for controlling the up / down counter 3. Since the lines 1 and 4 are used, there is a drawback that the line becomes complicated.

In view of the above, the present invention provides a timing control circuit for a phase locked loop capable of saving the line by controlling an up / down counter using a serial data transfer line.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention is applied to a phase locked loop (PLL) used in a channel selection section of a synthesizer receiver, for example, as shown in FIGS.
It will be described in detail based on.

FIG. 3 shows the entire structure of this embodiment. In FIG. 3, reference numeral 10 denotes an input terminal to which a frequency-divided output obtained by dividing the voltage controlled oscillator of the PLL circuit by a prescaler is supplied, which is not shown, 11 is, for example, FM / TV input 18
Bit, programmable divider with 16 bits for AM input, 12 is a multiplexer,
13 is an 18-bit processing up / down counter, 14 is a 20-bit processing shift register, 15 is a 19-bit processing latch circuit, 16 is a 14-bit programmable reference frequency divider, and 17 is a standard 4. 5 MH
z is a reference oscillator capable of guaranteeing 100 kHz to 10 MHz, 18 is a phase comparator for comparing the phases of the output signals of the frequency dividers 11 and 16, and 19 is a timing controller for generating various timing signals. Therefore, the timing controller 19 has a CLK terminal (clock input terminal for 20-bit serial data input / clock input terminal for data up / down), LAT terminal (latch signal input terminal for shift register input data / up / down mode). Select terminal) and DIN terminal (data input terminal also up /
Down terminals), and control signals corresponding to the respective control signal input terminals 20, 21 and 22 are supplied to each of these terminals from a microcomputer (not shown).

Reference numeral 23 is a frequency divider having an N value of 12, for example, and generates a system clock at its output terminal 24.
Reference numerals 25 and 26 are tri-state buffers, and when the control signal applied to the control signal input terminal 27 is "1", the output of the phase comparator 18 is set to 2 independent in the normal operation mode.
Send to two equivalent output terminals 28 and 29, but "0"
In this case, the output terminals 28 and 29 are forcibly made to have a high impedance, which enables various applications such as combination with the analog AFC and intermittent tuning. The bit-processed values of the circuits described above can be arbitrarily changed according to the number of bits of data to be handled.

In this embodiment, for example, a binary code composed of 20 bits as shown in FIGS. 4 and 5 is used. That is, FIG. 4 shows control input data of the reference frequency divider 16 and the like, which should be called initial state setting data, which must be input at the time of power-on or band switching.

In FIG. 4, R _{0 to} R ₁₃ denote R ₀ by LSB.
Represents the value of the frequency division number given to the reference frequency divider 16 by these 14 bits. PI ₁ , PI
₂ is for specifying signal input terminal, programmable frequency divider 1
Although not shown, three input terminals for AM, FM, and TV are prepared on the input side of 1 independently, and these terminals are designated by a combination of 2 bits of PI ₁ and PI _2. For example, when (PI ₁ , PI ₂ ) is (1, 0) AM, (0, 1) FM, (1, 1)
At that time, each signal input terminal of the TV is designated. A and B are for prescaler control and unlock signal output,
When T ₁ is "0", the switch 30 is connected to the contact a side, and the values of A and B are directly output to the terminals 31 and 32, respectively. Although not shown, these signals can be used for various purposes such as frequency division ratio switching of the prescaler of the PLL circuit, constant switching of the low-pass filter, and band switching signal. The division ratio of the prescaler is switched by a combination of 2 bits of A and B. For example, (A, B) is (0, 0).
When 1/1, 1/2 when (1,0), 1 when (0,1)
When it is / 4, (1, 1), it is switched to 1/8. See also T ₁
Is "1", the switch 30 is switched to the contact b side, and the locked / unlocked state of the phase comparator 18 is output to the terminal 32. For example, when the terminal 32 is "1", unlocked,
When it is "0", it represents the locked state. Therefore, it can be used as a signal for muting. At this time, B data is output to the terminal 31. C is a code that determines the latching direction of the input data. For example, when C is "0", the input data is fetched by the reference frequency divider 16 and when C is "1", it is fetched by the programmable frequency divider 11. , Which handles control input data of the reference frequency divider 16 and the like, is "0" in this case.

Further, FIG. 5 shows data for determining the frequency division ratio of the programmable frequency divider 11. In the figure, N
_{0 to} N ₁₇ are binary values in which N ₀ is the LSB.
The value of the frequency division number given to the programmable frequency divider 11 is represented by 8 bits. The actual frequency division number is P mentioned above.
It depends on which terminal is selected as a signal input depending on the combination of I ₁ and PI ₂ , and for example AM, FM and T
When the signal input terminals for V are selected, the range of frequency division numbers is 4 to 65, 537, 16 to 262, 151 and 32 to 524, 302, respectively. T ₂ is used for selecting the test mode and is always set to “0” in the normal operating state where no test is performed. C is a code for determining the latching direction of the input data, which is "1" in this case.

Next, regarding the method of inputting the control signal, in this embodiment, there are two modes of the data fetching mode (normal mode) and the up / down mode, and the signal input method is slightly different between the two modes.

That is, the data acquisition mode is selected when the LAT terminal of the timing controller 19 is set to the "0" state as shown in FIG. The data supplied from the microcomputer to the DIN terminal of the timing controller 19 as shown in B of FIG. 6 is also supplied from the microcomputer to the CLK terminal of the timing controller 19 as shown in C of FIG. 20 at the start of 1 bit
It is taken into the bit shift register 14. After sending the data to the shift register 14, the LA of the controller 19
Data is latched by setting the T terminal to the "1" state. At this time, depending on the final bit of the data, that is, the state of C in FIGS. 4 and 5, the input data is the programmable frequency divider 1
1 or the reference frequency divider 16. That is, if C is "1", it is the input data for the programmable frequency divider 11, so the latched data is taken into the programmable frequency divider 11, while if C is "0", the reference frequency divider is used. Since it is the control input data of the frequency divider 16 and the like, the latched data is fetched in the reference frequency divider 16.

In actual use, the control input data from the controller 19 to the reference frequency divider 16 as shown in FIG.
After outputting and fetching a bit signal, all internal states are set by sending a 20-bit signal which is data for setting the programmable frequency divider 11 as shown in FIG. That is, in the initial setting, it is necessary to input a total of 40 bits of data in two steps, but if the reception frequency is changed within the same band, it is only necessary to change the data of 20 bits.

Then, the LAT terminal of the controller 19 is set to "1" as shown in FIG.
It goes into down mode. In this mode, the frequency division number of the programmable frequency divider 11 can be increased or decreased by using the terminal 33 for data acquisition. That is, L of the controller 19
When the AT terminal becomes "1", the data is shifted to the shift register 14
At the same time, it is changed to the up / down mode, and the data “1”, which is supplied from the microcomputer to the DIN terminal of the controller 19 as shown in FIG. 7B,
In response to "0", the content of the up / down counter 13 is incremented or decremented by 1 at the rising edge of the clock (C in FIG. 7) of the CLK terminal of the controller 19.

When the LAT terminal of the controller 19 becomes "0", the mode returns to the normal mode, and at the same time, the contents of the up / down counter 13 are reversely loaded into the shift register 14. The loaded contents of the shift register 14 can be taken out from the terminal 33 by inputting a clock to the CLK terminal of the controller 19, which makes it possible to know the current frequency division number of the programmable frequency divider 11. it can. Since the contents of the shift register 14 are continuously output from the terminal 33, this is again output to the controller 19
It is also possible to confirm the transmission data from the controller 19 by returning to.

FIG. 8 shows an example of a concrete circuit configuration of the timing controller 19. In the figure, the control signal input terminal 20 is connected to a NOR circuit 41 via an inverter 40.
And 42, the control signal input terminal 21 is connected to the other input terminal of the NOR circuit 41, and is connected to the other input terminal of the NOR circuit 42 via the inverter 43. The shift register 14 and the up / down counter 1 are connected to the output terminals of the NOR circuits 41 and 42, respectively.
3 (both FIG. 3) connected to output terminals 44 and 45
Is derived. The control signal input terminal 21 is connected to the input terminal I of the delay circuit, for example, the flip-flop circuit 46, and is also connected to one input terminal of the AND circuit 47.
The output terminal Q of the flip-flop circuit 46 is connected to the trigger terminal T of the flip-flop circuit 48, and the inverting output terminal Q is connected to the other input terminal of the AND circuit 47.

The control signal input terminal 22 is connected to the set terminal S of the flip-flop circuit 48 and to the reset terminal R of the flip-flop circuit 48 via the inverter 49. The inverting output terminal Q (inversion) of the flip-flop circuit 48 is connected to the input terminal I of the delay circuit, for example, the flip-flop circuit 50, and the flip-flop circuit 5
The output terminal Q of 0 is connected to the output terminal I of the delay circuit, for example, the flip-flop circuit 51. Then, the output terminal Q of the flip-flop circuit 50 and the flip-flop circuit 5
The inverted output terminal Q (inverted) of 1 is connected to each input terminal of the AND circuit 52, and the inverted output terminal Q (inverted) of the flip-flop circuit 50 and the output terminal Q of the flip-flop circuit 51 are respectively connected to the AND circuit 53. It is connected to the input terminal, and the output terminals of the AND circuits 52 and 53 are connected to the input terminals of the NOR circuit 54, respectively.

The output terminal Q of the flip-flop circuit 51 is connected to the input terminal I of the delay circuit, for example, the flip-flop circuit 55, and the output terminal Q of the flip-flop circuit 55 is connected to the input terminal I of the delay circuit, for example, the flip-flop circuit 56. Connected. And the flip-flop circuit 55
Output terminal Q of the flip-flop circuit 56 and the inverting output terminal Q (inversion) of the flip-flop circuit 56 are connected to the respective input terminals of the AND circuit 57, and the inverting output terminal Q (inversion) of the flip-flop circuit 55 and the output terminal Q of the flip-flop circuit 56. Is connected to each input terminal of the AND circuit 58, and each output terminal of the AND circuits 57 and 58 and the output terminal of the AND circuit 47 are connected to each input terminal of the NOR circuit 59. And the NOR circuit 54
An output terminal 60 connected to the shift register 14 (FIG. 3) is derived from the output terminal of the output terminal 61 and an output terminal 61 connected to the up / down counter 13 and the latch circuit 15 (both of FIG. 3) from the output terminal of the NOR circuit 59. And the output terminal 62 connected to the up / down counter 13 is derived from the inverting output terminal Q (inversion) of the flip-flop circuit 55. The flip-flop circuits 46, 50, 51, 55, and 56 used as the delay circuits are, for example, as shown in FIG.
64 and FETs 65 to 68 that form a hysteresis section
And the FETs 69 and 70 that form the buffer section.

Next, the circuit operation of FIG. 8 will be described with reference to FIG.

Now, when the signal LAT supplied to the control signal input terminal 21 as shown in A of FIG. 10 changes from "0" to "1", the circuit operation is up / down mode from the normal mode (data capture mode). Change to. When the signal LAT changes from "0" to "1", the gates of the AND circuit 47 and the NOR circuit 59 are opened, and the output terminal 61
A load signal LDT (inverted) as shown by J in FIG. 10 is output, and the contents of the shift register 14 (FIG. 3) are taken into the up / down counter 13 (FIG. 3). Further, in the normal mode, the shift clock signal SFCLK for the shift register 14 obtained at the output terminal 44 via the NOR circuit 41 from the clock signal CLK shown in FIG. ”
When the gate of the NOR circuit 41 is closed by the change to "1", the gate is cut off as indicated by M in FIG. On the other hand, when the up / down clock signal UDCLK as shown by N in FIG. 10 to the up / down counter 13 which has not been output in the normal mode, the gate of the NOR circuit 42 is changed by the change of the signal LAT from “0” to “1”. When opened, it is output to the output terminal 45.

The output terminal Q of the flip-flop circuit 46 is synchronized with the change of the signal LAT from "0" to "1".
After a predetermined delay time, an output signal S ₁ as shown in D of FIG. 10 is output to the trigger terminal T of the flip-flop circuit 48. When the level of the trigger terminal T is "1", the flip-flop circuit 48 outputs the input signal as it is, but when it is "0", it holds the previous state. Therefore, the signal DIN is now inverted and derived at the inverting output terminal of the flip-flop circuit 48. This signal S ₂ is sequentially output to the flip-flop circuits 50 and 5 in the subsequent stages.
1, 55 and 56 are transmitted with a predetermined delay time,
Therefore, flip-flop circuits 50, 51, 55 and 56
Output signals S ₃ , S ₄ , S ₅ and S ₆ as shown at F to I in FIG. In addition,
Only when the levels of the signals S ₃ and S ₄ are different from each other, the gate of the NOR circuit 54 is opened via the AND circuits 52 and 53, and the load signal LTD (inverted) as shown by K in FIG. 10 is output to the output terminal 60. As a result, the contents of the up / down counter 13 are once moved to the shift register 14. When the signal S ₅ changes from “0” to “1”, its inverted output is output to the output terminal 62 as the up / down signal U / D (inversion) as shown by L in FIG. Then, the next load signal LDT (inversion) is output as indicated by J in FIG. 10, whereby the contents waiting in the shift register 14 are returned to the up / down counter 13. In this way, the contents of the up / down counter 13 are once made to wait in the shift register 14 before the generation of the up / down signal U / D (inversion), and the signal U / D
The reason for returning to the up / down counter 13 at the same time as the occurrence of (reversal) is based on the method of making the up / down counter. When the up / down ucanter is to be made regularly, the up / down counter is changed before the up / down switching. This is because if the data is latched, the up / down counter is destroyed at the time of up / down switching.

The contents of the up / down counter 13 are the contents of the up / down clock signal U from the output terminal 45 in accordance with the level of the signal DIN of the input terminal 22 for instructing the up mode and the down mode in the up / down mode.
It is incremented or decremented by 1 at the rising edge of DCLK (N in FIG. 10). For example, the contents of the up / down counter 13 are the clock signal UDC when the level of the signal DIN is "1".
Every time LK is input, it increases by 1 at the rising edge,
When it is "0", it decreases by 1 each time the clock signal UDCLK is input at the rising edge thereof.

Next, when the signal LAT changes from "1" to "0" as shown in A of FIG. 10, the circuit operation changes from the up / down mode to the normal mode, that is, the data acquisition mode. Then changes to "1" from "0" signals S ₁ to S ₆ in synchronism with the change to be with a predetermined delay time "1" from "0" of the signal LAT, the level of the signal S ₃ and S ₄ The load signal LT is output to the output terminal 60 in different periods.
D is generated, which causes the contents of the up / down counter 13 to be loaded into the shift register 14. Then, the loaded contents of the shift register 13 are the same as the signal LAT.
Of the shift clock signal SFCLK changed from "0" to "1" in synchronization with the change from "1" to "0" (see FIG.
0 of M) can be taken out to the output terminal 33 (FIG. 3) by inputting it to the shift register 14 and thereby substantially the current programmable divider 11 (FIG. 3).
You can know the frequency division number of.

Further, in synchronization with the change of the signal S ₅ from "1" to "0", the up / down signal U / D (inversion) of the output terminal 62 is changed from "1" to "0" as shown by L in FIG. The signal U / D (inversion) holds the level of the signal DIN at the time when its level changes. This also applies to the signals S _{2 to} S _6, and after these signals change from “1” to “0”, the signal D at the time of the change.
Holds the IN level.

Further, in synchronization with the change of the signal S ₅ from "1" to "0", that is, the generation of the signal U / D (inversion) is stopped, and at the same time, the output terminal 61 is indicated by J in FIG. Thus, the load signal LDT (inversion) is generated, whereby the contents of the shift register 14 are returned to the up / down counter 13.

FIG. 11 shows an example of a specific circuit configuration of the up / down counter 13, the shift register 14 and the latch circuit 15. In the figure, the output terminal 45 for outputting the up / down clock signal UDCLK is a flip-flop circuit 13 a of the up / down counter 13.
Connected to the clock terminal φ of the flip-flop circuit 1
The output terminal Q and the inverting output terminal Q (inversion) of 3a are connected to the clock terminal φ of the flip-flop circuit 13c via the switch circuit 13b, and the flip-flop circuit 13c
Is connected to the clock terminal φ of the flip-flop circuit 13e via the switch circuit 13d, and the output terminal Q and the inverted output terminal Q (inversion) of the flip-flop circuit 13e are switched circuits. 1
Although not shown, it is connected to the clock terminal of the flip-flop circuit of the next stage via 3f, and these flip-flop circuits and switch circuits are provided in a number corresponding to the number of bits depending on how many bits the up / down counter 13 processes. It is provided. The switch circuits 13b, 13d, 13f, ... Are switched by an up / down signal U / D (inversion) from the output terminal 62. For example, in the down mode, the switch circuits 13b, 13d, 13f ,. It is connected to the contact a side and is switched to the contact b side in the up mode.

The output terminal 61 for outputting the load signal LDT (inversion) outputs the flip-flop circuits 13a, 13a of the up / down counter 13 via the inverter 13g.
are connected to the load terminals L of c, 13e, ... And each of the flip-flop circuits 13a, 13c, 13e, ... Is set in a load state for receiving an input signal when the level of the load terminal L is a predetermined level, eg, "1".

The output terminal 44 for outputting the shift clock signal SFCLK has the flip-flop circuits 14a, 14b, 14c, ...
n clock terminal φ. It should be noted that these flip-flop circuits are arranged in the number corresponding to the number of bits depending on how many bits the shift register 14 processes. The output terminal 60 for outputting the load signal LDT (inversion) is connected to the load terminal L of each of the flip-flop circuits 14a, 14b, 14c ...
Connected to each of the flip-flop circuits 14a, 14b,
14c ... 14n is a load state when the input data is serial data, that is, data from the input terminal 22, the load terminal L is "0", and parallel data, that is, data from the up / down counter 13 is a load terminal. When L is "1", the load state is set.
Further, the input terminal 22 to which the signal DIN is applied is connected to the data input terminal D of the flip-flop circuit 14n and the data inverting input terminal D via the inverter 14f.
Connected to (reverse).

At the output side of the flip-flop circuit for the last bit of the data input to the shift register 14, here the flip-flop circuit 14n, the level of the code C that determines the latch direction of the input data in FIGS. 4 and 5 is set. Field-effect transistors 14g and 14h having a wired OR structure are provided for sorting and determining the contents of the shift register 14 to the up / down counter 13 side or the latch circuit 15 side. That is, the gate terminal of the transistor 14g is connected to the inverting output terminal Q of the flip-flop circuit 14n, the drain terminal is connected to each load terminal L of the flip-flop circuits 13a, 13c, 13e ... Grounded. The gate terminal of the transistor 14h is connected to the output terminal Q of the flip-flop circuit 14n, and the drain terminal of the transistor 14h is connected to the flip-flop circuits 15a and 15a of the latch circuit 15.
b, 15c, ... Connected to each load terminal L, and the source terminal is grounded. The number of flip-flop circuits forming the latch circuit 15 is also set according to the number of bits of the latch circuit 15 depending on how many bits the latch circuit 15 processes. In addition, the flip-flop circuits 15a, 15b,
An output terminal 61 for outputting a load signal LDT is connected to a load terminal L of 15c ... Through an inverter 15d, and flip-flop circuits 15a, 15b, 15c.
.. are connected to the reference frequency divider 16.

The remaining flip-flop circuits except the flip-flop circuit 14n for the last bit of the shift register 14, which are the flip-flop circuits 14a, 1 in FIG.
The output terminals Q of 4b, 14c, ... Corresponding flip-flop circuits 13a, 1 of the up / down counter 13, respectively.
3c, 13e ... Flip-flop circuits 15 connected to respective input terminals I of the latch circuits 15
are connected to the respective input terminals I of a, 15b, 15c ....
Further, each output terminal Q of the flip-flop circuits 13a, 13c, 13e, ... Of the up-down counter 13 is programmable via the multiplexer 12 to the programmable frequency divider 11 (FIG. 3).
And the input terminals I of the corresponding flip-flop circuits 14a, 14b, 14c, ... Of the shift register 14, respectively.

Now, in the normal mode (data capture mode) in which the signal LAT is in the "0" state, the data signal DIN from the input terminal 22 is shifted bit by bit at the rising edge of the shift clock signal SFCLK from the output terminal 44. Each flip-flop circuit 14a, 14b, 1
It is sent to 4c ... 14n. Then, when the signal LAT becomes "1", the load signal LD is output from the output terminal 61.
Although T (inversion) is generated and each flip-flop circuit of the up-down counter 13 and the latch circuit 15 is in a load state, each flip-flop circuit of the up-down counter 13 and the latch circuit 15 depends on the state of the last bit of the input data. The load state of one side of the circuit is suppressed and only the other side is substantially loaded. That is, the last bit of the data supplied to the input terminal 22 (see FIG.
And the C code in FIG. 5 is "1", the transistor 14h is turned on and the level of the load terminal of each of the flip-flop circuits 15a, 15b, 15c. Since the transistor 14g is suppressed, the flip-flop circuits 13a, 13c,
Only 13e ... are loaded. Therefore, the contents of the shift register 14 are latched by the up / down counter 13 and used as the data of the programmable frequency divider 11. When the last bit of the input data supplied to the input terminal 22 is "0", the transistor 14g turns on,
Since the transistor 14h is turned off, each flip-flop circuit 13a, 13c,
The load state of 13e ... Is suppressed, and the shift register 1
The contents of 4 are latched by the latch circuit 15, and the reference frequency divider 1
It is used as 6 data.

Next, when the signal LAT becomes "1", the mode is changed to the up / down mode, and the load register LDT (inversion) from the output terminal 60 causes the shift register 1 to operate.
4 flip-flop circuits 14a, 14b, 14c ...
14n is loaded and up / down counter 1
The contents of 3 are once transferred to the shift register 14. Then, at the same time when the up / down signal U / D is generated from the output terminal 62, a load signal LDT (inversion) is generated from the output terminal 61, the up / down counter 13 is put into the load state again, and the contents of the shift register 14 are changed. Returned to. Then, the up / down clock signal UDCLK from the output terminal 45 is accepted, and the signal U /
When D is "0", each switch circuit 13b, 13d, 1
3f ... Is connected to the contact a side, and the down mode is set.
The content of the up / down counter 13 is decremented by 1 at the rising edge of the up / down clock signal UDCLK. When the signal U / D is "1", each switch circuit 13b, 13
are switched to the contact b side to enter the up mode, and the content of the up / down counter 13 is incremented by 1 at the rising edge of the up / down clock signal UDCLK.

FIG. 12 shows the bit code A for prescaler control and unlock signal output shown in FIG.
An output signal AO obtained at the output terminal 32 (FIG. 3) and an output signal BO obtained at the output terminal 31 (FIG. 3) by the combination of B, T ₁ and the test bit code T ₂ shown in FIG.
2 shows an example of the relationship mode of FIG. For example, when (T ₁ , T ₂ ) is (0, 0), the output terminals 32 and 31 are in the normal mode in which the values of A and B are output as they are, and when (1, 0), the output terminal 32 is output. The unlocked state of the phase comparator 18 (FIG. 3) is output to the output terminal 31, and the value of B is output to the output terminal 31 in the unlock mode. Also, (T ₁ , T ₂ ) (A, B) is (1, 1)
When (0,0), the reference frequency divider 16 is connected to the output terminal 32.
The output signal RD of FIG. 3 and the output signal PD of the programmable frequency divider 11 (FIG. 3) are output to the output terminal 31, respectively, so that the operation of the phase comparator 18 can be checked (FIG. 3). Test mode of (1, 1) (1,
0), the output signal RD of the reference frequency divider 16 is output to the output terminal 32, and at least the most significant bit RMB of the output signal of the reference frequency divider 16 is output to the output terminal 31 and the reference frequency division is performed. In the test mode of the reference frequency divider 16 in which the operation of the frequency divider 16 can be checked, and when (1, 1) (0, 1), the output signal PD of the programmable frequency divider 11 and the output terminal are output terminal 32. 31 is at least the most significant bit PMB of the output signal of the programmable frequency divider 11.
Are output respectively and the operation of the programmable frequency divider 11 can be checked, and the programmable frequency divider 11 enters the test mode. When (1, 1) (1, 1), the load signal of data is output to the output terminal 32. The test and timing mode of the prescaler in which the output signal PSD of the prescaler (not shown) is output to the LDT and output terminal 31 is set.

FIG. 13 shows an example of a concrete circuit configuration for performing the logic processing of FIG. 12 described above. In practice, the output terminals 31 and 32 in FIG. 3 have the gate circuit as shown in FIG. It is designed to be derived through. That is, in FIG. 13, the input terminal 71 to which the lock signal LOCK is supplied from the phase comparator 18 (FIG. 3) is supplied.
(Substantially equivalent to the contact b of the switch 30 in FIG. 3) is connected to one input end of the AND circuit 72, and the bit T ₁ is applied from the shift register 14 or the latch circuit 15 (both in FIG. 3). The input terminal 73 is an AND circuit 7.
The input terminal 76 connected to the other input terminal of 2 and to one input terminal of the AND circuit 75 via the inverter 74 and to which the bit T ₂ is applied from the shift register 14 or the up / down counter 13 is a NOR circuit. It is connected to one input terminal of 77 and is also connected to each one input terminal of the NOR circuit 79, the AND circuit 80, and the NOR circuit 81 via the inverter 78.

The input terminal 82 to which the output signal RD of the reference frequency divider 16 (FIG. 3) is supplied is connected to one input terminal of the AND circuit 83, and the output signal P of the programmable frequency divider 11 is supplied.
The input terminal 84 to which D is supplied is connected to one input end of the AND circuit 85 and also connected to one input end of the AND circuit 86. An input terminal 87 to which a signal LDT obtained by inverting the load signal LDT (inversion) from the timing controller 19 (FIG. 3) is supplied is connected to one input terminal of the AND circuit 88, and the shift register 14 or the latch circuit 15 is connected. The input terminal 89 to which the bit A is supplied is connected to the other input terminal of the AND circuit 88 and each one input terminal of the AND circuits 90 and 91, and also via the inverter 92, the AND circuits 75 and 8 are connected.
It is connected to the other input terminals of 5,86 and one input terminal of the AND circuit 93. Similarly, the input terminal 94 to which the bit B is supplied from the shift register 14 or the latch circuit 15 is the other input terminal of the AND circuits 85 and 88, and the AND circuits 80 and 9.
Inverter 95 connected to the other input terminals of 3, 91
Is further connected to the other input end of the AND circuit 86 via.
Most significant bit RMB of the output signal of the reference frequency divider 16
Is connected to the other input terminal of the AND circuit 90, and the most significant bit PMB of the output signal of the programmable frequency divider 11 is supplied to the input terminal 9
7 is connected to the other input terminal of the AND circuit 93, and the input terminal 98 to which the output signal PSO of the prescaler (not shown) is supplied is connected to the other input terminal of the AND circuit 91.

The output terminals of the AND circuits 75 and 72 are connected to the other input terminals of the NOR circuit 77, respectively.
The output terminals of 85 and 88 are connected to the other input terminals of the NOR circuit 79, and the output terminals of the NOR circuits 77 and 79 are connected to the input terminals of the NOR circuit 99, respectively. The output terminal of the NOR circuit 99 is connected to the gate terminal of the field effect transistor 100, and also connected to the gate terminal of the field effect transistor 102 via the inverter 101.
00 has a source terminal grounded and a drain terminal connected to the source terminal of the transistor 102.
The drain terminal of 2 is connected to the positive power supply terminal V _DD , and the output terminal 32 is derived from the connection point of the drain terminal of the transistor 102 and the source terminal of the transistor 102.

Further, AND circuits 86, 90, 93, 91.
Is connected to each input terminal of the NOR circuit 81,
The output terminals of the AND circuit 80 and the NOR circuit 81 are connected to the input terminals of the NOR circuit 103, respectively. And the NOR circuit 10
3 is connected to the gate terminal of the field effect transistor 104, connected to the gate terminal of the field effect transistor 106 via the inverter 105, connected to the gate terminal of the transistor 104, and connected to the field effect via the inverter 105. The source terminal of the transistor 104 is connected to the gate terminal of the transistor 106, the drain terminal is connected to the gate terminal of the transistor 106, the source terminal of the transistor 104 is grounded, and the drain terminal is connected to the source terminal of the transistor 106. The drain terminal of the transistor 106 is connected to the positive power supply terminal V _DD , and the output terminal 31 is derived from the connection point of the drain terminal of the transistor 104 and the source terminal of the transistor 106.

[0039] Then, when the bit T ₂ of the bits T ₁ and the input terminal 76 of the input terminal 73 are both "0", the bit A of the input terminals 89, bit B input terminal 94 is respectively output terminal 32, 31 Is output to the external prescaler and the constants of the filter are switched by the combination of these bits as described above.

When the bit T ₁ is "1" and the bit T ₂ is "0", an unlock signal, that is, an inverted signal of the signal LOCK is taken out to the output terminal 32 and the output terminal 31
, The bit B is taken out. Output terminal 3 when both bits T ₁ and T ₂ are "1" and both bits A and B are "0"
The frequency dividers 1 from the input terminals 82 and 84 are respectively provided at 2 and 31.
Output signals RD and PD of 6 and 11 are output, and the operation of the phase comparator 18 is checked by these signals. Bit T
₁ and T ₂ are both “1” and bits A and B are “1”,
When it is “0”, the reference frequency divider 1 from the input terminal 82
The most significant bit RMB of the output signal of 6 is the output terminal 3
1 is output, which checks whether or not the data is correctly transmitted from the least significant bit to the most significant bit inside the reference frequency divider 16. Also, bits T ₁ and T ₂
Are both "1" and bits A and B are "0" and "1", respectively, the programmable frequency divider 1 from the input terminal 84
The output signal PD of 1 is output to the output terminal 32, and the most significant bit PMB of the output signal is output to the output terminal 31 from the input terminal 97 to the programmable frequency divider 11. It is checked whether data has been transmitted correctly from the least significant bit to the most significant bit inside. In addition, bit T ₁ ,
When T ₂ , A and B are all "1", the data load signal LDT from the input terminal 87 is output to the output terminal 32 and used as a timing signal and at the same time as the input terminal 98.
The output signal PSO of the prescaler is output to the output terminal 31 and is used for checking the operation of the teprescaler.

[0041]

According to the present invention, the timing control means causes the first frequency division ratio data as the initial state setting data,
The input selection data is stored in the storage means according to the clock signal, the division ratio of the reference frequency divider is set by the first division ratio data, and the input signal supplied to the programmable frequency divider by the input selection data. , And then the second frequency division ratio data for frequency setting is supplied to the programmable frequency divider to set the frequency, making it easy to use the serial data transfer line to initialize the phase-locked loop. It is possible to

[Brief description of drawings]

FIG. 1 is a system diagram showing an example of a conventional circuit.

FIG. 2 is a diagram for explaining the operation of FIG.

FIG. 3 is a system diagram showing an embodiment of the present invention.

FIG. 4 is a diagram for explaining the operation of FIG.

FIG. 5 is a diagram for explaining the operation of FIG.

6 is a diagram for explaining the operation of FIG.

7 is a diagram for explaining the operation of FIG.

FIG. 8 is a circuit diagram showing an example of a main part of the present invention.

9 is a connection diagram showing an example of a specific circuit configuration of a main part of FIG.

10 is a diagram for explaining the operation of FIG.

FIG. 11 is a circuit diagram showing an example of another main part of the present invention.

FIG. 12 is a diagram for explaining the present invention.

FIG. 13 is a circuit diagram showing an example of still another essential part of the present invention.

[Explanation of symbols]

 11 programmable frequency divider 13 up-down counter 14 shift register 15 latch circuit 16 reference frequency divider 19 timing controller

Claims (1)

[Claims] 1. A reference frequency divider for dividing an output of a reference oscillator by a first frequency division ratio, and outputs of a plurality of voltage controlled oscillators supplied to a plurality of signal input terminals are desired to be 1 according to input selection data. One is a programmable frequency divider for dividing the second frequency dividing ratio of the frequency setting is supplied is selected, a timing control means for latching signals, data and clock signals are supplied, said programmable frequency divider Of the reference frequency divider and a phase comparator for comparing the output of the reference frequency divider, and a temporary storage means, and the timing control means has the first frequency division ratio data as the initial state setting data, and the input selection. the stores the data and control data in the temporary memory means in response to said clock signal
Set preferences division ratio of the reference divider by the first frequency dividing ratio data on the basis of the control of the control data, by the input selection data to select the input signal supplied to the programmable frequency divider Then, the second frequency division ratio data and control data for frequency setting are stored in the temporary storage means.
A timing control circuit for a phase lock loop, characterized in that the second frequency division ratio data is supplied to the programmable frequency divider to set the frequency based on the control of the control data .