JPH0754457B2 - Multi-bit adder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a multi-bit adder, n input by the first addition means
The carry obtained by adding the data of the lower (n−m) bits of the bit data and the data of the upper m bits are fetched into the data holding means.

Then, after the addition by the second adding means using the output of the data holding means, the operation results of the first and second adding means are arranged to obtain an n-bit operation result. The means aims at speeding up without increasing the circuit scale by causing another calculation.

[Field of Industrial Application] The present invention relates to an improvement of a multi-bit adder, for example, a multi-bit adder used in an LSI processor or the like.

In general, when multi-bit addition is performed, carry occurs due to addition of lower bits and propagates to higher bits. Therefore, as n increases, the time required for addition increases and the operation time increases. Will increase.

Therefore, it is desired to reduce the calculation time (that is, speed up) without increasing the circuit scale.

[Conventional technology]

FIG. 4 shows a block diagram of a conventional example, and FIG. 5 shows an operation explanatory diagram of FIG. The symbols on the left side in FIG. 5 indicate the waveforms of the portions having the same symbols in FIG.

The operation of FIG. 4 will be described below with reference to FIG.

First, the registers 1, 3, 5 contain the data A, B, C of the X group, and the registers 2, 4, 6 contain the data D, E, F of the Y group, respectively (FIG. 5-X group, Y). See group).

These data are data A, B and C when the selection signal is at H level and data D, E and F when they are at L level as shown in FIG.
Is selected by the selectors 7, 8 and 9 and added to the adder ADDR 10. The selection time T is the time when the calculated value is fixed and the minimum necessary condition for fetching it is secured.

Now, as shown in FIG. 5-the selectors 7, 8 and 9 display data A,
When B and C are selected, these data are added to the adder ADDR 10 to start addition as shown in FIG.
After that, the calculated value, that is, the calculation result, is taken into the first accumulator ACC ₁ 11 as shown in FIG. 5 at the clock CK ₁ shown in FIG.

It should be noted that a large number of X-marked portions in FIG.
The part (A + B + C) shows the part of the calculation result.

Next, the selectors 7, 8, 9 select the data D, E, F and add the data by the adder ADDR10 as described above, and the clock CK ₂ shown in FIG. the operation result is taken into the second accumulator ACC ₂ 12 to.

Incidentally, t is T> t in order to capture the calculation result in the calculation time.

[Problems to be solved by the invention]

Here, in the case where one adder is time-divided and different data is added as described above, the next data is not calculated until one addition is completed for all bits and the calculation result is fetched into the accumulator ACC. Since this cannot be done, there is a problem that when the number of data bits n becomes large, t, that is, T becomes large and the operation time becomes long.

If one adder is assigned to one calculation to avoid this, the calculation time will be reduced, but the circuit scale will be large, and it will be difficult to realize it in a limited circuit scale such as an LSI. There is another problem to say.

[Means for solving problems]

The above problem is solved by the multi-bit adder shown in FIG.

Reference numeral 13 divides a plurality of types of n-bit data of each group into upper m bits and lower (n−m) bits, and alternately outputs the lower (n−m) bits of each group at a preset cycle. Dividing means, 14 is a first adding means for adding outputs of the dividing means to hold a calculation result and sending a carry, 15 is a data holding means for holding the upper m bits of each group and the carry, 16 Has an adder / holder for each group, adds the upper m bits of the group corresponding to the carry taken out from the data holding means, and holds the operation result, and 17 is the first, second Of the calculation results held by the adding means of
It is an operation result merging means for obtaining an operation result of bits.

[Action]

In general, when a multi-bit addition is performed, a carry signal (carry) generated by the addition is transmitted to the higher bits, and therefore, the higher the bit, the more delayed the operation and the difference in the operation time between the higher bit and the lower bit.

In order to utilize this time difference in the present invention, a plurality of types of n-bit data forming the first and second groups are divided by the dividing means into upper m bits and lower (n−m) bits,
The lower (nm) bits of each group are alternately transmitted at a set cycle (1/2 of the clock cycle).

Therefore, the first adding means 14 adds the output of the dividing means, for example, the lower (nm) bits of the first group, and holds the result when the operation result is obtained and holds the carry as data. After sending to the means 15, the addition of the lower order (n−m) bits of the second group input next is performed. In addition,
The data holding means 15 holds the upper m bits of the first and second groups for each group.

On the other hand, the second adding means 16 adds the carry from the data holding means 15 and the upper m bits of the first group to obtain an operation result, and then arranges the operation result of the first adding means side by side. The operation result of n bits in each group is obtained.

In other words, the first adding means is the lower (n
-M) bits are alternately calculated at a set cycle, and the second adding means separately calculates the upper m bits of the two groups,
The overall speed of the circuit has been increased without increasing the circuit scale.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an operation explanatory diagram of FIG. Throughout the drawings, the same reference numerals denote the same objects, and the symbols on the left side of FIG. 3 indicate the waveforms of the portions having the same symbols in FIG.

The first adder 141, the third accumulator 142, and the fourth accumulator 143 are parts of the first adding means 14,
The intermediate register 151 and the second intermediate register 152 are part of the data holding means 15, and are the second adder 161, the third adder 163,
The fifth accumulator 162 and the sixth accumulator 164 are part of the second adding means 16. Also, 13 is a dividing means, 17
Is an addition result merging means.

Hereafter, the data A, B, C of the X group is stored in the registers 1, 3, 5 and Y
It is assumed that the group data D, E, and F are stored in the registers 2, 4, and 6, respectively, and the X group data and the Y group data are added in a time division manner. Referring to FIG. 3, the operation of FIG. Will be described (see FIG. 3-X group, Y group).

First, the upper m bits of the n-bit data A, B, C fetched from the registers 1, 3, 5 and the n-bit data D, E, F fetched from the registers 2, 4, 6 are the first intermediate bits. In the register 151 and the second intermediate register 152, data A, D, data B, E,
The lower (n−m) bits of the data C and F are input to the selectors 7, 8 and 9, respectively.

The lower (n−m) bits of the data A, B, C selected by the selectors 7, 8, 9 driven by the H level selection signal shown in FIG. 3 are the first adder ADDR ₁ 141 The operation result and the carrier are obtained by adding with, but the operation result is taken into the third accumulator ACC ₃ 142 at the clock CK ₁ ,
The carry is taken into the first intermediate register 151 (see FIG. 3,-). The upper m bits and the carry are added by the second adder ADDR ₂ 161 and the operation result is fetched by the fifth accumulator ACC ₅ 162 at the clock CK ₂ and output (see FIG. 3-).

Here, the operation result of the lower (n−m) bits of the data A, B, C taken in the _third accumulator ACC ₃ 142 and the data A, B, taken in the fifth accumulator ACC ₅ 162.
Since the operation result of the upper m bits of C is held until the next clock is input, the output of the accumulator is taken out between the portion a in FIG. 3 and the portion b in FIG. As a result, the calculation results of the data A, B, C can be obtained (see FIG. 3,-).

Note that the first arithmetic unit ADDR ₁ 141 is lower than the data A, B, C (n-
When the addition of m) bits is completed, the selectors 7, 8 and 9 are driven and the lower (n−m) bits of the data D, E and F are input.
At CK ₂ , the fourth accumulator ACC ₄ 143 and the carry are taken into the second intermediate register 152 (FIG. 3 −,
,reference).

At this time, the upper m bits of the data D, E, F are simultaneously taken in by the second intermediate register 152, the upper m bits are added by the third adder ADDR ₃ 163, and the operation result is obtained by the clock CK _1. Is taken into the sixth accumulator ACC ₆ 164 and taken out side by side with the output of the fourth accumulator ACC ₄ 143, and the n-bit operation result of the data D, E, F is taken out.
Then, this is repeated (see FIG. 3,-).

That is, since the operation of the lower bits ends earlier than the operation of the upper bits, the operation units are used in a time-sharing manner, and the operation of the upper bits has a separate operation unit to end the operation quickly, thus making the circuit scale as a whole. Has made the calculation speed faster without increasing so much.

〔The invention's effect〕

As described in detail above, according to the present invention, there is an effect that the operation speed is increased without increasing the circuit scale so much.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is an operation explanatory diagram of FIG. 2, FIG. 4 is a block diagram of a conventional example, and FIG. The operation explanatory drawing of FIG. 4 is shown. In the figure, 13 is dividing means, 14 is first adding means, 15 is data holding means, 16 is second adding means, and 17 is addition result merging means.

Claims (1)

[Claims] 1. The first and second groups are each composed of a plurality of types of n-bit data, and when a plurality of types of n-bit data are added to each group, the plurality of types of n-bit data of each group are respectively added. A dividing means (13) which divides the upper m bits and the lower (nm) bits and alternately outputs the lower (nm) bits of each group at a preset cycle, and an output of the dividing means. A first adding means (14) for adding and holding the operation result and sending out a carry, a data holding means (15) for holding the upper m bits of each group and the carry, and an addition / holding part for each group A second adding means (16) for holding the operation result by adding the upper m bits of the group corresponding to the carry taken out from the data holding means, and the first and second adding means. Calculation results held Side by side, the n of each group
A multi-bit adder, comprising: an operation result merging means (17) for obtaining an operation result of bits.