JPH0754495B2 - Register read circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register read circuit, and more particularly to a register read circuit having an improved read speed of data stored in a register.

[Conventional technology]

FIG. 3 is a diagram showing a main configuration of an embodiment of a conventional computer device. In the figure, 1 is a microprocessor, 2 is a peripheral device for assisting the microprocessor 1 such as direct memory access and interruption, 3 is an address bus connecting the microprocessor 1 and the peripheral device 2 and transmitting a plurality of address signals, 4 is a A decoder 5 for selecting the peripheral device 2 is a second data bus for connecting the microprocessor 1 and the peripheral device 2 and transmitting a data signal, and 6 is a register reading circuit inside the peripheral device 2.

FIG. 4 is a block diagram showing the configuration around the peripheral device 2 in FIG. In FIG. 4, 7 is a plurality of registers for storing data by means not shown, 20 is a register group composed of the plurality of registers, and 15 is a part of a plurality of address signals from the address bus 3. An internal decoder that outputs a signal that selects one of the registers 7 from the register group 20, 11 is a read signal line that outputs a read signal that puts the peripheral device 2 into a read state, and 12 is a first circuit that controls the operation timing of the circuit. A first timing signal line through which a timing signal is transmitted, 13 is a first AND gate that receives the first timing signal and a device selection signal of the decoder 4 and outputs a predetermined signal, and 14 is the read signal and the first AND gate
A second AND gate that receives the output signal of 13 and outputs a predetermined signal, 18 receives the output signals of the second AND gate 14 and the internal decoder 15, and selects one of the registers 7 from the register group 20. First control circuit for outputting stored data, 16
Is a third AND gate which receives the output signals of the second AND gate 14 and the internal decoder 15 and outputs a predetermined signal; 9 is a first transmission gate which receives the output signal of the third AND gate and controls the output of the register 7; Is a first data bus to which the data read from the register 7 is transferred, and 19 is a first data bus for receiving the signal from the second AND gate 14 and outputting the data transferred to the first data bus 8 to the second data bus 5. Two control circuits, 10 is a second transmission gate that constitutes the second control circuit.

The peripheral device 2 includes a register read circuit 6 and a second AND gate 14. The register read circuit 6 includes the register group 20, the first data bus 8, the internal decoder 15, the first control circuit 18, and the second control circuit. The first control circuit 18 includes a plurality of first transmission gates 9 and a plurality of third AND gates 16.

Here, the first data bus 8 is of a so-called precharge type in which data is transmitted from the first control circuit 18 by being charged (precharged) in advance and then maintaining or discharging the charged state according to the data. The first data bus 8 is changed from the precharge state to the data transmission state by the first timing signal input to the first timing signal line 12. Note that these state changes are performed by a device (not shown).

FIG. 5 is an operation timing chart of the conventional device. Less than,
The operation of the conventional device will be described with reference to the drawings. First, the operation of the register read circuit 6 will be described based on an embodiment of the computer device shown in FIG. The microprocessor 1 advances its work while exchanging information with a memory and a peripheral device 2 not shown. The microprocessor 1 has a register 7 in the peripheral device 2.
When reading the data of, the information for selecting the register group 20 inside the peripheral device 2 (hereinafter, referred to as upper address) and the information for selecting one of the registers 7 from the register group 20 inside the peripheral device 2 (hereinafter, lower order) A plurality of address signals including an address) are output to the address bus 3, the decoder 4 and the register read circuit 6 in the peripheral device 2 are operated, and the register read circuit 6 transmits the data to the second data bus 5. The microprocessor reads this data. The operation of the conventional device will be described in detail, assuming that one form of this information exchange is register reading by a microprocessor.

A period in which a signal is fixed on the read signal line 11 is a read period. When the address signal is determined on the address bus 3 at time a, the decoder 4 decodes the upper address and the internal decoder 15 of the register read circuit 6 inside the peripheral device 2 decodes the lower address. Since the lower-order address signal has a smaller number of bits than the upper-order address signal, the internal decoder 15 finishes its operation first, the register selection signal is confirmed at time b, and the peripheral device selection signal is confirmed by the decoder 4 at time d. At time e, the signal is fixed on the first timing signal line 12. The first AND gate 13 is a decoder 4 and a first timing signal line 12
And outputs the required signal. This signal causes two actions. That is, the first data bus 8 in the precharged state is brought into the data transmission state, and the second AND gate 14 receiving the signals of the read signal line 11 and the first AND gate 13 outputs the required signal. Two further actions occur with this signal. That is, the data of one register 7 selected by the first control circuit 18 is transmitted to the first data bus 8 and the data of one register 7 is transmitted by the second control circuit 19.
Data is transmitted to the second data bus 5. Hereinafter, these two operations will be described in detail. When one third AND gate 16 receiving the output signals of the second AND gate 14 and the internal decoder 15 outputs a signal, one first transmission gate 9 selected by this signal and one of the registers 7 and The data signal is fixed at time f in the first data bus 8 which is connected to the data bus 8 and is in the data transmission state. Then, the second transmission gate 10 of the second control circuit 19 which receives the output signal of the second AND gate 14 connects the first data bus 8 and the second data bus 5, and at the second data bus 5, time g The data signal is fixed at.

The above is the register read operation of the conventional device.

[Problems to be Solved by the Invention]

Generally, in a computer device as shown in FIG. 3, improvement in processing speed is required. The related process of the register read circuit is the exchange of information between each device. In order to realize fast and reliable exchange of information, it is necessary to shorten the time from address determination to data determination. In the conventional register read circuit described above, the first data bus 8 operates after the decoder 4 operates, so that it is difficult to speed up the confirmation of data. This indicates that it is difficult to secure the time for which the data is fixed, in response to the demand for high speed.

The present invention has been made to solve the above conventional problems, and an object thereof is to obtain a high-speed register read circuit.

[Means for Solving the Problems]

A first register read circuit according to the present invention provides a register group including a plurality of registers for storing data and a signal for receiving one of a plurality of address signals and selecting one of the registers from the register group. An internal decoder for outputting, a read signal, a timing signal, and an output signal of the internal decoder are received, one of the registers is selected from the register group, and the storage data of the selected register is output to the first data bus. A control circuit and a predetermined signal related to a register group selection signal obtained by decoding the second parts of the plurality of address signals are received to transfer the data transmitted to the first data bus to the second circuit. The second register read circuit according to the present invention is the read control circuit according to claim 1, No. selects one register from the register group receives a timing signal and an output signal of the internal decoder, in which the data stored in the selected register and the outputs to the first data bus.

[Work]

In the present invention, the operation of the first control circuit is performed regardless of the signal for operating the second control circuit, and the data stored in the selected register is fixed to the first data bus.

As a result, the storage data read time of the register read circuit is shortened.

〔Example〕

 The configuration of an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a register read circuit according to an embodiment of the present invention. In the figure, 2 to 15 and 19 are the same as or equivalent to those in the conventional device.

In the figure, 17 is a second timing signal line through which a second timing signal for controlling the operation timing of the first control circuit 18 is transmitted. In this case, the first control circuit 18 uses the read signal line 11, the internal decoder 15, and the second timing signal line 17
To output the data of the selected register 7 to the first data bus 8. The plurality of third AND gates 16, 16, 16 are provided with the read signal line 11, the internal decoder 15, and the second timing. The first data bus 8 receives a signal from the signal line 17 and outputs a predetermined signal. The first data bus 8 has a precharge state and a data transmission state according to a second timing signal.
It takes one of two states.

FIG. 2 is an operation timing chart of the register read circuit of the present invention. The detailed operation will be described below with reference to this figure.

A period in which a signal is fixed on the read signal line 11 is a read period. When the address signal is determined on the address bus 3 at time a, the decoder 4 decodes the upper address and the internal decoder 15 of the register reading circuit 6 inside the peripheral device 2 decodes the lower address. Since the lower-order address signal has a smaller number of bits than the upper-order address signal, the internal decoder 15 finishes its operation first and determines the register selection signal at time b.

In the conventional circuit, from time b to time e, that is, the internal decoder
After 15 (see FIG. 4) selects the register 7, the decoder 4 finishes its operation, and the register read circuit waits until the signal is fixed on the first timing signal line 12.

In the circuit of the present invention, the data is fixed on the first data bus 8 from the time b to the time e corresponding to FIG. This operation will be described below. First, the register selection signal of the decoder 15 is fixed at time b, and then the signal is fixed on the second timing signal line 17 at time c. Then, these two signals cause the following two operations.
That is, on the one hand, the first data bus 8 in the precharged state is brought into the data transmission state by means not shown, and on the other hand, the data of one register 7 selected by the first control circuit 18 is transmitted to the first data bus 8. To be done. First control circuit
In the inside of 18, when one third AND gate 16 receiving the three signals of the read signal line 11, the internal decoder 15 and the second timing signal line 17 outputs a predetermined signal, it corresponds to the one selected by this signal. The transmission gate 9 connects the corresponding register 7 and the first data bus 8. Then, the data signal is fixed at the time f on the first data bus 8 in the data transmission state.

On the other hand, the decoder 4 determines the peripheral device selection signal at time d, as in the conventional case, and then determines the signal on the first timing signal line 12 at time e. The first AND gate 13 receives signals from the decoder 4 and the first timing signal line 12 and outputs a predetermined signal. The second AND gate 14 receiving this signal and the signal of the read signal line 11 outputs a predetermined signal.

In the conventional circuit, this signal causes the first control circuit 18 to start operating, but in the circuit of the present invention, only the second control circuit 19 operates because the data has already been determined on the first data bus 8.

The second transmission gate 10 receiving the output signal of the second AND gate 14 connects the first data bus 8 and the second data bus 5, and the data is fixed to the second data bus 5 at time g.

The above is the operation of the register read circuit of the present invention. As described above, in this embodiment, the decoder 4 and the first data bus 8 which are sequentially operated in the conventional circuit are configured to operate in parallel, so that the overall operation time is shortened.

Although the first data bus 8 is of the precharge type in this embodiment, it may be of the three-state type. Here, the three-state type has three states of high, low, and high impedance, and can transmit data regardless of timing. In that case, the second timing signal line 17 is unnecessary.

In this embodiment, the second timing signal line 17 receives a signal from an external circuit (not shown), but it may be generated by an internal circuit. In that case, the terminal of the second timing signal line 17 becomes unnecessary.

In this embodiment, the lower address signal has a smaller number of bits than the upper address signal.
Although the operation is completed earlier and the register selection signal is fixed, the operation may be reversed or equal due to reasons such as the number of bits and the operating speed of each device. In this case, new control means may be required inside depending on the timing and the state of the first data bus.

Although there is only one kind of timing signal in this embodiment, other timing signals can be added externally or internally. This allows each operation to have a margin.

In this embodiment, all signals used positive logic, but negative logic may be used if necessary. The circuit configuration can be rationalized by appropriately using positive and negative logic.

In this embodiment, the external decoder 6 is external to the circuit, but it may be built in if necessary and the system configuration can be widened.

In this embodiment, the transmission gate 10 in the circuit connects the first data bus 8 and the second data bus 5,
This part may be exposed to the outside.

Allows a wide range of system configurations.

〔The invention's effect〕

As described above, according to the present invention, when reading the data of the register, the operation of the first control circuit is performed by receiving the signals of the read signal line, the timing signal line and the output signal of the internal decoder, and the second control circuit. Regardless of the signal that drives
Since the storage data of the selected register is settled on the first data bus, there is an effect that a register reading circuit capable of reading the storage data of the register at high speed can be obtained.

[Brief description of drawings]

1 is a block diagram of a register read circuit according to an embodiment of the present invention, FIG. 2 is an operation timing of the register read circuit according to an embodiment of the present invention, FIG. 3 is a configuration diagram of a main part of a computer device, and FIG. FIG. 5 is a block diagram of a conventional register read circuit, and FIG. 5 is an operation timing diagram of the conventional register read circuit. In the figure, 7 is a register, 20 is a register group, 15 is an internal decoder, 11 is a read signal line, 17 is a second timing signal line, 8 is a first data bus, 18 is a first control circuit, and 5 is second data. The bus 19 is a second control circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A register group comprising a plurality of registers for storing data, an internal decoder for receiving a first part of a plurality of address signals and outputting a signal for selecting one of the register groups, and a read. A first control circuit that receives a signal, a timing signal, and an output signal of the internal decoder, selects one of the registers from the register group, and outputs the storage data of the selected register to a first data bus; Receiving a predetermined signal related to the register group selection signal obtained by decoding the second part of the address signal of the first data bus, and outputting the data transmitted to the first data bus to the second data bus. And a second control circuit. 2. The first control circuit directly receives the read signal, the timing signal and the output signal of the internal decoder, selects one of the registers from the register group, and stores data in the selected register. Is output to the first data bus.
The register read circuit according to the item.