JPH0754626B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a large capacity semiconductor integrated memory.

(Prior Art and Problems Thereof) Among conventional semiconductor memory devices, an example of a random access memory (hereinafter referred to as RAM) using MIS transistors is shown in FIG. 3 (IEE PROCEEDING magazine, Volume 130, June 1983). Month 1
Pages 27-135, "High Density Single Device Dynamics M
OS memory cell "" High-density one-device dynamic
MOS memory cells "). In the conventional MISRAM as shown in FIG. 3, when the voltage of the decoder output X _i selected by the X decoder is high level, the voltage of the word line activation signal RA changes from low level to high level. When the voltage goes up, the voltage of the word line W _i goes up from a low level to a high level.In general, only one decoder output goes high due to the address signal applied to the RAM, and only one word line At this time, the information of the memory cell 1 connected to the selected word line is read out to the digit line B _i connected to each memory cell, and the other digit line of the pair. ▲
▼ indicates whether the memory cell is high or low by a reference potential generating circuit.
A potential and an intermediate level are generated when the value storage information is read out to the digit line. As a result, a slight potential difference determined by the capacitance division of the memory cell capacitance and the digit line capacitance is generated between the pair of digit lines B _i and ▲ ▼, and the signal is amplified by activating the sense amplifier 2. . After that, the signal of the digit line is output through the input / output circuit selected by the Y decoder, and the reading of the memory information is completed. For writing, information is written to the selected digit line pair and memory cell through the input / output circuit.

In such a MISRAM, a gate electrode of polycrystalline silicon is used as a wiring as a word line as it is, and a metal wiring is used as a word line to switch a switch
There are two methods for connecting a polycrystalline silicon gate electrode of a transistor to a memory word line through a contact hole. The advantages and disadvantages of both methods are that, when the polycrystalline silicon wiring is a word line, there is an advantage that the layout pitch of the word line can be narrowed, but on the other hand, the resistance per unit length of the word line is large and the memory capacity can be increased. Therefore, if the wiring length of the word line becomes long, the signal propagation time from the near end to the far end of the word line becomes long, and there is a drawback that high speed read / write operation cannot be performed. On the other hand, when the metal wiring is used as the word line, the wiring resistance is extremely smaller than that of the polycrystalline silicon wiring, and thus high-speed operation is possible, but the contact connecting the metal wiring and the polycrystalline silicon gate electrode is used. There is a drawback that the layout margin of the hole becomes large and the layout pitch of the word line cannot be narrowed. As a compromise between the two, a method is also used in which two word lines, a metal line and a polycrystalline silicon line, are vertically stacked, and both lines are connected through a contact hole at a certain interval. (1984 IEEE INTERNATIONAL SOLID-STATE CIRCU
ITS CONFERENCE ISSC CDIGEST OF TECHNICAL PAPERS magazine,
February 1984, pp. 278-279, "A25ns64K SRAM"). With this method, the delay time at the far end of the word line is reduced, but with the high integration and large capacity of the memory, the miniaturization of memory cells, MIS transistors, wiring, etc. is reached. There is a drawback in that the layout margin of the contact hole connecting the wiring and the polycrystalline silicon wiring becomes large, and the layout pitch of the word line cannot be reduced.

As is clear from the above description, in the conventional word line drive circuit and wiring configuration, there are merits and demerits between the word line layout pitch and the signal propagation time, and there is a word line drive system that solves both of them. A semiconductor memory device has been earnestly desired.

An object of the present invention is to provide a semiconductor memory device which solves the above problems in a highly integrated and large capacity semiconductor memory, reduces the layout pitch of word lines, and has a high operation speed.

(Means for Solving the Problems) Means provided by the present invention in order to solve the above-mentioned problems include a plurality of memory cells arranged in a matrix and a plurality of switch gates for connecting the memory cells in the column direction. A sub word line, a main word line for each of the plurality of sub word lines arranged in parallel with the sub word line, a plurality of digit line pairs for connecting the digit terminals of the memory cells in the row direction, and the plurality of digit lines. A semiconductor memory device comprising at least a plurality of sense amplifiers respectively connected to a line pair, wherein the main word line is connected to the corresponding plurality of sub word lines at a plurality of locations through MIS transistors, respectively. Is.

(Operation) In the semiconductor memory device according to the present invention, as a word line, there are a main word line only for wiring and a sub word line in which a switch gate of a memory cell is directly entangled, and one main word line The plurality of sub-word lines are connected to each other at a plurality of the same places through MIS transistors. Therefore, in order to read the information of one memory cell, first, one main word line is selected, and further, one main word line is selected via one MIS transistor of a plurality of corresponding sub word lines, and 1 is selected in the column direction. Read the memory cells in the column. As a result, the information of each memory cell is read to the digit line entwined with the cell, the signal read by the corresponding sense amplifier is amplified, and only one of these signals is selected and externally output. Reportedly.

In the semiconductor memory device of the present invention, for example, the memory wiring is used as the main word line, the polycrystalline silicon wiring is used as the sub word line, and the polycrystalline silicon wiring of the sub word line is also used as the gate electrode of the switch gate transistor of the memory cell. As a result, the layout pitch of the sub word line can be narrowed. On the other hand, regarding the signal delay time between the near end and the far end of the word line, the sub word is connected to the main word line of the metal wiring through the MIS transistor at a plurality of locations of one sub word line. The signal delay time at both ends of the word line can be made substantially equal to that in the case of metal wiring. Moreover, since the main word line is arranged as one wiring for each of the plurality of sub word lines, even if the wiring width of the main word line is widened, the layout pitch of the word lines does not become large, and only the sub word lines are arranged. The narrow layout pitch determined by can be held. As a result, the present invention can realize both the reduction of the word line layout pitch and the reduction of the signal propagation time, which are difficult in the conventional semiconductor memory, and a large capacity semiconductor integrated memory using a long word line. It will be very useful.

(Examples) In order to facilitate understanding of the present invention, examples will be described below.

(Embodiment 1) FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In the MISRAM of this embodiment, the word line is composed of a main word line and a sub word line, and both word lines are MI at the near end and the far end of the main word line.
3rd except that it is connected through an S-transistor
It is almost the same as the conventional MISRAM in the figure, and the same circuit element is named the same signal.

In the MISRAM of this embodiment, when the voltage of the word line activation signal RA rises from the low level to the high level while the voltage of the decoder output X _i selected by the X decoder is at the high level, first, the main word line The voltage of W _oi rises from low level to high level. At the same time, the signal of either X _o or ▲ ▼ selected by one bit of the X address is held at a high level voltage in advance, and the sub word line W _i
The voltage of one word line of W _{i + 1} rises from low level to high level. Later, if the signal of ▲ ▼ is at a high level voltage, the voltage of the sub word line W _i rises from a low level to a high level, and the information of the memory cell 1 coupled to the sub word line is The data is read out to the digit line B _i connected to. In addition, the intermediate level of the high and low binary read signals is generated by the reference potential generating circuit on the other pair of digit lines (). As a result, the pair of digit lines B _i and ▲
A slight potential difference is generated between the two points, and the signal is amplified by activating the sense amplifier 2. After that, similarly to the conventional example of FIG. 3, data is transmitted to the outside by the Y decoder and the input / output circuit.

In this embodiment, when a metal wiring is used as the main word line and a polycrystalline silicon wiring is used as the sub word line, the sub word line directly entwined with the switch gate of the memory cell can be used as the gate electrode wiring, and the sub word line of the memory cell can be used. Since contact holes for connecting different wirings are not required, the layout bit of the sub word line can be narrowed. Further, as for the main word line, it is sufficient that one wiring is provided for every two sub word lines, so that a wiring width wider than that of the sub word line can be used. This is because the metal wiring generally has poorer processing accuracy than the polycrystalline silicon wiring and the wiring width is always wide, which is very convenient in practice.

Regarding the MIS transistor for connecting the main word line and the sub word line, one MIS transistor is provided at each end of each sub word line.
Although a transistor is required, this is the same in the conventional example shown in FIG. 3, and the sub word line pitch can be narrowed up to the word line pitch using the polycrystalline silicon wiring as the word line also in this embodiment. Become.

On the other hand, regarding the signal delay time of the word line, since the main word line of the metal wiring is connected through the MIS transistor at both ends of the sub word line, there is almost no difference in the signal delay time at both ends of the sub word line. . In this case, although the signal propagation time in the central portion of the sub word line is delayed,
Compared with the word line delay time in the case of using the polycrystalline silicon wiring word line in the conventional example of FIG. 3, it is reduced to about 1/4,
In practical use, a large speedup of word line signal propagation can be measured.

That is, in the present embodiment, both the reduction of the word line layout pitch and the reduction of the signal propagation time can be realized.

As described above, in the semiconductor memory device of the present invention, the main word line 1
With respect to the book, an embodiment having a configuration in which two main word lines and two sub word lines are connected via MIS transistors at two and three word lines has been described. The present invention is not limited to this configuration, and 1
Also applicable to MISRAM, etc., in which each main word line has three or more sub word lines, or in which four or more word lines connect the main word line and sub word lines through MIS transistors. it can. Also, in this embodiment,
Although the MIS transistor connecting the main word line and the sub word line has been described as an N channel MIS transistor, it may be a P channel or any other MIS transistor. Further, regarding the wiring material of the main word line and the sub word line, it is not limited to use the metal wiring for the main word line and the polycrystalline silicon wiring for the sub word line, and the present invention can be applied to any wiring material combination. Needless to say, can be applied.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize both the reduction of the word line layout pitch and the reduction of the signal propagation time, which have been difficult in the past, and to realize a large-capacity semiconductor integration. The memory is effective for large capacity and high speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a MISRAM showing a first embodiment of the present invention,
FIG. 2 is a circuit diagram for explaining a conventional MISRAM. In the figure, X _i and X _{i + 1} are X decoder outputs, RA is a word line activation signal, 1 is a memory cell, 2 is a sense amplifier, W _oi is a main word line, and W _i is a word line activation signal. , W _{i + 1} is the sub word line,
B _i , ▲ ▼ shows a digit line, and X _o , ▲ ▼ shows a sub word line selection signal.

Claims (1)

[Claims] 1. Memory cells arranged in a matrix,
A plurality of sub-word lines connecting the switch gates of the memory cells in the column direction, a main word line arranged in parallel with the sub-word lines for every plurality of the sub-word lines, and a digit terminal of the memory cell in the row direction. A plurality of digit line pairs connected to
At least a plurality of sense amplifiers respectively connected to the plurality of digit line pairs are provided, and the main word line is connected to the corresponding plurality of sub word lines via the MIS transistors at both ends of the sub word line. A semiconductor memory device characterized by being connected to.