JPH0754633B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.
The present invention relates to a technology effectively applied to an EPROM (electrically programmable read only memory) device composed of a MOSFET (insulated gate type field effect transistor).

[Conventional technology]

An EPROM device is known in which a semiconductor element such as FAMOS (floating avalanche injection MOSFET) is used as a negative element (memory cell) (for example, JP-A-54).
-152993 gazette). In the EPROM device, the threshold voltage is changed by selectively avalanche injecting electricity into the floating gate of the FAMOS transistor by using a writing high voltage Vpp set to a relatively high voltage such as about 12V. Then, the writing of the logical "0" or the logical "1" is performed.

[Problems to be solved by the invention]

The present inventors have developed a sense amplifier SA as shown in FIG. 3 in order to speed up the read operation of the FMOS transistor as described above. The signal read from the memory array to the common data line CD is supplied to the source of the amplification MOSFET Q11. In the gate of this amplification MOSFET Q11,
The inverted amplified signal of the common data line CD is supplied. That is, the MOSFET Q1 whose gate is coupled to the common data line CD
P-channel load MOS provided on 3 and its drain
FETQ14 forms an inverting amplifier circuit and outputs its output signal to the MO
It is transmitted to the gate of SFETQ11. Amplification MOSFET Q above
The drain of 11 has a P-channel MOSF as a load means.
ETQ12 is provided. The drain output of the amplification MOSFET Q11 is supplied to, for example, the CMOS inverter circuit IV, and the high level / low level of the read signal is discriminated by using the logic threshold voltage as a reference voltage.

The selected memory cell has a high threshold voltage or a low threshold voltage with respect to the word line selection level at the time of reading according to the data written in advance. If the selected memory cell in the memory array (not shown) has a high threshold voltage (“0”), no direct current path is formed between the common data line CD and the circuit ground. In this case, the common data line CD is set to a relatively high level by the current supply from the MOSFETs Q11 and Q12. At this time, when the common data line CD reaches a predetermined potential, the MOSFET Q11 is turned off by the inverted output signal of the output signal of the inverting amplifier circuit, and the current supply is stopped. Therefore,
The high level of the common data line CD is limited to a relatively low potential. On the other hand, if the selected memory cell in the memory array has a low threshold voltage, the column switch MOSFE is connected between the common data line CD and the circuit ground.
T, data line, selected memory cell and MOSFET Q11, Q12
A direct current path is formed through the. Therefore, the common data line CD is set to the low level regardless of the bias current supplied from the bias circuit. The amplitude limitation between the high level and the low level of the common data line CD by such a bias circuit makes it possible to increase the reading speed regardless of whether the common data line CD or the like has a capacitance such as a stray capacitance that limits the signal change speed. Can be achieved.

However, in the addressing of the memory array, when the FAMOS transistor is connected to the unselected data line and the FAMOS transistor is in the ON state, the potential of the data line is at a low level like the ground potential of the circuit. Therefore, as shown in the timing chart of FIG. 4, by switching the address signals AX and AY, the word line is switched and the low-level data line is selected, and the FAMOS transistor coupled to the data line is turned off. In the state, a current temporarily flows from the sense amplifier SA to the data line through the common data line CD and the column switch circuit. As a result, the drain output voltage A of the amplification MOSFET Q11 performs an inversion operation in which the drain output voltage A is momentarily brought to the low level side with the above current supply operation. As a result, the read operation of the logic "0" is delayed. Further, due to the temporary inversion reading of the sense amplifier SA, the output circuit responds and a relatively large current for driving a relatively large load capacitance is caused to flow, and the ground line or the power supply voltage line of the circuit. This causes a relatively large noise to occur, and deteriorates the operation margin.

An object of the present invention is to provide a semiconductor memory device which has a high speed operation.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the read operation from the memory array is precharged to charge up the common data line of the memory array to a level near the logic threshold voltage of the sense amplifier according to the first timing signal, and the precharge circuit is delayed from the first timing signal. And a sense amplifier including an amplifier circuit that amplifies the signal on the common data line and is operated according to a second timing signal generated by

[Work]

According to the above-mentioned means, the potential of the common data line can be charged up to near the logic threshold voltage before the sense amplifier starts its operation, so that the sense amplifier can be read at high speed.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of an EPROM device to which the present invention is applied. Each circuit element in the figure is formed by a known CMOS integrated circuit manufacturing technique, but is not particularly limited, and is formed on one semiconductor substrate such as single crystal silicon.

Although not particularly limited, the EPROM device of this embodiment is provided with eight data input / output terminals so that 8-bit data can be written and read. EP
The ROM device is operated with a power supply voltage such as +5 volts and a high level write voltage Vpp such as ten and several volts. The EPROM device is operated by a power supply voltage Vcc such as + 5V in a normal read operation. The EPROM device has an external address signal supplied via an address input terminal and control terminals ▲ ▼, ▲ ▼, ▲ ▼
The operation is controlled by a chip enable signal, an output enable signal, and a program signal supplied via the.

In this embodiment, since 8-bit data writing / reading is performed as described above, there is no particular limitation.
A set of memory array M-ARY and a data input / output circuit are provided, but in FIG.
-ARY and the data input circuit DIB and the data output circuit DOB are shown as representatives. Memory array M-AR
Y is a number of FAMOS transistors (non-volatile memory element
・ MOSFETs Q1 to Q6), word lines W1 and W2, and data lines D1 and D2
~ Dn and. FAMOS transistors Q1 to Q3 arranged in the same row in the memory array M-ARY
The control gates of (Q4 to Q6) are connected to the corresponding word lines W1 (W2), and FAMOs are arranged in the same column.
The S transistors Q1 and Q4, Q2 and Q5, Q3, and the drain are connected to the corresponding data lines D1 to Dn, respectively.

The common source line CS of the FAMOS transistor is grounded via a depletion type MOSFET Q10 which receives a write signal {circle over ()}, although not particularly limited. This MOSFET Q
10 is provided for the following reasons. That is, when writing data to a memory cell, such as Q1, a high voltage at the write level is applied to the word line W1 and the data line
A high voltage is applied according to the data to be written to D1.
In this case, the floating gate of the memory cell Q4, which is coupled to the selected data line D1 and is to be deselected, causes an undesired electrostatic coupling with the data line D1 and the data line D1 to bring it to a high potential. Accordingly, the potential is undesirably raised. As a result, the memory cell Q4 that should be kept in the off state due to being unselected undesirably becomes conductive. That is, a leak current flows in the memory cell that should be unselected, and the memory cell Q1 that should be selected is
The write current that should flow to the memory is reduced. Illustrated
MOSFET Q10 has the above internal control signal during writing.
Its low level makes its conductance relatively small. As a result, the potential of the common source line CS generated by the write current flowing at the time of writing becomes
By setting the conductance of 0 to be relatively small, a relatively high potential is obtained. When the potential of the common source line CS is made relatively high, the threshold voltage of the FAMOS transistor is made relatively high by the substrate effect. Thus, as a result of increasing the effective threshold voltage of the FAMOS transistor to be unselected, the leak current flowing in the FAMOS transistor to be unselected can be reduced. As a result, the write current generated by the write high voltage is efficiently supplied to the selected FAMOS transistor, so that an efficient write operation can be performed. During the read operation, the conductance of the MOSFET Q10 is made relatively large due to the high level of the control signal ▲ ▼. As a result, the current flowing through the FAMOS transistor for writing logical "1" can be increased, and the reading speed can be increased.

The EPROM device of this embodiment includes address buffers XADB and YADB which receive X and Y address signals supplied through external terminals (not shown). The complementary address signals formed by the address buffers XADB and YADB are sent to the address decoder XD.
Supplied to CR and YDCR. In the figure, the X address buffer XADB and the X address decoder XDCR are shown together as a circuit block XADB.DCR, and the Y address buffer YADB and the Y address decoder YDCR are shown together as a circuit block YADB.DCR.

Although not particularly limited, the above address buffers XADB and YADB
Is a chip selection signal ce formed by the control circuit CONT.
By being activated by, the address signal from the external terminal is taken in and a complementary address signal composed of an internal address signal having the same phase as the address signal supplied from the external terminal and an address signal having the opposite phase is formed.

The X address decoder XDCR forms a selection signal to be supplied to the word line of the memory array M-ARY (the same applies to other memory arrays not shown) according to the complementary address signals supplied thereto. X address decoder XDCR
Is operated by a power supply voltage of + 5V, but is not limited thereto. Therefore, the X address decoder XDCR forms a 5 volt system select signal. On the other hand, the level of the selection signal required by the memory array M-ARY is
In the read operation, for example, the high level is approximately 5V and the low level is approximately 0V, and in the write operation, the high level is approximately the write voltage Vpp level and the low level is approximately 0V. Output from X address decoder XDCR
In order to set the word lines of the memory array M-ARY to the required levels in response to the 5V system selection signal, X
The output part of the address decoder XDCR is provided with a level conversion circuit using the high voltage Vpp as an operating voltage.

In FIG. 1, a common data line CD is provided for the memory array M-ARY. Data line of memory array M-ARY and common data line corresponding to the memory array
Between the CD and MOSFET Q7 which forms the column switch circuit
~ Q9 is provided.

The Y address decoder YDCR forms a selection signal for selecting the data line of the memory array M-ARY according to the complementary address signal supplied thereto. Y address decoder
The YDCR is operated by a power supply voltage of 5V system like the X address decoder XDCR. The selection signal output from the Y address decoder YDCR is used for controlling the column switch circuit. Here, the column switch circuit is required to have the ability to transmit a write signal at a write voltage level in the write operation. Column switch MOSFET
In order to be able to turn on and off sufficiently,
The output part of the Y address decoder XDCR is provided with a level conversion circuit using the high voltage Vpp as an operating voltage.

The common data line CD is provided with a first-stage amplifier circuit which will be described next and constitutes an input stage circuit of the sense amplifier SA.

The common data line CD is provided with an N-channel type amplification MOSFET Q11 whose source is connected. This amplification MOS
A P-channel type load MOSFET Q12 is provided between the drain of the FET Q11 and the power supply voltage terminal Vcc. The voltage of the common data line CD is supplied to the gate of the drive MOSFET Q13 which is the input of the inverting amplifier circuit including the N-channel drive MOSFET Q13 and the P-channel load MOSFET Q14.
The output voltage of the inverting amplifier circuit is supplied to the gate of the amplifier MOSFET Q11 which is the input of the amplifier circuit composed of the MOSFETs Q11 and Q12. Furthermore, in order to prevent unnecessary current consumption during the non-operation period of the sense amplifier, an N-channel MOSF is provided between the gate of the amplification MOSFET Q11 and the ground potential point of the circuit.
ETQ15 is provided. The operation timing signal (2) of the common sense amplifier is supplied to the gate of the MOSFET Q15 and the P-channel MOSFET Q14 which constitutes the inverting amplifier circuit.

In this embodiment, in order to speed up the read operation,
The common data line CD is provided with the following precharge circuit. The precharge circuit is composed of a circuit similar to the input stage circuit. That is, N channel MO
SFET Q18 and P-channel MOSFET Q19 correspond to the above inverting amplifier circuit, and N-channel MOSFET Q16 and P-channel MOSFE
The TQ17 corresponds to the above amplifier circuit. The N-channel MOSFET Q20 corresponds to the above MOSFET Q15. However, the element constant of this precharge circuit is slightly different from that of the first-stage circuit. When the potential of the common data line CD reaches a relatively low level by setting the gain of the inverting amplifier circuit of the precharge circuit to a relatively large value, the MOSFET Q16 is turned off early. The timing signal {circle around (1)} supplied to the gates of the MOSFETs Q19 and Q20 is generated at a timing earlier than the timing signal {circle around (2)}. In other words, the operation timing of the precharge circuit is earlier than the operation timing of the sense amplifier SA. Furthermore, MOSEFTQ1
6 and Q17 set the potential of the common data line CD to a desired potential at high speed, so that the current supply capability is made larger than that of the first-stage amplifier circuit.

The amplifying MOSFET Q11 performs an amplifying operation of the gate grounded source input, transmits the output signal A to the CMOS inverter circuit, and performs high level / low level discrimination with the logic threshold voltage of the inverter circuit as a reference voltage. . The output signal of the sense amplifier SA is sent from the external terminal I / O via the data pressure buffer DOB.

Further, the write signal supplied from the external terminal I / O is transmitted to the common data line CD via the data input buffer IB which is operated in the write operation mode.

Timing control circuit CONT has external terminals ▲ ▼, ▲
Internal control signals ce, ▲ according to the chip enable signal, output enable signal, program signal and high voltage for writing supplied to ▼, ▲ ▼ and Vpp.
Timing signals such as ▼, ▲ ▼ 1, and ▲ ▼ 2, and read voltage Vcc / that is selectively supplied to the address decoder.
A high voltage Vpp for writing is formed. For example, if the chip enable signal ▲ ▼ is low level, the output enable signal ▲ ▼ is high level, and the program signal ▲ ▼ is low level, the write mode is set,
The internal signal ▲ ▼ is set to low level and ce is set to high level. In addition, the chip enable signal ▲ ▼ is low level, the output enable ▲ ▼ is low level, the program signal ▲ ▼ is high level, and Vpp is in the verify mode from the high voltage for writing, and the internal signals ▲ ▼ and ce are high. Be leveled. Further, the chip enable signal ▲ ▼ is low level, the output enable signal ▲ ▼ is low level, the program signal ▲ ▼ is high level, and Vpp is in the read mode from the read low voltage.
ce goes high.

An example of the read operation of this embodiment will be described below with reference to the timing chart shown in FIG.

When the address signals AX and AY are supplied and the chip enable signal ▲ ▼ is set to low level, the address decoder X
-DCR and Y-DCR select one memory cell. The selected memory cell has a high threshold voltage or a low threshold voltage with respect to the word line selection level according to the write data.

In the worst case described above, in the previous read cycle, the data line that was brought to the ground potential of the circuit is selected and the memory cell coupled to it is turned off regardless of the word line selection level. Timing signal generated before SA operation starts ▲ ▼
The precharge circuit operates by 1 and the common data line CD
Is rapidly precharged to a constant level through MOSFT Q17 and Q16. After this, the timing signal ▲
(2) is generated and the sense amplifier SA is activated. If the memory cell is off as described above, the common data line CD
It is further charged up by a minute voltage via the MOSFETs Q12 and Q11 to make its drain output A high level. As a result, the signal of the output signal A does not drop significantly due to the current supply to the common data CD, so that a high-level output signal can be obtained at high speed. Further, since the output signal A does not change, the output circuit does not flow an undesired charge-up or discharge current to the load capacitance. As a result, at the operation timing of the sense amplifier SA, noise is not generated in the circuit ground line and the power supply line, so that the operation margin can be improved.

When the selected memory cell is turned on by the word line selection level, the common data line CD is set to a relatively low level also by the operation of the precharge circuit. In this case, the high level of the common data line CD means that the output voltage of the relatively low level formed by the precharge circuit or the inverting amplifier circuit of the sense amplifier SA is MOSFET Q1.
Limited to a relatively low potential by being supplied to the gates of 6 and Q11. On the other hand, the low level of the common data line CD is limited to a relatively high potential by supplying the gate of the MOSFET Q11 with a relatively high level voltage formed by an inverting amplifier circuit which receives the low level potential. By limiting the high level and the low level of the common data line CD, the reading speed can be increased regardless of the stray capacitance or the like that limits the signal change speed in the common data line CD. You can Suawachi,
In the case of reading data from a plurality of memory cells one after another, it is possible to shorten the time until one level of the common data line CD is changed to the other level.

The effects obtained from the above-described embodiment are as follows. That is, (1) by providing the common data line with a precharge circuit that operates at an early timing and has a level limiter function, a current for precharging the common data line is supplied to the sense amplifier that is subsequently operated. You can do it without flowing. As a result, in reading the memory cell in the off state, a temporary inversion signal is not output to the output of the sense amplifier, so that the operation can be speeded up.

(2) Since the above (1) can prevent a temporary inverted signal from being output to the output of the sense amplifier, the output circuit is charged up or discharged with a relatively large load capacitance at the operation timing of the sense amplifier. Therefore, it is possible to prevent a relatively large current from flowing. As a result, noise can be prevented from occurring in the power supply line or the ground potential of the circuit, so that the operation margin can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, the precharge circuit may be any circuit that uses a circuit similar to the above-described sense amplifier, and may be any circuit that sets the potential of the common data line to a desired potential according to a timing signal. Also,
A delay circuit including an inverter circuit or the like may be provided between the precharge circuit and the sense amplifier SA to form a timing signal supplied to the sense amplifier side delayed from the operation timing signal of the precharge circuit. . The EPROM device may be built in a one-chip microcomputer.

In the above description, the case where the invention made by the inventor of the present application is mainly applied to the EPROM device which is the technical field of the background has been described, but the invention is not limited to this, and MNOS (metal nitride oxide) is used. -Semiconductor) or mask type ROM, which can be widely used for a semiconductor memory device including a memory element having a relatively high threshold voltage or a low threshold voltage according to stored information.

〔The invention's effect〕

The following is a brief description of an effect obtained by the representative one of the inventions disclosed in the present application. That is, by providing a precharge circuit that precharges the common data line to a desired level at an early timing, the precharge circuit is operated at a slower speed and an undesired inverted output is temporarily output to the output of the sense amplifier having the level limiter function. It can be prevented from being output. As a result, the effect that the read operation can be speeded up is obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an EPROM device to which the present invention is applied, FIG. 2 is a timing diagram showing an example of the operation, and FIG. 3 is a sense amplifier considered prior to the present invention. FIG. 4 is a circuit diagram showing an example, and FIG. 4 is a timing diagram showing an example of the operation. XADB / DCR ... X address buffer / decoder, YADB / D
CR ... Y address buffer / decoder, M-ARY ... memory array, SA ... sense amplifier, DOB ... data output circuit, DIB ... data input circuit, CONT ... control circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor, Yoshiaki Tomae, 1448, Kamimizumoto-cho, Kodaira-shi, Tokyo Inside Hitachi Ultra ESI Engineering Co., Ltd. (72) Inventor, Kazuo Yoshizaki, Kamimizumoto-cho, Kodaira, Tokyo 1448 Address Musashi Plant, Hitachi, Ltd. (56) References Japanese Patent Laid-Open No. 59-79492 (JP, A)

Claims (1)

[Claims] 1. A memory array formed by arranging storage elements arranged in a matrix so as to have a relatively high threshold voltage or a relatively low threshold voltage according to stored information.
The common data line is commonly provided to the data line of the memory array via a column switch, the first amplification MOSFET whose source is coupled to the common data line, and the common data according to the first timing signal. A first inverting amplifier circuit for amplifying a voltage signal on the line and transmitting it to the gate of the first amplifier MOSFET, and a precharge circuit including first load means provided in the drain of the first amplifier MOSFET; A second amplifying MOSFET whose source is coupled to a common data line of the memory array and a second timing signal generated later than the first timing signal, amplifying the voltage signal of the common data line to amplify the voltage signal of the common data line. Amplification of 2
An amplifier circuit including a second inverting amplifier circuit for transmitting to the gate of the MOSFET and a second load means provided for the drain of the second amplifier MOSFET, and transmitting the drain output of the second amplifier MOSFET to the next stage circuit. A semiconductor memory device comprising: a sense amplifier including: