JPH0754826B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an element isolation method using a dielectric.

[Technical background of the invention and its problems]

Compared to pn junction isolation, the so-called dielectric isolation method in which conventional ICs and LSIs are used to isolate elements from each other with an insulator can (1) greatly reduce leakage current, and (2) increase breakdown voltage. It has advantages such as that (3) it is not necessary to pay attention to the direction of voltage application.

The ideal dielectric isolation is achieved by completely wrapping each element with an insulator except for the electrode connections. Such an element can be formed using, for example, an SOS substrate in which silicon is epitaxially grown on sapphire. However, sapphire is expensive, and the crystal matching with silicon is not perfect, so that a high-quality single crystal film cannot be obtained, and the film thickness cannot be increased sufficiently. There is a limit.

Many dielectric isolation methods that do not use an insulating substrate such as sapphire have been proposed so far. An example thereof will be described with reference to FIGS.

First, FIG. 3 (a) shows a plurality of silicon single crystal substrates 31 formed by anisotropic etching using an alkaline etching solution having a normal crystal orientation (100) plane as a main surface and an etching rate difference depending on the crystal plane orientation. An isolation V-shaped groove 32 is formed, and an insulating film 33 such as a SiO ₂ film is formed on the entire surface as shown in FIG. 3B.
Cover with. Thereafter, as shown in FIG. 3C, a polycrystalline silicon support layer 34 is deposited on the insulating film.

Next, the front and back are reversed, and the silicon substrate 31 is scraped off by polishing etching or the like until each single crystal is completely separated. Then, as shown in FIG. 3 (d), inside the separated single crystal
Semiconductor layers 35 (a) and (b) are formed on 31 (a) and (b) to obtain a dielectrically separated element.

The biggest problem with such a conventional method is that the formation of a support layer is essential. Not only extra steps such as deposition of the support layer and removal of abnormal deposits (protrusions) are required, but even in the case of commonly used polycrystalline silicon, the deposition rate is slow, so it can withstand polishing and other steps. It takes a very long time to obtain sufficient thickness to obtain. Furthermore, warpage occurs due to the difference in thermal expansion coefficient between this polycrystalline silicon and single crystal silicon, and in some cases deformation due to warpage of several hundreds of microns occurs, making the PEP process of forming the support layer difficult and making the product yield extremely high. Had a bad drawback.

[Object of the Invention]

The present invention has been made in view of the above points, and an object of the present invention is to provide a method of manufacturing a semiconductor device that enables highly reliable dielectric isolation with simple steps.

[Outline of Invention]

According to the present invention, when the surfaces of two semiconductor single crystal substrates are mirror-polished to be sufficiently smooth, a strong substrate bonded body can be obtained by directly adhering the polished surfaces to each other in a sufficiently clean atmosphere. Based on our findings, we apply this technique to dielectric isolation. The essence of the present invention is to use a bonded body in which an insulating film is interposed between two semiconductor single crystal substrates, and anisotropy with an alkaline etching solution with the crystal plane (100) of one of the semiconductor single crystal substrates as the main surface. In the case where a separation V-shaped groove is provided by an etching technique to form a plurality of separated single crystal islands, the width W of the separation V-shaped groove and the thickness t of the single crystal island are (Here θ is relative to the groove running in the <110> direction on the (100) plane.
The characteristic is that they are formed and arranged in a relationship of 54.7 °, a = 0.2).

〔The invention's effect〕

According to the present invention, since a single crystal strong substrate joined body directly bonded via an insulating film is used, warpage of the substrate can be ignored, and high temperature heat treatment step or polishing step after the substrate joined body is formed. There is no influence. Further, by defining the width W between the island-shaped single crystals (width of the V-shaped groove for separation) and the thickness t, a dielectric isolation structure having a high degree of integration and high reliability can be realized. Furthermore, since the surface of the substrate is flattened, it is possible to provide an inexpensive semiconductor device in which electrode wiring is easy and the yield is high.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment in which a V-shaped groove for separation is formed. FIG. 1A is a perspective view and FIG. 1B is an A in FIG.
7 is a cross-sectional view taken along line A-A '. When the single crystal silicon substrate 10 having the crystal plane (100) as the main surface is etched using an alkaline aqueous solution, the crystal plane (100) has a high etching rate as shown in FIG. 1 (a). 111)
However, since the etching rate is very slow, it is possible to perform anisotropic etching utilizing the difference in etching rate depending on the crystal plane. When this anisotropic etching is performed using, for example, an oxide film (SiO ₂ ) as the mask material 13, a V-shaped groove having an angle θ determined by the crystal planes (100) and (111) is formed. Two semiconductor single crystal substrates shown in FIG. 1 (b)
In the case of a substrate joined body in which the insulating film 11 is interposed between 10 and 12,
To form a single crystal island by the separating V-shaped groove 14,
The relationship between the separation V-shaped groove width W and the island thickness t is Under the condition that the thickness t is larger than the left side, the V-shaped groove for isolation does not reach the insulating film, and electrical isolation becomes impossible. On the other hand, when constructing a semiconductor integrated circuit on such a substrate assembly, it is necessary to minimize the pellet size. In order to minimize the size of the pellet, the minimum size required for each component of the semiconductor integrated circuit in terms of electrical characteristics and the thickness of insulating and isolated single crystal islands are formed at high density. There is a need. Therefore, in order to solve the above-mentioned problem, the relationship between the width V of the V-shaped groove for separation and the thickness t of the island should be expressed as (W / 2) · tan θ> t ≧ (W / 2) (1-a) · tan θ θ : 54.7 ° (angle) a: 0.2 (constant)

FIGS. 2 (a) to 2 (h) are views showing an example of manufacturing a photodiode array using the present invention.
Fig. 2 (a) shows the surface index (100) and resistivity 10 to 20 Ω · cm.
1-1.5μ of thermal oxide film 11 on N-type silicon single crystal substrate 10 of
Prepare the formed product. Next, as shown in FIG. 2 (b), the surfaces of the substrate 10 and the other single crystal substrate 12 facing each other are mirror-polished side-to-face, and heat-bonded at a temperature of 200.degree. Let One substrate 10 of the substrate bonded body thus formed is ground by polishing, etching or the like to a thickness of 60 ± 5 μm, and a thermal oxide film 13 of 5000 Å is formed as a mask material, as shown in FIG. 2 (c). Get the structure.
A PEP that is generally known by using a glass mask designed so that the distance between the arrayed photodiodes is 100 μm.
By the process, a grid-like opening having a width of 100 μm is formed in a part of the oxide film 13, and anisotropic etching is performed at a temperature of about 80 ° C. using an alkaline etching solution containing KOH as a main component with the oxide film as a mask. As shown in FIG. 2 (d), single crystal islands 10 (a)-(c) are formed by the V-shaped grooves 14 (a) and 14 (b) for separation. As shown in FIG. 2 (e), the surface of the single crystal separated into islands is thermally oxidized.
15 is formed to have a thickness of 1 to 1.5 μm, and polycrystalline polysilicon 16 is deposited thereon to a thickness of about 60 μm as shown in FIG. 2 (f). Next, polishing is carried out from the polycrystalline polysilicon side until the thickness of the single crystal island is reduced to 50 μm, and the islands are ground and etched to complete the dielectric isolation substrate shown in FIG. 2 (g). Then, P-type impurities such as boron and N-type impurities such as phosphorus are introduced into the dielectric-isolated single-crystal island 10 (b) to form P-type layer 17 and N-type layer 18, respectively. Then, the photodiode shown in FIG. 2 (h) is formed. A photodiode array is completed by connecting a plurality of photodiodes configured in this way in series by wiring electrodes.

As described above, according to the embodiments of the present invention, a highly reliable semiconductor device having a dielectric isolation structure can be easily manufactured. The greatest feature of the present invention is that when a semiconductor body having two semiconductor single crystal substrates with an insulating film interposed is used and one of the semiconductor single crystal substrates has a crystal plane (100) as a main surface, a V-shape for separation is provided. By defining the maximum groove width W formed by the groove and the thickness t of the single crystal island, it is possible to manufacture a photodiode array having a high degree of integration and a high yield and having a dielectric isolation.

In the above embodiment, the insulating film is formed on one of the semiconductor single crystal substrates before forming the substrate joined body, but the present invention is also applicable to the case where the substrate joined body is formed after forming the insulating films on both substrates. You can Further, although the photodiode array has been described in the above embodiment, a transistor, a thyristor, a MOSFET or the like can be formed.

[Brief description of drawings]

FIG. 1 is a diagram for explaining conditions for forming a V-shaped groove for separation according to an embodiment of the present invention, FIG. 2 is a diagram showing an element manufacturing process of an embodiment according to the present invention, and FIG. It is a figure which shows the element manufacturing process by a dielectric separation method. 10 …… Semiconductor single crystal substrate with crystal plane (100) as main surface 11 …… Insulating film 12 …… Semiconductor single crystal substrate 13 …… Mask material (thermal oxide film) 14 …… V-shaped groove for separation 15 …… Insulation film 16 Polycrystalline silicon layer 17 P-type layer 18 N-type layer

Claims (1)

[Claims] 1. At least a first semiconductor single crystal substrate is covered with an insulating film, first and second semiconductor single crystal substrates to be bonded are brought into close contact with each other in a clean atmosphere, and heat treated at a temperature of 200 ° C. or higher. Bonding step, a step of polishing and removing the surface of the bonded first semiconductor single crystal substrate to a predetermined thickness, and an insulating film from the polished first semiconductor single crystal surface using an alkaline etching solution. Forming a first semiconductor single crystal island, a step of covering the surface of the first semiconductor single crystal island again with an insulating film, and a step of burying polycrystalline silicon in the groove portion. Then, polishing is further performed flatly until the surface of the island of the semiconductor single crystal is exposed, and at least one or more P-
A method of manufacturing a semiconductor device having an N-junction, comprising:
The thickness t of the first semiconductor single crystal and the width W of the groove are (W / 2) · tan θ> t ≧ (W / 2) (1-a) · tan θ (where θ is the (100) plane. For grooves running in the <110> direction
54.7 °, a = 0.2).