JPH0754913B2 - Data conversion circuit - Google Patents

Description

The present invention relates to a data conversion circuit.

[Conventional technology]

Conventionally, the format of the input data is converted (for example,
The data conversion circuit shown in FIG. 4 has been used as a data conversion circuit for converting the data word length and reversing the upper and lower sides. Fourth
In the figure, 1 _-1 to 1 _-l is a data input terminal for inputting input data, 2 _-1 to 2 _-m is a control data input terminal for inputting control data, 3 is a clock input terminal for inputting a clock signal, 4
_-1 to 4- _n are data output terminals for outputting the converted data, and are composed of a conversion unit 5 and a control unit 6 '.

The conversion unit 5 includes at least one delay circuit 51 and the delay circuit.
The gate circuit 52 _-k (1 ≤ k ≤ where the output of 51 is input from the first input terminal, the output is converted and output from the output terminal.
i) is a unit circuit 50 _-k , and i stages are cascade-connected. That is, in the unit circuit 50 _{-1 of the} first stage, the input terminal of the delay circuit 51 is connected to the data input terminals 1 _-1 to 1 _-l, and the output terminal of the gate circuit 52 _-1 of the unit circuit 50 _-2 of the next stage. connected one after the other so that they are connected to the input terminal of the delay circuit 51, the unit circuit 50 _-i in the final stage, the output terminal of the gate circuit 52 _-i is connected to the data output terminal 4 _-1 to 4 _-n Has been done.

On the other hand, the control unit _{6'corresponds to} the unit circuit 50 _-k of the conversion unit 5,
Has a gate circuit 62 _-k, the gate circuits 62 to _-k input terminal control data input terminal 2 _-1 to 2 _-m, gate circuits of the respective output terminals each unit circuit 50 _-k 52 _{- It} is connected to the second input terminal of _k and supplies conversion control data to each unit circuit 50 _-k .

The clock signal supplied from the clock input terminal 3 is connected to the clock input terminal of each delay circuit 51. Also, the number of inputs and outputs of the unit circuit 50 _-k at each stage is
Note that they are generally different. For example, the number of the first input terminals of the gate circuit 52 _-1 of the first-stage unit circuit 50 _-1 is 1, but the number of the second input terminals and output terminals thereof is not always l. Absent. Similarly,
The number of output terminals of each gate circuit 62- _k of the control unit 6'is also generally different.

Compared with the conventional data conversion circuit having the above general structure,
The operation of the conventional data conversion circuit will be described with reference to the time chart of FIG. 6 by showing a concrete example in the figure.

FIG. 5 shows an example of a three-stage data conversion circuit, in which the data input terminal, the control data input terminal and the data output terminal are shown as 1, 2, and 4, respectively, and the clock input terminal is omitted. Also, the delay circuit 51 is shown as a representative one in each stage.

Input data x is input from the data input terminal 1. Control data h [g {f ()}] is input from the control data input terminal 2. Each gate circuit 62 _-1 , 62 _-2 and 62 of the control unit 6 '
_-3 inputs control data h [g {f ()}], respectively, and converts control data f (), g {} and h [].
_Is output to the gate circuits 52 _-1 , 52 _-2 , and 52 _-3 of the conversion unit 5.

The gate circuit 52 _-1 of the unit circuit 50 _{-1 in} the first stage converts the input data x input via the delay circuit 51 into f (x) by the conversion control data f () from the gate circuit 62 _-1. do it,
Output to the next unit circuit 50 _-2 . Second stage unit circuit 50 _-2
The gate circuit 52 _-2 of the gate circuit 52 _-2 converts the data f _(x) input via the delay circuit 51 into the control data g for conversion from the gate circuit 62 _-2.
Converted to g {f _(x) } by {}, and the final stage unit circuit
Output to 50 _-3 . Final stage unit circuit 50 _-3 gate circuit 52
_-3 is the data g {f _(x) } input via the delay circuit 51.
_Is converted into h [g {f _(x) }] by the conversion control data h [] from the gate circuit _62-2 and output to the data output terminal 4. Here, the control data h [g {f _{( )} }] is b
₁ [g ₁ {f _{1 ( )} }], h ₁ [g ₁ {f _{2 ( )} }], ..., h ₃ [g ₃
It is assumed that there are 27 types of {f _{2 ( )} }] and h ₃ [g ₃ {f _{3 ( )} }], and accordingly, the gate circuit 62 _-1 has f ₁ (), f
₂ () and f ₃ (), and the gate circuit 62 _-2 uses g ₁ {}, g ₂
{} And g ₃ {}, the gate circuit 62 _-3 uses h ₁ [], h ₂
[] And h ₃ [] shall be output.

Referring to FIG. 6, at timing T ₁ , input data x ₁ is input from data input terminal 1 and control data h ₁ [g ₃ {f ₂ ()}] is input from control data input terminal 2. At the same time, the gate circuits 62 _-1 , 62 _-2 and 62 _-3 of the control unit _6'are
Output f ₂ (), g ₃ {} and h ₁ [] respectively.
At the next timing T ₂ , the gate circuit 52 _-1 outputs f ₂ (x ₁ ), and at the timing T ₃ , the gate circuit 52 _-2 outputs g ₃ {f
₂ (x ₁ )} is output, and at timing T ₄ , the gate circuit 52 _-3
Outputs h ₁ [g ₃ {f ₂ (x ₁ )}]. Timing T _{1 to} T ₄
During this period, the control data input from the control data input terminal 2 is held in h ₁ [g ₃ {f ₂ ()}]. Then, at the next timing T ₅ , the input data x ₂ is input from the input terminal 1 and the control data h ₃ [g ₃ {f ₁ ()}] is input from the control data input terminal 2, and the same operation as described above is performed. Repeated. Therefore, conversion data is obtained every four clock cycles.

[Problems to be solved by the invention]

Thus, in the conventional data conversion circuit, the gate circuit 52
_Since the operation of _{-1 to} 52 _-i immediately responds to the control data from the control data input terminals 2 _-1 to 2 _-m , the data input terminal
Until one input data input from 1 _-1 to 1 _-l completes the processing in all gate circuits 52 _{-1 to} 52 _{-i and} is output to the data output terminals 4 _-1 to 4- _n , Control data input terminal
It is necessary to fix the control data input to 2 _{-1 to} 2 _-m . Therefore, there is a drawback in that data with different conversion control cannot be continuously input, the temporal data conversion efficiency decreases, and the conversion speed decreases.

[Means for solving problems]

As shown in FIG. 1, the data conversion circuit according to the present invention converts input data from at least one data input terminal 1 _-1 to 1 _-l from at least one data output terminal 4 _-1 to 4 _-n. And a control unit 6 for inputting control data from at least one control data input terminal 2 _-1 to 2- _m .

The conversion unit 5 includes at least one delay circuit 51 and the delay circuit.
The gate circuit 52 _-k (1 ≤ k ≤ where the output of 51 is input from the first input terminal, the output is converted and output from the output terminal.
i) is a unit circuit 50 _-k , and i stages are cascade-connected. That is, in the unit circuit 50 _{-1 of the} first stage, the input terminal of the delay circuit 51 is connected to the data input terminals 1 _-1 to 1 _-l, and the output terminal of the gate circuit 52 _-1 of the unit circuit 50 _-2 of the next stage. connected one after the other so that they are connected to the input terminal of the delay circuit 51, the unit circuit 50 _-i in the final stage, the output terminal of the gate circuit 52 _-i is connected to the data output terminal 4 _-1 to 4 _-n Has been done.

On the other hand, the control unit 6 includes at least one delay circuit 61 having the same delay time as that of the delay circuit 51 of the unit circuit 50 _-k and the delay circuit 61 corresponding to the unit circuit 50 _-k of each stage of the conversion unit 5. And a gate circuit 62 _-k for converting the output of 61 into the control data for conversion and outputting it to the second input terminal of the gate circuit 52 _-k . The input terminal of the delay circuit 61 in the first stage is the control data input terminal.
Is connected to the 2 _-1 to 2 _-m, they are connected in cascade in this order in order to that the output terminal of the first delay circuit 61 is connected to an input terminal of the next stage delay circuit 61.

Also, the clock signal supplied from the clock input terminal is
The clock input terminals of each delay circuit 51 and each delay circuit 61 are connected.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a diagram showing the configuration of an embodiment of the data conversion circuit according to the present invention, and the same components as those in FIG. 5 are designated by the same reference numerals. The difference from FIG. 5 is that the control unit 6 is provided with a delay circuit 61 in front of the gate circuits 62 _-1 , 62 _-2 and 62 _-3 .

FIG. 3 is a time chart for explaining the operation of the circuit of FIG.

In the timing T _1, the input data x ₁ from the data input terminal 1, the control from the control data input terminal 2 data h ₁ [g
₃ Enter {f ₂ ()}].

At the next timing T ₂ , the gate circuit 62 _-1 outputs conversion control data f ₂ (), and the first-stage gate circuit 52 _-1 converts the input data x ₁ input via the delay circuit 51 for conversion control. data
It is converted to f ₂ (x ₁ ) by f ₂ () and the next unit circuit 5
Output to 0 _-2 . The data input terminal 1 receives the next input data x ₂ and the control data input terminal 2 receives the next control data h ₃
Enter [g ₂ {f ₁ ()}].

At the next timing T ₃ , the gate circuit 62 _-1 outputs conversion control data f ₁ (), and the first-stage gate circuit 52 _-1 converts the input data x ₂ input via the delay circuit 51 for conversion control. data
It is converted to f ₁ (x ₂ ) by f ₁ () and the next unit circuit 5
Output to 0 _-2 . At the same time, the gate circuit 62 _-2 outputs the first conversion control data g ₃ {}, and the gate circuit 52 of the next stage outputs.
_-2 is a unit circuit in the final stage, which converts the data f ₂ (x ₁ ) input via the delay circuit 51 into g ₃ {f ₂ (x ₁ )} by the conversion control data g ₃ {}. Output to 50 _-3 . Input data x ₃ is input to the data input terminal 1, and control data h ₂ [g ₂ {f ₃ ()}] is input to the control data input terminal 2.

At timing T ₄ , the gate circuit 62 _-1 converts the control data for conversion.
f ₃ () is output, and the first-stage gate circuit 52 _-1 is a delay circuit
The control data f ₃ for converting the input data x ₃ input via 51
Converted to f ₃ (x ₃ ) by () and the next unit circuit 50
Output to _-2 . At the same time, the gate circuit 62 _-2 outputs the conversion control data g ₂ {}, and the gate circuit 52 _-2 at the next stage controls the conversion of the data f ₁ (x ₂ ) input via the delay circuit 51. The data g ₂ {} is converted into g ₂ {f ₁ (x ₂ )} and output to the final unit circuit 50 _-3 . Furthermore, the gate circuit 62 _-3
Outputs the _first control data for conversion h ₁ [], and the gate circuit 52 _-3 at the final stage outputs the data g ₃ input via the delay circuit.
The {f ₂ (x _1)} conversion control data h ₁ a [], h ₁ [g
₃ {f ₂ (x ₁ )}] and output to the data output terminal 4. The input data x ₄ is input to the data input terminal 1, and the control data h ₃ [g ₁ {f ₁ ()}] is input to the control data input terminal 2.
To enter.

The above operation is repeated, and at timing T ₅ , h ₃ [g ₂ {f ₁ (x ₂ )}] from the data output terminal 4, and at timing T ₆ from the data output terminal 4 h ₂ [g ₂ {f ₃ (x ₃ )}] are sequentially output. That is, in the data conversion circuit of the present invention, the control data is transferred in synchronization with the transfer of the input data to the next stage, and is transferred and stored until the data conversion is completed. Therefore, the timing T ₄ and later converted data for each clock cycle is obtained.

〔The invention's effect〕

As described above, according to the present invention, the control data is
Control data to be input to the control data input terminal can be transferred by delaying in the same manner in synchronization with the transfer and delay of input data and holding it until all data conversion is completed.
There is no need to fix it until all data conversion is complete. Therefore, it is possible to continuously input data with different conversion control, which has the effect of increasing the temporal data conversion efficiency and obtaining a high data conversion speed.

[Brief description of drawings]

1 is a circuit diagram showing the configuration of a data conversion circuit according to the present invention, FIG. 2 is a circuit diagram showing the configuration of an embodiment of the data conversion circuit according to the present invention, and FIG. 3 is a circuit diagram of the circuit of FIG. A time chart for explaining the operation, FIG. 4 is a circuit diagram showing a configuration of a conventional data conversion circuit, FIG. 5 is a circuit diagram showing a concrete configuration example of the conventional data conversion circuit, and FIG. Fifth
6 is a time chart for explaining the operation of the circuit in the figure. 1,1 _-1 to 1 _-l ...... Data input terminal, 2,2 _-1 to 2 _-m ...... Control data input terminal, 3 ...... Clock input terminal, 4,4 _-1 to 4 _-n ......
Data output terminal, 5 ...... Conversion unit, 50 _-1 to 50 _-i ...... Unit circuit,
51 …… delay circuit, 52 _{−1 to} 52 _-i …… gate circuit, 6 …… control unit, 61 …… delay circuit, 62 _{−1 to} 62 _-i …… gate circuit.

Claims (1)

[Claims] 1. A conversion unit for converting input data from at least one data input terminal from at least one data output terminal and outputting the converted data, and a control unit for inputting control data from at least one control data input terminal. The conversion unit has at least one first delay circuit and a first gate circuit for converting the output of the first delay circuit input from the first input terminal from the output terminal and outputting the unit. In the first stage unit circuit, the input terminal of the first delay circuit is connected to the data input terminal, and the output terminal of the first gate circuit is the input terminal of the first delay circuit of the next stage unit circuit. The unit circuits of the final stage are connected in cascade such that the output terminal of the first gate circuit is connected to the data output terminal. Pair with unit circuit Then, data conversion for supplying conversion control data for converting data input from the first input terminal of the first gate circuit to the second input terminal of the first gate circuit of the unit circuit In the circuit, the control unit corresponds to a unit circuit of each stage of the conversion unit, and at least one second delay circuit having the same delay time as that of the first delay circuit of the unit circuit; A second gate circuit for converting the output of the second delay circuit into the control data for conversion and outputting the converted control data to the second input terminal of the first gate circuit, and the input of the second delay circuit of the first stage. A terminal is connected to the control data input terminal, an output terminal of the first delay circuit of the second delay circuit is connected to an input terminal of the second delay circuit of the next step, and the terminals are connected in cascade. Characteristic data conversion circuit.