JPH0756516B2 - Electronic clock - Google Patents
Electronic clockInfo
- Publication number
- JPH0756516B2 JPH0756516B2 JP60090292A JP9029285A JPH0756516B2 JP H0756516 B2 JPH0756516 B2 JP H0756516B2 JP 60090292 A JP60090292 A JP 60090292A JP 9029285 A JP9029285 A JP 9029285A JP H0756516 B2 JPH0756516 B2 JP H0756516B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- frequency dividing
- charge storage
- storage member
- power generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010248 power generation Methods 0.000 claims description 19
- 238000001514 detection method Methods 0.000 claims description 12
- 230000010355 oscillation Effects 0.000 claims description 7
- 230000002265 prevention Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 230000005674 electromagnetic induction Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Electric Clocks (AREA)
- Electromechanical Clocks (AREA)
- Direct Current Feeding And Distribution (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、内部に発電機構と該発電機構で発電された電
力を蓄える電荷蓄積部材と該電荷蓄積部材への過充電を
抑えるリミツタ手段と該電荷蓄積部材に発生した電圧を
昇降圧する昇降圧手段と電圧検出手段を有し、その昇降
圧電圧をシステムの電源として使用する電子時計に関
し、特にそのシステムリセツト時のシステム動作に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a power generation mechanism, a charge storage member that stores electric power generated by the power generation mechanism, and a limiter unit that suppresses overcharge to the charge storage member. The present invention relates to an electronic timepiece having a step-up / step-down means for boosting / stepping down a voltage generated in the charge storage member and a voltage detecting means, and using the step-up / step-down voltage as a power source of a system, and more particularly to system operation at the time of system reset.
本発明は、内部に発電機構と該発電機構で発電された電
力を蓄える電荷蓄積部材と該電荷蓄積部材への過充電を
抑えるリミツタ手段と該電荷蓄積部材に発生した電圧を
昇降圧する昇降圧手段と電圧検出手段を有し、その昇降
圧電圧をシステムの電源として使用する電子時計におい
て、システムリセツト期間も前記電圧検出手段、昇降圧
手段及びリミツタ手段を含む電源制御部を動作させるシ
ステム構成とすることにより、システムリセツト期間で
も電源制御を可能とし、システムの信頼性を向上させる
ものである。The present invention relates to a power generation mechanism, a charge storage member that stores electric power generated by the power generation mechanism, a limiter unit that suppresses overcharging of the charge storage member, and a step-up / down unit that boosts / decreases the voltage generated in the charge storage member. An electronic timepiece having a voltage detecting means and a step-up / step-down voltage as a power source of a system, and having a system configuration in which a power supply control section including the voltage detecting means, the step-up / down means and the limiter means is operated during a system reset period. As a result, the power supply can be controlled even during the system reset period and the reliability of the system is improved.
従来電子時計は、ボタン型電池等の１次電池を使用して
動作していたが、近年時計の電池寿命を延ばすために太
陽電池等の発電機構を有し、その発電電力を２次電池に
充電して利用したり、最近では２次電池の換わりに電気
二重層コンデンサに前記発電電力を蓄えて電源とし、半
永久的に動作する電子時計も発売されている。さらに、
時計内部に電磁誘導発電機構を持ち、その発電電力を利
用する時計も考えられ、詳細は特願昭59−246778等に開
示されている。該特許に開示されているように該時計
は、その発電電力を無駄なく有効に利用するために、内
部に昇圧回路を有し電荷蓄積部材に蓄えられ発生した電
圧を昇圧し電源として利用している。Conventionally, electronic timepieces were operated by using primary batteries such as button type batteries, but in recent years, in order to extend the battery life of timepieces, there is a power generation mechanism such as a solar cell, and the generated power is supplied to a secondary battery. An electronic timepiece that is semi-permanently operated by charging and using it, or recently, by storing the generated power in an electric double layer capacitor instead of a secondary battery and using it as a power source has been put on the market. further,
A timepiece having an electromagnetic induction power generation mechanism inside the timepiece and utilizing the generated power is also considered, and the details are disclosed in Japanese Patent Application No. 59-246778. As disclosed in the patent, the watch has a booster circuit inside to boost the voltage stored in the charge storage member and use it as a power source in order to effectively use the generated power. There is.
また、このような時計は、通常動作時は前記電荷蓄積部
材に蓄えられ発生した電圧やその昇圧電圧等を電圧検出
して、それらの電圧が定格電圧以上になるとリミツタ手
段で電荷蓄積部材に過充電されないよう電流をバイパス
したり、昇圧手段の倍率を変化させ定格電圧以上になら
ないように制御されている。In addition, such a timepiece detects the voltage accumulated in the charge storage member and the generated boosted voltage during normal operation, and when the voltage exceeds the rated voltage, the limiter means causes the charge storage member to overload. The current is controlled so as not to be charged, and the voltage is controlled so as not to exceed the rated voltage by changing the magnification of the booster.
しかし、このような時計のシステムリセツト状態は一般
の時計のように発振回路及び若干の分周回路を残し、前
記電圧検出手段、昇圧手段、リミツタ手段を含めた全て
をリセツト状態としてしまう訳にはいかない。なぜなら
時計がシステムリセツト状態にあっても前記太陽電池や
電磁誘導発電機構はユーザーの扱い方しだいでいくらで
も発電をし続け、ついには各電圧が定格電圧を越え時計
の破壊へつながるからである。特にアナログ時計の場合
には時刻修正の度にシステムリセツトがかかるのでこの
危険性は大きなものとなる。また、システムリセツト時
に前記のごとき発電手段に発電をさせないようにするた
めには、大きな電流を制御しなければならずシステムに
負担がかかる上、発電を殺すというのは発電電力利用シ
ステムとしては非常に具合が悪い。However, the system reset state of such a timepiece does not mean that the oscillation circuit and some frequency dividing circuits are left as in a general timepiece, and all of the voltage detecting means, the boosting means, and the limiter means are put into the reset state. It doesn't. This is because even if the timepiece is in the system reset state, the solar cell and the electromagnetic induction power generation mechanism continue to generate power depending on how the user handles it, and eventually each voltage exceeds the rated voltage, leading to destruction of the timepiece. Especially in the case of an analog clock, a system reset is required each time the time is adjusted, and this risk becomes great. In addition, in order to prevent the above-mentioned power generation means from generating power during system reset, a large current must be controlled, which imposes a burden on the system. I'm sick.
本発明の電子時計は、発振回路と、 第１の分周手段と第２の分周手段からなり前記発振回路
の発振出力を分周する分周手段と、 前記第２の分周手段の出力信号を計数する時計手段と、 発電手段と、 前記発電手段により発電された電圧を蓄える電荷蓄積部
材と、 前記第１の分周手段の出力信号により制御され前記電荷
蓄積部材の電圧を検出する電圧検出手段と、 前記電圧検出手段の出力により前記電荷蓄積部材の過充
電を防止するリミッタ手段と、 前記第２の分周手段と前記時計手段とをリセット信号に
より初期化するとともに前記リセット信号発生時にも前
記電圧検出手段及び前記リミッタ手段を初期化せずに電
圧検出及び過充電防止を行う如く制御する制御手段とを
有することを特徴とする。The electronic timepiece of the present invention comprises an oscillation circuit, a first frequency dividing means, and a second frequency dividing means, which divides the oscillation output of the oscillation circuit, and the output of the second frequency dividing means. Clock means for counting signals, power generation means, charge storage member for storing the voltage generated by the power generation means, voltage for detecting the voltage of the charge storage member controlled by the output signal of the first frequency dividing means Detection means, limiter means for preventing the charge storage member from being overcharged by the output of the voltage detection means, the second frequency dividing means and the clock means are initialized by a reset signal, and when the reset signal is generated. Also includes control means for controlling the voltage detection means and the limiter means so as to detect the voltage and prevent overcharge without initializing the voltage detection means and the limiter means.
本発明の上記のシステム構成によれば、システムリセツ
ト期間中も電圧検出を行ない、昇降圧制御をしリミツタ
を動作させるので、システムリセツト中に発電機構によ
って続々と発電された電力を制御できシステムとしての
信頼性を高められ、さらに常時発電電力の有効利用が可
能となる。According to the above system configuration of the present invention, the voltage is detected even during the system reset period, the step-up / down control is performed and the limiter is operated, so that the power generated one after another by the power generation mechanism during the system reset can be controlled as a system. The reliability of the power generation can be improved, and the generated power can be effectively used at all times.
第１図は、本発明よる発電機構付電子時計のブロツク図
である。第１図において、１は特願昭59−246778に開示
されているような発電機構であり、該発電機構１による
起電力はダイオード７で整流され電荷蓄積部材３に充電
される。該電荷蓄積部材３に規定以上の電圧Vscが充電
されないように余分な電流をバイパスするリミツタ手段
と、該電圧Vscを昇降圧してバツクアツプコンデンサ５
に規定電圧範囲内の電圧Vssを充電する昇降圧手段は、V
sc及びVss電圧検出する電圧検出手段４によって制御さ
れる。６は計時手段で前記Vssを電源とし、発振回路、
分周回路、外部スイッチ制御手段、各種時計機能を含み
システム全体を制御しており、システムリセツト時は分
周回路の一部や各種時計機能にリセツトをかけ、電圧検
出手段4,リミツタ手段2,昇降圧手段８は能動状態に保持
するようになっている。第２図は、該計時手段を細分し
た本発明のシステム図である。第２図において、一点鎖
線で囲った部分が第１図の計時手段６であり、発振回路
21から出力した原振は、分周回路22,23で分周され、基
本時計、タイマー、表示等の各種時計機能24に供給され
る。なお、第２図から明らかなように、分周回路22の分
周出力は、外部スイッチ制御手段25と電圧検出手段26に
印加され、外部スイツチ制御手段25と電圧検出手段26は
同じタイミングで制御される。また、外部スイツチから
の信号は、外部スイツチ制御手段25によりコントロール
信号に変換され各種時計機能24等の制御を行ない、その
内の１つとしてシステムリセツト信号SRが出力される。
信号SRは、一部の分周回路23と各種時計機能24のみに与
えられ、電圧検出手段26,リミツタ手段27,昇圧手段28に
は与えられない。従って、時計機能の初期値設定等のシ
ステムリセツト機能にはなんら支障を与えずに、電圧制
御だけを作動させることができる。FIG. 1 is a block diagram of an electronic timepiece with a power generation mechanism according to the present invention. In FIG. 1, reference numeral 1 denotes a power generation mechanism as disclosed in Japanese Patent Application No. 59-246778. The electromotive force generated by the power generation mechanism 1 is rectified by a diode 7 and charged in a charge storage member 3. Limiter means for bypassing an excess current so that the charge storage member 3 is not charged with a voltage Vsc higher than a specified value, and a buck-up capacitor 5 for boosting / decreasing the voltage Vsc.
The buck-boost means to charge the voltage Vss within the specified voltage range is V
It is controlled by the voltage detection means 4 for detecting the sc and Vss voltages. 6 is a clocking means, which uses the Vss as a power source,
It controls the entire system including the frequency divider circuit, external switch control means, and various clock functions.At the time of system reset, a part of the frequency divider circuit and various clock functions are reset, the voltage detection means 4, the limiter means 2, The step-up / step-down means 8 is adapted to be held in an active state. FIG. 2 is a system diagram of the present invention in which the timing means is subdivided. In FIG. 2, the portion surrounded by the alternate long and short dash line is the time measuring means 6 in FIG.
The original vibration output from 21 is divided by frequency dividing circuits 22 and 23 and supplied to various clock functions 24 such as a basic clock, a timer, and a display. As apparent from FIG. 2, the frequency-divided output of the frequency-dividing circuit 22 is applied to the external switch control means 25 and the voltage detection means 26, and the external switch control means 25 and the voltage detection means 26 are controlled at the same timing. To be done. Also, the signal from the external switch is converted into a control signal by the external switch control means 25 to control various clock functions 24 and the like, and the system reset signal SR is output as one of them.
The signal SR is given only to some of the frequency dividing circuits 23 and various clock functions 24, and is not given to the voltage detecting means 26, the limiter means 27, and the boosting means 28. Therefore, it is possible to operate only the voltage control without any hindrance to the system reset function such as setting the initial value of the clock function.
本発明によれば、時計機能のリセットを行っている期間
中も電圧検出手段を制御する信号を生成する分周手段は
リセットされず、したがって電圧検出及び過充電防止回
路を動作させるため、システムリセット期間中でも発充
電を安全に且つ有効に行うことができ、発電電力の有効
利用とシステムの信頼性の向上という効果を奏するもの
である。According to the present invention, the frequency dividing means for generating the signal for controlling the voltage detecting means is not reset even during the resetting of the timepiece function. It is possible to safely and effectively generate and charge electricity even during the period, and it is possible to effectively use the generated power and improve the reliability of the system.
第１図……本発明による発電機構付電子時計のブロツク
図 第２図……本発明のシステム図 １……発電機構、３……電荷蓄積部材 2,27……リミツタ手段 4,26……電圧検出手段 8,28……昇降圧手段 ６……計時手段FIG. 1 ... Block diagram of electronic timepiece with power generation mechanism according to the present invention FIG. 2 ... System diagram of the present invention 1 ... Power generation mechanism, 3 ... Charge storage member 2, 27 ... Limiter means 4, 26. Voltage detection means 8,28 …… Buck-boost means 6 …… Timekeeping means
Claims (1)
の発振出力を分周する分周手段と、 前記第２の分周手段の出力信号を計数する時計手段と、 発電手段と、 前記発電手段により発電された電圧を蓄える電荷蓄積部
材と、 前記第１の分周手段の出力信号により制御され前記電荷
蓄積部材の電圧を検出する電圧検出手段と、 前記電圧検出手段の出力により前記電荷蓄積部材の過充
電を防止するリミッタ手段と、 前記第２の分周手段と前記時計手段とをリセット信号に
より初期化するとともに前記リセット信号発生時にも前
記電圧検出手段及び前記リミッタ手段を初期化せずに電
圧検出及び過充電防止を行う如く制御する制御手段とを
有することを特徴とする電子時計。1. An oscillation circuit, a frequency dividing means comprising a first frequency dividing means and a second frequency dividing means for dividing an oscillation output of the oscillation circuit, and an output signal of the second frequency dividing means. Clock means for counting, power generation means, charge storage member for storing the voltage generated by the power generation means, and voltage detection means for detecting the voltage of the charge storage member controlled by the output signal of the first frequency dividing means A limiter means for preventing the charge storage member from being overcharged by the output of the voltage detecting means, the second frequency dividing means and the clock means are initialized by a reset signal, and the reset signal is generated when An electronic timepiece comprising: a voltage detection means and a control means for controlling the voltage detection and the overcharge prevention without initializing the limiter means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60090292A JPH0756516B2 (en) | 1985-04-26 | 1985-04-26 | Electronic clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60090292A JPH0756516B2 (en) | 1985-04-26 | 1985-04-26 | Electronic clock |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61247993A JPS61247993A (en) | 1986-11-05 |
| JPH0756516B2 true JPH0756516B2 (en) | 1995-06-14 |
Family
ID=13994453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60090292A Expired - Lifetime JPH0756516B2 (en) | 1985-04-26 | 1985-04-26 | Electronic clock |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0756516B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54109878A (en) * | 1978-02-17 | 1979-08-28 | Seiko Instr & Electronics Ltd | Electronic watch with solar batteries |
| JPS58160377U (en) * | 1982-04-20 | 1983-10-25 | シチズン時計株式会社 | Pointer display electronic watch |
-
1985
- 1985-04-26 JP JP60090292A patent/JPH0756516B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61247993A (en) | 1986-11-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |