JPH0756619B2 - Input noise detection circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an input noise of a system in which a constant-period pulse train is used when data is “1” and a data signal that is high level or low level when data is “0” is input. The present invention relates to a detection circuit.

2. Description of the Related Art Conventionally, in this type of input noise detection circuit, an RS flip-flop is simply connected to the key matrix output in the key matrix using circuit as shown in FIG. Fifth
In the case of the figure, even if the key matrix output signal is affected by chattering, once the RS flip-flop is set, its output becomes "1", and therefore the chattering effect by the data signal is not exerted. Also, the RS flip-flop is reset by a reset signal from the system at appropriate times. As described above, conventionally, it is only to prevent chattering.

Problems to be Solved by the Invention In the conventional configuration as described above, it is possible to prevent chattering, but if noise is added to the input signal,
The system may mistakenly recognize noise as data and cause a malfunction. The present invention solves such a problem, and an object thereof is to prevent malfunction due to input noise.

Means for Solving the Problems In order to solve this problem, according to the present invention, when the data is “1” after system reset, m panel rows of a constant cycle are used as input data signals, and the data is “0”. , A first latch circuit that uses a high level or a low level as an input data signal and a second latch circuit that latches the data signal at the timing of the nth pulse (m ≧ n) and the data signal at the timing of the nth pulse. A first logic circuit for generating a timing signal for checking a comparison result between the load signal for latching in the second latch circuit and the output of the load signal and the output of the second latch circuit after the load signal; 1
When the outputs of the first latch circuit and the second latch circuit are different from the result of the comparator comparing the outputs of the latch circuit and the second latch circuit, the "1" data latched by the first latch circuit is output. If it is determined that the noise occurs, a system reset signal is generated at the timing of the check signal, and the outputs of the first latch circuit and the second latch circuit match, the first
When the "1" data latched by the latch circuit is judged to be a normal input signal and the second logic circuit for judging whether to hold the "1" data and the second logic circuit output the system reset signal, or the system When it outputs a reset signal, the reset circuit resets the first latch circuit, the second latch circuit, the first logic circuit, and the system.

With this configuration, the "1" data latched after the system reset is compared with the data signal latched at the nth timing after the "1" data latch, and when the comparison result is different, the first latch circuit latches the data. Judge "1" data as noise and reset the system by the system reset signal. If the comparison results are in agreement, the "1" data latched by the first latch circuit is judged to be normal and the system is not reset.

Embodiment 1 FIG. 1 is a block diagram of an input noise detection circuit according to an embodiment of the present invention. The block inputs a first latch circuit 1 to which a data signal of m pulse trains having a constant cycle is input, a first logic which inputs the output of the first latch circuit 1 and a clock signal, and generates a load signal and a check signal. A circuit 2, a second latch circuit 3 that functions with the load signal, a comparator 4 that compares the outputs of the first latch circuit 1 and the second latch circuit 3, and the comparison result functions at the timing of the check signal. The reset circuit 6 includes a second logic circuit 5 and a reset circuit 6 for resetting the first latch circuit 1, the second latch circuit 3, and the first logic circuit 2, respectively.
Is a function of the signal from the system 7. FIG. 2 is a specific logic circuit diagram of the input noise detection circuit according to the embodiment of the present invention. FIG. 3 shows a timing chart when a normal signal is input to this circuit configuration. Third
In the figure, if the first, second and third pulses of the data signal are "1" data, the first latch circuit (RS flip-flop 8) is set by the "1" data of the first pulse after system reset. , Its output A becomes "1". First logic circuit (AND gates 14 and 15, reset T flip-flop 16 to
18, OR gate 19) loads the second pulse of the data signal to the second latch circuit (inverter 10, NOR gate 11, R) by the load signal for latching the second pulse of the data signal. The S flip-flop 9) latches, and the output B becomes "1". The outputs of the first and second latch circuits A and B are compared by a comparator (EXOR gate 12), and the comparison result is checked by a second logic circuit (AND gate 13) of the check signal generated by the first logic circuit. Check at the timing. In this case, since the first latch circuit output A and the second latch circuit output B match "1" respectively, the data signal is judged to be normal and the second logic circuit (AND gate 13)
Does not output the system reset signal.

Next, if the 1st, 2nd, and 3rd pulses of the data signal are "0" data, that is, if the data signal is fixed at the low level, after the system reset, "1" data is temporarily generated due to noise occurrence in the 1st pulse. A timing chart in the case of occurrence is shown in FIG. 4. The first latch circuit 1 is set and its output A becomes "1". Since the second pulse is "0" data, the second latch circuit 3 is not set and its output B is "0". Since the output results of the first and second latch circuits are different, it is determined that the noise occurs and the second
The logic circuit 5 outputs a system reset signal. The system reset signal resets the first and second latch circuits and the first logic circuit via the reset circuit (OR gate 20).

Note that fixing the data signal at the high level is the second
It must be avoided in the circuit of the illustrated embodiment. This is because the first and second latch circuits latch the high level and completely lose the function of noise detection.

Although the embodiments shown in FIGS. 2 to 4 are described in the positive logic, each input pattern can be changed to the negative polarity by changing the logic configuration in FIG. 2 to the negative logic.

EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to prevent the malfunction of the system even if the input data signal is abnormal due to noise.

[Brief description of drawings]

FIG. 1 is a block diagram showing an input noise detection and system reset circuit according to an embodiment of the present invention, FIG. 2 is a logic configuration diagram showing an input noise detection circuit according to an embodiment, and FIG.
FIG. 4 is a timing chart showing a normal input signal, FIG. 4 is a timing chart showing an abnormal input signal,
FIG. 5 is a circuit diagram showing a conventional technique. 1 ... 1st latch circuit, 2 ... 1st logic circuit, 3 ... 2nd latch circuit, 4 ... comparator, 5 ... 2nd logic circuit, 6
...... Reset circuit, 7 ... System, 8,9 ... RS flip-flop, 10 ... Inverter, 11 ... NOR gate, 12 ... EXOR gate, 13-15 ... AND gate, 16-18
...... T flip-flop with reset, 19,20 …… OR gate, 21 …… System.

Continuation of the front page (56) References JP-A-58-96335 (JP, A) Actual opening 56-109148 (JP, U) Actual opening 59-192744 (JP, U)

Claims (1)

[Claims] 1. A first latch circuit for inputting m pulses having a constant cycle as a data signal, a second latch circuit for latching an nth pulse (mn) data signal of the pulse train, and the first latch circuit. Comparator for comparing the output of the second latch circuit with the output of the second latch circuit, and a data signal for the second signal at the timing of the n-th pulse.
A first logic circuit for generating a load signal for latching in a latch circuit and a timing signal for checking the output of the comparator after the load signal; and when the comparator outputs different outputs from the both latch circuits. A second logic circuit that produces a system set signal based on the timing signal when the determination is made, and the first latch circuit and the second logic circuit output a system reset signal or a system reset signal. An input noise detection circuit including a second latch circuit, the first logic circuit, and a reset circuit that resets the system.