JPH0756626B2 - Digital comparator - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a digital comparator, and more particularly to a digital comparator suitable for application to a microcomputer emulator, a logic state analyzer, or the like.

[Technical background of the invention and its problems]

2. Description of the Related Art Conventionally, a digital comparator has been used to detect a match or a mismatch between a plurality of digital data by hardware. Various types of such digital comparators are known, and FIG. 6 shows an example thereof.

As shown in FIG. 6, the first digital data D1 and the second digital data D2 are input in parallel from the first and second parallel input terminals 2 and 4, respectively. Each data D1, D2
Each bit of is input to the exclusive NOR circuit 8 via the inversion buffer 6 in correspondence with the digit. As a result, the exclusive NOR circuit 8 outputs a signal of "1" if the corresponding bits of the data D1 and D2 match and a signal of "0" if they do not match. The output signal of each exclusive NOR circuit 8 is input to the NAND circuit 12 together with the synchronization signal S input via the inversion buffer 10. Therefore, from the NAND circuit 12,
When all the bits of each data D1 and D2 match, the "0" signal is transmitted in synchronization with the synchronization signal S. This coincidence detection signal is sent to another device (not shown) and processed.

In such a conventional digital comparator, when the number of digital data to be compared increases, it is necessary to perform time-division processing or add a similar circuit according to the number of data. However, the former has a problem that the processing time is long, and the latter has a problem that the circuit scale is increased.

[Object of the Invention]

The present invention has been made to solve the above-mentioned problems of the prior art, and provides a digital comparator which has a small circuit scale and can perform coincidence detection of a plurality of digital signals without increasing the processing time. The purpose is to do.

[Outline of Invention]

To achieve the above object, the present invention has a plurality of addressable setting areas that can be individually set to a second state (for example, "1") with a first state (for example, "0") as an initial state. Receiving a plurality of array structure elements and first data,
Setting means for selecting any one of the plurality of array structure elements to set the setting area addressed by the first data in the selected array structure element to the second state; Of the plurality of array structure elements, the plurality of setting contents of the setting area addressed by the second data of each of the plurality of array structure elements are simultaneously read to generate a plurality of bits of output corresponding to the plurality of array structure elements. And a digital comparator including an abutting unit.

Example of Invention

Hereinafter, reference examples and embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a digital comparator according to a reference example of the present invention, and FIG. 2 is a configuration diagram of a main part thereof. A plurality of data D1 ... Dn are given from the parallel input terminal 14 in a time division manner,
It is input to the decoder 16 and the decoder selector 22.
The decoder 16 decodes the input data and outputs the array structure element 18
Give to. The decoder selector 22 has a function of decoding the input data and giving it to the array structure element 18, and a function of selecting a coincidence signal from the array structure element 18. The array structure element 18 is reset by the clear signal C from the clear terminal 20,
The area “1” corresponding to the lines from the decoder 16 and the decoder selector 22 is set by the set signal W input to the set terminal 26. The decoder 16 and the decoder selector 22 have a function of transmitting a coincidence signal to the buffer 24 via the decoder selector 22 when the correlation between the line and the set position is obtained. The buffer 24 outputs a data coincidence signal in synchronization with the synchronization signal S from the synchronization terminal 28.

As shown in FIG. 2, the array structure element 18 is formed by arraying a plurality of setting areas 19 at predetermined positions. In the example of FIG. 2, the data D1 to Dn are composed of 8 bits, and therefore the data D1 to Dn are 2 ⁸ = 256 ways. On the other hand, the array structure element 18 is composed of 16 × 16 = 256 setting areas 19. That is, there is one setting area at a position corresponding to each piece of data to be compared.

The array structure element can be formed by a combination of memory cells. The decoder selector is an AND circuit,
It can be formed by a combination of OR circuits.

Next, the operation will be described.

Prior to the data comparison, the clear signal C is first input from the clear terminal 20 to set all the setting areas 19 of the array structure element 18.
Is initialized to “0”. Next, digital data (reference data) desired to be matched is input from the parallel input terminal 14 in bit parallel. Here, the set signal W is sent to the decoder selector 22.
Is set, "1" is set in the setting area of the position corresponding to the data in the array structure element 18. If there are multiple digital data for which you want to see the match, the parallel input terminal 14
By inputting the set signal W while inputting the digital data to, the setting area for the number of data in the array structure element 18 is set to "1".

Next, the digital data (comparison data) to be compared is given from the parallel input terminal 14, and while the decoded value is given to the array structure element 18 via the decoder selector 22, the data match,
Detects discrepancies. That is, when the digital data to be compared matches the digital data to be compared, "1" is extracted from the corresponding setting area, is derived through the decoder selector 22, and is provided to the buffer 24. When they do not match, “0” in the setting area is derived.
The buffer 24 synchronizes with the synchronization signal S and outputs the comparison result to the signal R.
To the outside.

FIG. 3 is a block diagram of a digital comparator according to another reference example of the present invention. This is different from the one shown in FIG.
The parallel input terminals for data input are provided as two parallel input terminals 14a and 14b independently of the reference data D1 to Dn and the comparison data Dn + 1 to Dm, and the data input to the decoder 16 and the decoder selector 28 are Select signal L from select terminal 34
The data selectors 30 and 32 controlled by are selected.

With this configuration, the reference data and the comparison data can be input from the individual input terminals 14a and 14b. The operation of data matching and coincidence detection is similar to that of FIG.

FIG. 4 is a block diagram of a digital comparator according to an embodiment of the present invention. This differs from the one in Fig. 1 in that
The array structure elements 18a to 18d are provided in parallel, the buffer 24 is provided with terminals for outputting four different signals R0 to R4, and the decoder 16 is provided with two (4 bits). That is, the setting signal A can be input.

That is, in the embodiment of FIG. 4, when a plurality of data (reference data) are set, a result signal indicating which reference data and the comparison data match or not is output as R0 to R4, and One data is output to R1 and another data is R2
It is designed to be output to. Therefore, prepare a plurality of array structure elements corresponding to the number of bits of output data,
For example, the first array structure element 18d outputs to R0, and the second array structure element 18c outputs to R1. When setting the data, the number of output bits required by the setting signal A which bit (R0 to R4) is to be output, that is, which array structure element (18a to 18d) is set ≤ 2 ⁿ (n is the minimum N) are required. In this embodiment, since it is 4 ≦ 2 ^2, are required two setting signal. By doing so, it is possible to obtain outputs having four different meanings R0 to R3.

This digital comparator has particular applications where it is desirable to make use of it. One of its uses is an emulator that evaluates the functions and performance of computers. The emulator is required to have a function capable of performing various operations such as stopping the CPU, turning on / off the execution trace, and turning on / off the execution time measurement timer at a preset address of the program. Therefore, a digital comparator is used to compare the preset program address for performing those operations with the program address executed by the CPU. When the digital comparator of FIG. 4 is used for this purpose, each operation such as CPU stop, execution locus on / off, and execution time measurement timer on / off is associated with each array structure element. For example, the stop of the CPU corresponds to the array structure element 18a, and the execution locus is on when the array structure element 1a is turned on.
It corresponds to 8b, and so on. Then, the program address at which each operation should be performed is set as reference data in the array structure element corresponding to each operation. For example, the address at which the CPU should be stopped is set in the array structure element 18a, and the address at which the execution locus is turned on is the array structure element.
Set it to 18b, and so on. After that, the address executed by the CPU is given as comparison data. When this execution address matches the preset address,
The signals R0 to R3 are output, and the signals R0 to R3 indicate the operation to be performed by the emulator. For example, when the signal R0 is output, the CPU is stopped, when the signal R1 is output, the execution locus is turned on, and so on. Therefore, the digital comparator of FIG. 4 is very easy to use in the emulator.

FIG. 5 is a block diagram of a digital comparator according to a reference example. This is different from the one shown in FIG. 4 in that data is compared in one array structure element 18 'divided into four. Then, a 2-bit signal A for designating which part of the four-divided array structure element 18 'is to be set with data and to be matched with data is a terminal.
It is given to the decoder 16 and the decoder selector 22 via 29.

This reference example is also suitable for use in an emulator as in the embodiment shown in FIG. In this case, each divided part of the array structure element is associated with each operation of the emulator, and the address of each corresponding operation is set in each part. Then, the address being executed by the CPU is relatively given as data, and data comparison is performed in the array structure element. This data comparison is performed in one part in the array structure element selected by the signal A. That is, the signal A selects the operation to be performed by the emulator.

The present invention is not limited to the above embodiment, but various modifications can be made. For example, the digital data to be compared is not limited to 8-bit data. Also, the digital comparator of the present invention can be utilized as a memory for storing whether or not certain digital data is generated. In addition, a plurality of array structure elements are provided, and reference data can be set to the array structure element arbitrarily selected from among them,
The output signal indicates in which array structure element the coincidence of the data comparison has occurred, or since it is possible to arbitrarily select the array structure element for performing the data comparison, for example,
It is possible to provide a very easy-to-use digital comparator for a specific application such as address comparison in an emulator.

〔The invention's effect〕

As described above, according to the present invention, one or a plurality of data can be set as the reference digital data, and the comparison digital data can be compared with the reference data at the same time. Therefore, the configuration is relatively simple. Thus, it is possible to obtain a digital comparator capable of high speed data comparison.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital comparator according to a reference example of the present invention, FIG. 2 is a block diagram of a main part thereof, and FIG. 3 is a block diagram of a digital comparator according to another reference example of the present invention.
FIG. 4 is a block diagram of a digital comparator according to an embodiment of the present invention, FIG. 5 is a block diagram of a digital comparator according to another reference example of the present invention, and FIG. 6 is a block diagram of a conventional digital comparator. Is. 16 …… decoder, 18 …… array structure element, 22 …… decoder selector, 24 …… buffer, 30,32 …… data selector.

Claims (6)

[Claims] 1. The first state is set as an initial state and the second state is individually set.
A plurality of array structure elements having a plurality of addressable setting areas, which can be set to the state, and receiving one of the first data, selecting one of the plurality of array structure elements, and selecting the selected array structure. The first in the element
Setting means for setting the setting area addressed by the data of the second state to the second state, and the setting area for receiving the second data and being addressed by the second data of each of the plurality of array structure elements. A digital comparator comprising: butting means for simultaneously reading a plurality of setting contents and generating a plurality of bits of output corresponding to the plurality of array structure elements. 2. The digital comparator according to claim 1, wherein said setting means has a decoder which decodes said first data and supplies it to said array structure element. 3. The abutting means includes a decoder for decoding the second data and applying the decoded data to the array structure element, and a buffer for holding an output of the plurality of bits. The digital comparator described in the item. 4. The digital comparison according to claim 1, wherein the array structure element has an initialization means for initializing the setting area to the first state. vessel. 5. The digital comparator according to any one of claims 1 to 4, wherein the first data and the second data are received at different input terminals. 6. The array structure element has a clear terminal for simultaneously setting all the setting areas in each array structure element to the first state. The digital comparator according to any one of items 1 to 5.