JPH0756755B2 - MIS memory circuit - Google Patents

Description

The present invention relates to MIS memory circuits.

Generally, in an insulated gate transistor memory circuit (hereinafter simply referred to as MIS memory circuit) in which writing and reading are performed via a pair of common data lines, the potential state of the common data line generated at the time of writing (first It is necessary to shift the potential state) to a potential state (second potential state) required for reading, and a data line potential setting circuit is used to shorten the time.

An MIS memory circuit using such a data line potential setting circuit will be described with reference to FIG.

In the figure, 1 is a memory matrix in which memory cells MS _{11 to} MSmn are arranged in m rows and n columns. A row selection address decoder 2 selects each row of the memory matrix by row address signals W1 to Wm. Reference numeral 3 is a column gate means for connecting a pair of digit lines (D ₀₁ , D ₁₁ ) to (D ₀ n, D ₁ n) arranged in each column to common common data lines CD _{0 to} CD ₁ . , A pair of column gate switching elements (Q ₅ , Q ₆ ) to (Q ₅ ′, Q ₆ ′) for each column. Four
Is the pair of column gate switching elements (Q ₅ , Q ₆ )
Is a column selection address decoder for selecting (Q ₅ ′, Q ₆ ′) by column gate signals CL _{1 to} CLn. Reference numeral 5 is a load means for supplying current to the pair of digit lines (D ₀₁ , D ₁₁ ) to (D ₀ n, D ₁ n) in each column, and a pair of MISFETs (Q ₇ ,
_{Q 8) ~ (Q 7 '} , Q 8' consists of). 6CSX signal, WED signal, W
The write circuit is controlled by the E ′ signal and amplifies write data from the input / output terminal I / O and transmits the amplified write data to the pair of common data lines. 7 is CSX signal, WE signal, Is a read circuit that amplifies the data read by the common data lines CD _{0 to} CD ₁ and transmits it to the input / output terminals I / O. Reference numeral 8 is a data line potential setting circuit connected to a pair of common data lines. MISFET Q ₉ ′ Q ₉ is connected between the common data line CD ₀ and bias source Vcc, and common data CD ₁ and bias source Vcc are connected. Between and MISFETQ ₁₀ ′, Q
_It has a circuit configuration provided with ₁₀ and the MISFET Q ₉ , Q ₁₀
Are controlled by ▲ ▼ signals. Each memory cell has a MISFET cross-connected as shown in MS ₁₁ and MSmn.
Q ₃ , Q ₄ (Q ₃ ′, Q ₄ ′) and their cross connection points A, B
(A ', B') and the digit lines D ₀₁ , D ₁₁ (D ₀ n, D ₁ n), and the row address signal W ₁ (Wm) is applied to the MISFETs Q ₁ , Q ₂ ( Q ₁ ′, Q ₂ ′) and load elements R ₁ , R ₂ (R ₁ ′, R ₂ ′) connected between the bias source Vcc and the cross connection points A, B (A ′, B ′). ), The data is statically generated so that a high level (hereinafter referred to as H level) is generated at one cross connection point and a low level (hereinafter referred to as L level) is generated at the other cross connection point. Has the function of storing and holding. As shown in FIG. 2, the write circuit 6 includes a push-pull amplifying means composed of MISFETs Q ₄₂ , Q ₄₃ , Q ₄₉ , Q ₅₀ , and Q ₅₆ , the push-pull amplifying means, and a pair of common data lines CD ₀ , CD. MISFET connected between ₁ and
Transmission means consisting of Q ₄₂ ′ and Q ₄₉ ′, and MISFET Q ₄₄ , Q ₄₅ ,
Q _51, Q _52, a first inverter waveform shaping means consisting of _{Q 57, MISFETQ 46, Q 47} , Q 5 3, Q 54, a second inverter waveform shaping means and MISFET Q ₄₈ consisting of Q _58, Q _55, It consists of input buffer means consisting of Q _59,
The write data from the input / output terminal is amplified by controlling the push-pull amplifying means with the WE signal by the E ′ signal, and controlling the first and second inverter waveform shaping means and the input buffer means with the CSX signal. Applied to a pair of common data CD ₀ and CD ₁ .

The levels of the write data to be transmitted to the common data line are 3.8V "H" level and the other 0.3V "L" level when the bias source Vcc is 4.5V. Further, the MISFET Q ₄₄ to Q ₄₈ are Depuretsushon type and the other is an enhancement type.

Further, the reading circuit 7 is a MISF as shown in FIG.
ETQ ₆₀ , Q ₆₁ , Q ₇₂ , a first actuation amplification means consisting of Q ₇₅ ,
MISFETQ ₆₂ , Q ₆₃ , Q ₇₆ , second differential amplifying means driving level control means, and MISFETQ ₆₄ , Q ₆₀ , Q ₇₇ , Q
The second differential amplifying means consisting of ₇₈ , Q ₇₉ and Q ₈₀ , and MISFETQ
_A second level control means for driving differential amplification consisting of ₆₆ , Q ₆₇ and Q ₈₁ , and MISFETs Q ₈₂ , Q ₈₄ , Q ₆₈ , Q ₆₉ , Q ₈₃ and Q _80.
First push-pull amplification means consisting of MISFETQ ₈₆ , Q
₇₀ , Q ₈₇ , Q ₇₁ , Q ₈₈ constituted by a second push-pull amplifying means, MISFET Q ₉₀ , Q ₉₁ TTL signal level driving inverter means, and MISFET Q ₈₉ , Q ₈₉ ′ tri-state means. The first and second differential amplifying means and the level control means for driving the first and second differential amplifying means are CSX signals and the first and second push-pull amplifying means are used. Then, by controlling the tri-state means by the WE ₁ signal respectively, the data read to the common data lines CD ₀ , CD ₁ is amplified and taken out to the input / output terminal I / O.

The optimum level of the signal applied to the first differential amplifier stage is 3.8V “H” level and the other 3.5V “L” level when the bias source Vcc is 4.5V. And the difference is about 0.3V. The MISFETs Q _{60 to} Q _{71 are} depletion type and the other MISFETs are enhancement type.

In the MIS memory circuit of FIG. 1 having the above configuration, a case where data is written in the memory cell MS ₁₁ and immediately after that data is read out from the memory cell MSmn in the same chip, a pair of common data lines DC ₀ , CD How the potential state at the time of writing ₁ (first potential state) shifts to the potential state required at the time of reading (second potential state) will be described with reference to the timing chart of FIG.

In the figure, ▲ ▼ signal, ▲ ▼ signal, Ai
Signals, Din / D _OUT, are applied from outside the IC chip, and other signals are formed inside the IC chip.

At timing t ₁ , the signal ▲ ▼ becomes "L" level to bring about the chip selection state, and the address signal Ai from the outside is applied to the row and column selection address decoder. As a result, the memory cell MS ₁₁ is selected, and the digit lines D ₀₁ and D ₁₁ are connected to the pair of common data lines CD ₀ and CD ₁ via the column gate switching elements Q ₅ and Q ₆ . Also, since MISFETs Q ₁ and Q ₂ are also turned on, cross connection points A and B
Is connected to the pair of digit lines D ₀₁ and D ₁₁ .

Due to the change of the WE signal to the "L" level after the timing t ₁ , the WE 'signal is at the "L" level at the timing t ₂ , so that the write circuit 6 in FIG. 2 sets the WED signal to the "H" level. , Since the CSX signal is at the “H” level, the push-pull amplifying means, the first inverter waveform shaping means, and the input buffer means are operating respectively, thereby amplifying the write data Di _N applied from the input / output terminals. Then, the data is transmitted to the pair of common data lines CD ₀ and CD ₁ .

Now, when Di _{N is set} to the “H” level, the common data line DC ₀
The potential V _CD0 of the common data line CD ₁ is about 3.8 V, and the potential V _CD1 of the common data line CD ₁ is about 0.3 V “L” level (V _1H ).
_1L ). The levels of V _1H and V _1L indicate the first potential state.

First potential state V of the pair of common data lines CD ₀ , CD _1
1H and V _1L are memory cells through column switching means Q ₅ and Q ₆ and a pair of digit lines D ₀₁ and D ₁₁ and MISFETs Q ₁ and Q _2.
It is also transmitted to the cross connection points A and B of MS ₁₁ .

Since the current driving capability of the load means MISFETs Q ₇ and Q ₈ and the load resistance elements R ₁ and R ₂ of the memory cell MS ₁₁ is smaller than the current driving capability of the push-pull amplifying means of the write circuit 6, the cross connection point A , B levels are V _1H and V _1L . Further, at this time point, the parasitic capacitances C ₀ and C ₁ existing in the common data lines CD ₀ and CD ₁ also accumulate V _1H and V _1L . In addition,
Since the common data lines CD ₀ and CD ₁ are commonly used for a plurality of pairs of digit lines (D ₀₁ , D ₁₁ ) to (D ₀ n, D ₁ n), the line length is considered to be long. Therefore, the parasitic capacitances C ₀ and C ₁ are very large.

At timing t ₃ , the transmission circuit of the writing circuit 6 receives W
Since the “L” level of the E ′ signal is applied, the common data lines CD ₀ and CD ₁ are electrically disconnected from the write circuit 6, but the level is set to the first potential state by the capacitors C ₀ and C ₁ . Held in.

At this point, the load means Q ₇ , Q ₈ and the load resistance element
R ₁ and R ₂ can supply a bias to the cross connection points A and B without being restricted by the push-pull amplification means of the write circuit 6. Also, Becomes high, the data line potential setting circuit 8 also starts operating.

The MISFETs Q9 'and Q9 of the data line potential setting circuit 8 are turned off because the potential difference between the gate and source thereof is less than the threshold ground voltage (about 0.7V) in response to the common data line CD ₀ being V _1H. ing. Also, since the common data line CD ₁ is V _1L , the potential difference between the gate and source of the MISFETs Q ₁₀ ′ and Q ₁₀ is more than the threshold voltage (about 0.7 V), so that they are turned on. As a result, the capacitance C ₁ is charged via the MISFETs Q ₁₀ ′ and Q _10, and the level of the common data line CD ₁ is gradually raised.

On the other hand, the cross connection point A of the memory cell MS ₁₁ operates so as to _{reach the} level V _2H determined by the load means Q ₇ , MISFETQ ₁ , Q ₃ from V _1L . The cross connection point B is V when writing
_It remains at _2H .

Here, the current drivability of the load means Q ₇ , Q ₈ is made larger than that of the data line potential setting circuit 8. Accordingly, the level of the common data line is fixed to the level determined by the cross connection points A and B of the memory cell MS ₁₁ . As a result, the common data line CD ₁ becomes V during the period indicated by T ₁ in FIG.
_{The level of 1L} to V _2L and the common data line CD _{0 changes} from V _1H to V _2H , and the level difference is about 0.3V.

It is only necessary to switch the address signal Ai and select the next memory cell MSmn when the level difference of the common data line becomes about 0.3 V, but in reality, it is slightly delayed,
It is switched at timing t ₅ . From timing t ₄ to timing t ₅ , the levels of the common data lines CD ₀ and CD ₁ are held in the second potential state.

At timing t ₅ , when the address signal Ai is switched, the memory cell MSmn is selected, which causes the common data lines CD ₀ and CD ₁ to move to the column gate switching element Q ₅ ′,
It is connected to a pair of digit lines D ₀ n and D ₁ n via Q ₆ ′. Now, at the cross connection point A ′ of the memory cell MSmn, load means is provided.
Potential V determined by Q ₇ ′, MISFETQ ₁ ′, Q ₃ ′
_2H is also 'the load means _{Q 8' B, MISFETQ 2 '} , Q 4' and the potential V _2L exists which is determined by the memory cell M
The data opposite to the data written in S ₁₁ is stored and held. Therefore, the memory cell MSmn is the common data line CD
₀ , level of CD ₁ is reversed from V _2H , V _2L to V _2L , V _2H .

At timing t ₆ , the potential states V _2L and V 2 required for reading the data of the memory cell MSmn on the common data lines CD ₀ and CD _{1
When 2H} , that is, V _2L becomes 3.5V and V _2H 3.8V, the read circuit 7 amplifies the level difference 0.3V between the common data lines CD ₀ and CD _{1 in} the optimum state and outputs it from the input / output terminal I / O. Read data D
_{Read OUT} . In this case, the read data D _OUT is “L”
It is a level. At timing t ₆ , the read circuit 7 is operable because the CSX signal is at “H” level and the WE ₁ signal is at “L” level.

Although the operation of the MIS memory circuit of FIG. 1 has been described above, the write recovery time can be shortened by using the data line potential setting circuit 8 in FIG.
However, in the present situation, there is a demand in the market to further shorten the write recovery time, and it is necessary to satisfy the specifications.

Therefore, an object of the present invention is to provide a data line potential setting circuit which can obtain the level difference of the second potential state more rapidly.

Another object of the present invention is to reduce the level difference of the second potential state to the second level.
It is to provide a data line potential setting circuit that can be obtained at a position closer to the potential state of.

Still another object of the present invention is to obtain a data line potential setting circuit that does not supply current when the potential state of the pair of data lines is near the second potential state.

Still another object of the present invention is to provide a data line potential setting circuit capable of clamping the level of the potential state of the pair of data lines near the second potential state.

The basic constituent features of the present invention are as set forth in the claims, and the present invention will be described in detail below with reference to Examples.

FIG. 5 shows an MIS memory circuit using the data line potential setting circuit 9 according to the present invention. Instead of the data line potential setting circuit 8, the data line potential setting circuit 9 according to the present invention is used. The configuration is the same as that of the MIS circuit shown in FIG. 1 except that the write recovery signal generating circuit 10 is added. The same numbers and symbols are used for the parts common to those in FIG. The description of these common parts has already been described above, and will not be repeated here.

The read circuit 7'in FIG. 5 is the MIS of FIG.
Although the circuit configuration is the same as that of the read circuit 7 used in the memory circuit, as will be described later, the read levels “H” level and “L” level applied to the first differential amplification means are higher than those in the conventional case. It is a low value. (For example, if the bias source is 4.
In case of 5V, the optimum values of "H" level and "L" level are 2.8V and 2.5V
Further, at each cross connection point of each memory cell, the one corresponding to the optimum read value in the stored state is the “H” level, and the other is the “L” level.

In FIG. 5, the data line potential setting circuit 9 according to the present invention includes a switching means 9'comprising a MISFET Q ₁₁ connected between common data lines, and a MISFET Q ₉ connected between a bias source Vcc and each common data line. , Q ₁₀ and a clamp means 9 composed of depletion type MISFETs Q ₁₂ , Q ₁₃ and enhancement type MISFETs Q _{14 to} Q ₂₀ .

The write recovery signal generation circuit 10 generates a first write recovery signal φ _RW1 and a second write recovery signal φ _RW2 by being controlled by ▲ ▼ and WED signals shown in the timing chart of FIG. To do.

The switching means 9'is controlled by the first write recovery signal φ _RW1 and its MISFWETQ ₁₁ operates in a non-saturated state.

The current supply means 9 ″ is controlled by the second write recovery signal φ _RW2 , and the MISFETs Q ₉ and Q ₁₀ operate in the saturation region.

In the clamp means 9, the MISFET Q ₁₈ is changed by the signal shown in the timing chart of FIG.
MISFETQ ₁₉ is controlled by CSA ₂ signal, and MOI
SFETQ ₂₀ has its gate connected to bias source Vcc. Therefore, the means composed of MISFETQ _{18 to} Q ₂₀ level-converts the bias source Vcc and applies the voltage to MISFETQ ₁₆ and Q ₁₇ . The MISFETs Q ₁₄ and Q ₁₅ are controlled by the signal ▼ described above. Therefore, the means consisting of MISFET Q ₁₃ , Q ₁₅ and Q ₁₇ and the means consisting of MISFET Q ₁₂ , Q ₁₄ and Q ₁₆ respectively bring the common data lines CD ₀ and CD ₁ to the intermediate level between the second potential states V _2L and V _2H. .

FIG. 6 shows a specific circuit diagram of the write recovery signal generating circuit 10.

In the figure, MISFETQ _{21 to} Q ₂₇ are depletion type MISF.
ET, and MISFETs Q _{28 to} Q ₄₁ , and Q ₂₉ ′ and Q ₃₀ ′ are enhancement type.

MISFETQ ₂₁ and Q ₂₈ are the first inverter,
The WED signal is applied and the output is P ₁ . MISFETQ ₂₉ ′, Q
₂₂ and Q ₂₀ are the second inverters, the input of which is P ₁ and the output of which is P ₂ .

In addition, ▲ is added to MISFETQ ₂₉ ′ and MISFETQ ₂₅ , Q ₃₄
The signal P ₅ inverted at is applied. MISFET
_{Q 30 ', Q 23, Q} 30 is the third inverter, P ₂ is applied to its input, the output is P _3.

In addition, ▲ ▼ is added to MISFETQ ₃₀ ′ and MISFETQ ₂₅ , Q ₃₄
The signal P ₅ inverted at is applied.

MISFETQ ₂₄ , Q ₃₂ is a fourth inverter, the input of which is determined by the signal of P ₃ and the output of MISFET Q ₃₁ which receives the signal ▲ ▼, the output of which is P ₄ and the second write recovery signal. It is connected to the output terminal of _φWR2 .

The P ₄ is also controlled by the MISFET Q ₃₃ which receives the WED signal.

MISFETQ ₂₆ and Q ₃₅ are the first delay means,
P ₃ is applied and its output is P ₆ .

MISFETQ ₃₆ and Q ₃₇ are second delay means, and the signal of P ₆ is applied to MISFETQ ₃₆ and the signal of P ₃ is applied to MISFETQ ₃₇ ,
Its output is P ₇ . The P ₇ is a MISFETQ that receives the WED signal.
_It is also controlled by ₃₈ .

MISFETs Q ₂₇ and Q ₃₉ are _fifth inverters, which receive P ₇ as an input and P ₈ as an output.

The MISFETQ ₄₀ , Q ₄₁ and the capacitor CB are bootstrapping means, and P ₈ is applied to the MISFETQ ₄₁ . A boot strap capacitor CB is connected between the gate and source of the MISFET Q _40. One electrode is P ₇ , and the other electrode is MISFET.
Ground level is applied via Q ₄₁ or Vcc is applied via MISFET Q ₄₀ . Then, the first write recovery signal φ _WR1 is taken out from one electrode of the capacitor CB.

The operation of the write recovery signal generation circuit 10 will be briefly described.

First, when ▲ ▼ is at "H" level and WDE is at "H" level, P ₁ is at "L" level, P ₂ is at open state, P ₃ is at "L" level, P ₄ is at "L" level. _Therefore , the second write recovery signal φ _WR2 is at “L” level, and P
₆ is "H" level, P ₇ is "L" level, P ₈ is "H" level, P ₉
Is at the "L" level, the first write recovery signal is also at the "L" level.

Next, when ▲ ▼ is at “L” level and WDE is at “H” level, P ₁ is at “L” level, P ₂ is at “L” level, P ₃ is at “L” level and P ₄ is at “L” level. The second write recovery signal φ _WR2 is at "L" level because it becomes "level." Also, P ₆ is “H”
Since the level, P ₇ is “L” level, P ₈ is “H” level, and P ₉ is “L” level, the first write recovery signal φ _WR1 is also “L” level.

Furthermore, when ▲ ▼ is at “L” level and WED is at “L” level, P ₁ is at “H” level, P ₂ is at “L” level,
Since P ₃ is "H" level, but P ₄ becomes "L" level WED signal is delayed by the first, second, third inverter,
The level of P ₄ is initially at “H” level,
The second write recovery signal φ _WR2 generates a level of about Vcc.

When the level of P ₃ becomes “H” level, the level of P ₄ becomes “L”
Since it is set to the level, the second write recovery signal φ _WR2 is changed to the “L” level at that time. That is, W
The second write recovery signal φ _WR2 will generate a one-shot “H” level when ED becomes “L” level.

When P ₃ above is still at “L” level, P ₆ is at “H” level, P ₇
Is at "H" level. P ₈ receives P _{7 and} goes to “L” level, but the time is slightly delayed, so MISFET Q ₃₆ , capacitance CB, MIS
A current flows through the FETQ ₄₁ , and charges are supplied to the capacitor CB.

Then, when P ₈ becomes completely “L” level, MISFETQ ₄₁
The level of P ₉ for turning off is Vcc. As a result, the capacitance CB is bootstrapped, and one electrode has approximately 2
A high "H" level of Vcc-Vth is generated as the first write recovery signal φ _WR1 .

Next, since the level of P ₃ is completely set to “H” level, P ₆ is set to “L” level and P ₇ is set to “L” level, and thus the first write recovery signal φ _WR1 is set to “L” level. "Become a level.

Therefore, the first write recovery signal φ _WR1 outputs a one-shot “H” level from the time when the WED signal becomes “L” level.

The configuration of the data line potential setting circuit 9 and the write recovery signal generating circuit 10 according to the present invention in the MIS memory circuit of FIG. 5 has been described above. Next, when the data line potential setting circuit 9 according to the present invention is used , The first when writing
How quickly the potential state of 1 shifts to the second potential state required at the time of reading will be described with reference to the timing chart of FIG.

In the MIS memory circuit shown in FIG. 5, first, the memory cell MS
_{It is} assumed that the “H” level of D ₁ n is written in ₁₁ and immediately after that, the “L” level is read as D _OUT from the memory cell MSmn in the same chip.

Therefore, a memory circuit and a condition of the first figure in the timing chart of Figure 7 is the same, time t ₃
Let's start with. In addition, in FIG.
▼ signal, ▲ ▼ signal, Ai signal, and D _IN / D _OUT
The signals taken in from the outside of the IC chip or the signals taken out to the outside are shown, and other signals are formed inside the IC chip.

At timing t ₃ , the WE ′ signal goes to “L” level to electrically disconnect the write circuit 6 from the common data lines CD ₀ and CD ₁ . However, the potentials at the time of writing, that is, V _1H and V _1L exist in the capacitors C ₀ and C ₁ of the common data lines CD ₀ and CD ₁ , respectively.

At this point, both ▲ ▼ and WED signals are "L".
Since it is at the level, the second write recovery signal φ _WR2 and the potential of the bias source Vcc from the write recovery signal generation circuit 10 (shown as Vφ _WR2 in FIG. 7) and about 2 · Vcc-Vth. And a first write recovery signal φ _WR1 (shown as Vφ _WR1 in FIG. 7) having a voltage of V _WR1 is generated.

Thereby, first, the switching means 9'of the MISFET Q ₁₁
Since the common data lines CD ₀ and CD ₁ are electrically connected to each other, the charge of the capacitor C ₀ is discharged to the capacitor C ₁ via the MISFET Q ₁₁ to cause charge dispersion. Thereby common data line CD
The level of ₀ goes down, and the level of the common data line CD ₁ goes up. The rising and falling are performed with almost the same characteristics.

Further, since MISFET Q ₁₁ is that the first write recovery signal phi _WR1 is a 2 · Vcc-Vth, about 8.3 V, shown in FIG. 12
Since the MISFET operates in the non-saturated region indicated by Z ₁ in the output voltage-output current characteristics, its operating resistance is extremely small.

Therefore, the fall of the level of the common data line CD _{0 and} the fall of the level of the common data line CD ₁ are rapid, and the common data lines CD ₀ and CD ₁ are changed from the first potential state. The speed approaches the second potential state.

Further, since the second write recovery signal φ _WR2 is applied to the current supply means 9 ″, the MISFET Q ₁₀ is turned on and the MISFET Q ₁₀ is turned on.
Q ₉ is off because the common data line CD ₀ is at V _1H of 3.8V. Since the charge is supplied from the MISFETQ ₁₀ to the capacitor C ₁ , the common data line formed by the switching means 9 '
It will help set the level for CD ₁ .

Therefore, the level difference of the second potential state can be obtained earlier accordingly.

Therefore, at the timing t _4, the common data line
CD ₀ and CD _{1 change} from the first potential state V _1H and V _1L to the vicinity of the second potential state V _2H ′ and V _2L ′ (in this second potential state, V _2H ′ and V _2L ′ are both The value is lower than that in the case of.) The level difference is also about 0.3V.

At this point, it is ideal if the first write recovery signal and the second write recovery signals φ _WR1 and φ _WR2 are set to the “L” level, respectively, but since they become the “L” level with a slight delay,
By the timing t ₅ by the current supply means 9 ″
_Set V _2L ′ to V _2L ″ and V _2H ′ to V _2H ″.

The clamp means 9 starts to operate substantially at the timing t ₅ . That is, the clamping means 9 is W
It is already operating when the ▲ ▼ signal obtained by inverting the E ′ signal becomes “H” level and the CSA ₂ signal becomes “H” level, but the current driving capability is lower than that of the current supply means 9 ″. This is because.

By this clamp means 9, common data lines CD ₀ , CD ₁
Of V _2H ", V _2L" a, V _2H, V _2L by state near V _2H, V _2L
Take it to me.

That is, the clamp means 9 uses the common data lines CD ₀ , CD _1
Is biased near the intermediate level V ₀ between the second potential states V _2H and V _2L and works to clamp the level.

Therefore, if the first and second write recovery signals φ
_{Even if WR1} and φ _WR2 become the “L” level before the level difference of 0.3 V in the second potential state is obtained, the level can be compensated by the clamp means 9 and brought to 0.3 V.

The memory cell MSmn is selected by switching the address signal Ai at the timing t ₆ .

The memory cell MSmn has a load means Q ₇ ′ at its cross connection point A ′,
The potential V _2H determined by MISFETQ ₁ ′ and Q ₃ ′ is stored and stored at the cross connection point B ′, and the potential V _2L determined by the load means Q ₈ ′, MISFETQ ₂ ′ and Q ₄ ′, respectively.

Therefore, the state is exactly opposite to that of the common data lines CD ₀ and CD ₁ .

Common data lines CD ₀ , CD ₁ V _2H , V _2L
Low level by setting V _2H and V _2L with mn and inverting it
V _2L and high level V _2H .

Since V _2H and V _2L are almost equal to V _2H and V _2L , the level correction in the memory cell MSmn is faster than that in the MIS memory circuit of FIG. At timing t ₇ , since the low level V _2L and the high level V _2H are obtained as the read data of the memory cell MSmn on the common data lines CD ₀ and CD ₁ , they are amplified by the read circuit 7 ′ and input / output terminal I / O
Outputs "L" level D _OUT as read data.

In the read circuit of the present invention, for example, a bias source
When Vcc is 4.5V, V _2L and V _2H are 2.5V,
Since 2.8V is obtained, the TTL logic level output from the read circuit can be easily obtained.

As described above, MI using the data line potential setting circuit 9 according to the present invention
The operation of the S memory circuit was explained, but for the following reasons,
The object of the present invention can be achieved.

1) Since the switching means 9'is connected between the common data lines and the electric charge of the capacitance of one common data line is discharged to the capacitance of the other common data line via the switching means 9 ', the one common data line is discharged. The level difference between the two is made by the fall and rise of the level of the data line. (According to the conventional circuit, the levels of both common data lines are brought close to each other only by raising the level of the other common data line.) Further, the switching means 9'is provided with the first write recovery signal φ _WR1.
Since the gate is applied with a potential of 2 · Vcc-Vth, it operates in a non-saturated state, and its operating resistance is small, so that the rising and falling edges are rapid. Further, since the electric current is supplied to the capacitance of the other common data line by the current supply means 9 ', the level rise of the other common data line becomes faster together with that of the switching means 9', and as a result, both common data lines The level between them will come closer to that level.

From the above, it is possible to obtain the level difference in the second potential state earlier than in the conventional data line potential setting circuit.

2) A switching means 9'is connected between the common data lines so that the electric charge of the capacitance of one common data line is discharged to the other capacitance via the switching means 9'and the switching means 9'is desaturated. Since the common data line is operated in the same manner, the falling characteristic of one common data line and the rising characteristic of the other common data line can be made substantially the same, and as a result, the lower level in the second potential state is almost the second level. It is obtained near the potential state of.

Therefore, the time for which the memory cell is in the second potential state can be shortened.

3) When the level between the common data lines becomes close to the second potential state, the switching means 9 ″ and the current supply means 9 ′ cause the first and second write recovery signals φ _WR1 and φ _{WR to} be “L”.
Since it is at the level, it is not operating and the level of the common data line does not rise to a level higher than the second potential state.

4) The switching means 9'and the current supply means 9 "are the second
After the level of the common data line is raised above the potential state of No. 2 and the operation is stopped, the clamp means 9 for lowering the level to the vicinity of the second potential state is provided. Therefore, it is not necessary to lower the level by the memory cell itself. As a result, the second potential state is obtained, so that the speed becomes faster.

As another embodiment of the present invention, a data line potential setting circuit shown in FIGS. 8 to 10 can be considered.

In the embodiment shown in FIGS. 8A to 8F, the data line potential setting circuit is constructed by using only the switching means 9'and the current supply means 9 ".

The data line potential setting circuit shown in FIG. 8 (a) is obtained by removing the clamp means 9 from the data line potential setting circuit 9 shown in FIG.
Due to the reason 3), the second potential state can be obtained more rapidly than in the conventional data line potential setting circuit of FIG.

In the data line potential setting circuit of FIG. 8 (b), the value of the bias source connected to the current supply means is set to the level of V _2H of V _2H in the second potential state to the level of V _2L or an intermediate level of MISFET.
The threshold voltage (about 0.7V) is almost equal to that. If the MISFETs Q ₉ and Q ₁₀ are enhancement type MISFETs and are operating in the saturation region, the level of the common data line does not rise above the second potential state. Therefore, in this case, the clamp means 9 may not be used.

The data line potential setting circuit of FIG. 8 (c) is adapted to apply the first write recovery signal φ _WR1 to the switch means 9 ′ and the current supply means 9, and the MISFET Q _{9 of the} current supply means 9 ″. , Q ₁₀ are operated in the non-saturation region so that one common data line can be rapidly charged together with the switching means 9 '.

The data line potential setting circuit of FIG. 8 (d) uses Vcc ″ as the bias source of the data line potential setting circuit of FIG. 8 (c), and the value of Vcc ″ is V _{2H in} the second potential state. Level of V
_{It is set to} a level of _2L or to be almost equal to the level in the middle between them so that the level of the common data line does not rise above the level of the second potential state.
Also in the case of this circuit, the clamp means 9 may not be used in particular.

In the data line potential setting circuit of FIG. 8 (e), the bias source of the current supply means 9 ″ is the first or second write recovery signals φ _WR1 and φ _WR2 .
The same effects as those in FIGS. (A) to (d) can be obtained.

The data line potential setting circuit of FIG. 8 (f) is such that the current supplying means 9 ″ is always operated, but in this case as well, the action of the switching means 9 ′ makes it more effective than the conventional data line potential setting circuit. It is quick to obtain the potential state of 2. However, in the case of this circuit, the driving capability of the current supply means needs to be smaller than that of the circuit means (for example, the writing circuit 6) that sets the data line to the first potential state.

Bias sources Vcc 'and Vcc "used in the data line potential setting circuits of FIGS. 8 (c) and 8 (d) are potential conversion circuits composed of MISFETs Q _{93 to} Q ₉₇ as shown in FIG. 11, for example. Can be obtained by using.

The data line potential setting circuit shown in FIG. 9 is another embodiment in which it comprises a switching means 9 ', a current supply means 9 ", and a clamp means 9. The switching means 9'and the current supply means 9" are provided as an eighth embodiment. The circuit shown in FIG. 6C is used, and substantially the same effect as that of the data line potential setting circuit shown in FIG. 5 can be obtained. In addition, in this kind of combination, it is naturally conceivable to add a clamping means to the circuits of FIGS. 8B, 8D, and 8E to form the data line potential setting circuit.

The data line potential setting circuit shown in FIG. 10, 'is obtained by so configuring the clamping means 9 "only in this case, T ₂ shown in FIG. 7' switching means 9 period, the current supply means 9 It is possible to prevent the potential level of the data line from undesirably rising due to "".

A MISFET is used as the switching means 9 ', but a bipolar transistor may be used. Further, the number of elements formed between the common data lines is not limited to one and may have a plurality of logic circuits.

The current supply means 9 ″ is an enhancement type MISFET
However, a depletion type may be used.
Further, it may be a current supply means such as a bipolar transistor other than MISFET, a diode, or a resistor. It may also include a plurality of elements connected between the bias source and the data line.

Further, the clamp means 9 is not limited to that shown in FIG. 5, and various modified circuits having the same function can be considered.

[Brief description of drawings]

FIG. 1 is a schematic MIS memory circuit diagram using a data line potential setting circuit, FIG. 2 is a write circuit diagram used in the MIS memory circuit, and FIG. 3 is a read circuit diagram used in the MIS memory circuit. 4 is a timing chart of the MIS memory circuit of FIG. 1, FIG. 5 is a schematic MIS memory circuit using the data line potential setting circuit according to the present invention, FIG. 6 is a write recovery signal generation circuit diagram, and FIG. FIG. 8 is a timing chart of the MIS memory circuit of FIG. 5, FIG. 8 (a) (b) (c) (d) (e) (f), and FIG.
FIG. 10 and FIG. 10 are data line potential setting circuit diagrams according to another embodiment of the present invention, FIG. 11 is a voltage conversion circuit diagram, and FIG. 12 is a MISFET output voltage (V _DS ) −output current (I _DS ). It is a characteristic view which shows a characteristic. 1 ... Memory matrix, 2 ... Row selection address decoder, 3 ... Column gate means, 4 ... Column selection address decoder, 5 ... Load means, 6 ... Writing circuit,
7 ', 7 ... Readout circuit, 8 ... Conventional data line potential setting circuit, 9 ... Data line potential setting circuit according to the present invention,
10 …… Light recovery signal generation circuit, 11 …… Potential conversion circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/11 G11C 11/34 354 C

Claims (1)

[Claims] 1. A pair of gate-drain cross-connected
MISFET, a pair of load elements connected between the drain and bias source of the pair of MISFETs, and the pair of MISFETs
Pair of MISFETs for data input / output coupled to the drains of the
A memory matrix having a plurality of memory cells each composed of a column switch means, a column switch means, and one of the memory cells connected to the memory matrix via the column switch means. A plurality of common data lines, which are set to the first level and the other is set to the second level which is a low level, are connected in series between the bias source and the ground terminal of the circuit, and a plurality of voltage dividers divide the voltage of the bias source. A bias circuit that includes a MISFET, forms a bias voltage at an intermediate level between the first level and the second level based on a voltage formed by the plurality of MISFETs, and outputs the bias voltage to its output terminal; A pair of first switches composed of MISFETs provided between the output terminal of the bias circuit and the pair of common data lines. A data line potential setting circuit including a switching means and a second switching means composed of a MISFET provided between the pair of common data lines, and a data line potential setting circuit for selecting a memory cell from among the plurality of memory cells to be selected. A timing signal forming means for forming a timing signal for forming a timing signal for temporarily turning on the pair of first switching means and second switching means prior to data reading. MIS memory circuit.