JPH0756884B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to store data by applying a voltage and passing a current to cause a transition from a high resistance state to a low resistance state. The present invention relates to a method of manufacturing a semiconductor device that mainly functions as a so-called "anti fuse".

[Conventional technology]

The above-mentioned anti-fuse is used by applying the function that when a voltage is applied to an electrode of a semiconductor element to cause a current to flow, the electrode transitions from a non-conducting state to a conducting state. In other words, the anti-fuse forms a semiconductor element having a characteristic or function opposite to that of a "fuse" that disconnects a wiring made of, for example, polycrystalline silicon from a conductive state to a non-conductive state as is conventionally done. is there.

Conventionally, chalcogenide, amorphous silicon, and the like have been known as substances that serve as the anti-fuse, and practical examples thereof include those disclosed in the following documents. Hereinafter, the characteristics of the anti-fuse shown in these documents will be briefly described.

Reference 1: Japanese Patent Publication No. 47-32944: Amorphous high-resistance semiconductor material is given energy such as electron irradiation or laser irradiation to bring it into a stable state of low resistance rather than stable state of high resistance.

Reference 2: Japanese Examined Patent Publication No. S57-4038 ... A PROM device including high-resistance polycrystalline silicon whose resistance value is irreversibly changed by an applied electric field.

Reference 3: Japanese Patent Application Laid-Open No. 54-88739. An EEPROM device having a tellurium-based chalcogenide as a constituent, which has a high electric resistance in the amorphous state and a low electric resistance in the crystalline state.

As the application of the anti-fuse, it is applied to a simple wiring connection switch in an IC, a PLA (programmable logic array), a memory redundancy circuit, a PROM, or the like, or its application is being considered.

FIG. 2 is a schematic sectional view showing a structure of a semiconductor element which is used as the anti-fuse and is most similar to the semiconductor element of the present invention.

In the figure, 201 is a semiconductor substrate, and 202 is a semiconductor substrate.
Impurity diffusion layers formed on the surface of 201, 203 and 203a are interlayer insulating films, 204 is a wiring electrode, 205 is amorphous silicon,
206 is an upper electrode formed on the amorphous silicon 205. The amorphous silicon 205 is a high resistance element, and the upper electrode 206 is made of a good conductor and is formed simultaneously with the wiring electrode 204.

In the above structure, the wiring electrode 204 and the amorphous silicon 205 are formed in contact with the surfaces of both ends of the impurity diffusion layer 202, and the amorphous silicon is formed between the upper electrode 206 and the lower electrode formed by the impurity diffusion tank 202. It has a structure with 205 inserted. In this structure, the high resistance amorphous silicon 205 functions as a main constituent part of the above-mentioned anti-fuse. That is, a voltage is applied between the upper electrode 206 and the wiring electrode 204 connected to the lower electrode,
When a current is passed, the portion centering on the amorphous silicon 205 between both electrodes irreversibly transits from the high resistance state to the low resistance state. That is, amorphous silicon between both electrodes
A memory element can be formed by utilizing the fact that a portion around 205 is changed from an insulating state to a conductive state, which makes it possible to distinguish the element from which no current flows.

[Problems to be Solved by the Invention]

In the conventional semiconductor device as described above, the resistance value before transition R _off is higher and the resistance value after transition is higher in terms of device performance.
Lower R _on is desirable.

The R _off of amorphous silicon is somewhat lower than that of an insulating film such as an oxide film, which is not preferable. On the other hand, it is superior in reliability and has advantages and disadvantages as compared with the element using the insulation film breakdown. Further, in order to lower R _on , it is effective to include an acceptor ion or a donor ion in amorphous silicon, but since R _{off in} a state before transition becomes considerably low, a conventional element has a preferable structure. Was not.

The present invention has been made to overcome the above-mentioned problems, and it is possible to secure R _off comparable to that of an insulator in amorphous silicon, and also to utilize the effect of R _on lowering due to inclusion of impurity ions, and on the same substrate. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a structure that does not adversely affect other semiconductor devices.

[Means for Solving the Problems]

According to the method of manufacturing a semiconductor element of the present invention, a voltage is applied between a first conductive layer having a lower electrode and a second conductive layer having an upper electrode to cause a current to flow, thereby changing from a high resistance state to a low resistance state. In a method of manufacturing a semiconductor device formed between the lower electrode and the upper electrode, which functions as an anti-fuse that transitions to a state, a step of forming an interlayer insulating film on at least the lower electrode; A step of forming a contact hole in the interlayer insulating film, a step of forming a silicon insulating film inside the contact hole, a step of forming an amorphous silicon layer above the silicon insulating film, and a step of forming the upper electrode above the amorphous silicon layer. And at least a forming step.

Further, according to the method of manufacturing a semiconductor element of the present invention, a voltage is applied between a first conductive layer having a lower electrode and a second conductive layer having an upper electrode to cause a current to flow. In a method of manufacturing a semiconductor device formed between the lower electrode and the upper electrode, which functions as an anti-fuse that transitions to a low resistance state, a step of forming an interlayer insulating film on at least the lower electrode, the lower portion Forming a contact hole in the interlayer insulating film on the electrode; forming an amorphous silicon layer at least inside the contact hole; forming a silicon insulating film above the amorphous silicon layer; and forming a silicon insulating film above the silicon insulating film. And a step of forming the upper electrode.

Further, the silicon insulating film is formed to have a film thickness of 50Å to 100Å.

[Action]

In the present invention, the element functioning as an anti-fuse in the semiconductor element has a four-layer structure of the upper electrode, the amorphous silicon, the silicon insulating film, and the lower electrode. Therefore, R _off is higher than that of the silicon insulating film having a high specific resistance. The resistance is secured, and the reliability of the anti-fuse is secured by the characteristics of amorphous silicon. Since the silicon insulating film is used for the purpose of ensuring a high R _off , it may be very thin, and it can be easily broken when a program voltage is applied by thinning it, so it has almost an effect _on R _on. It is easy to reduce the resistance.

For the amorphous silicon region in the four-layer structure doped with Group III or Group V impurities, when ion implantation is carried out at about 10 ¹⁵ cm ^{-3, the} Joule generated by the current due to the application of the program (writing) voltage. Due to the generation of heat, some of the amorphous silicon melts, and when that part cools it will probably turn into something like a polycrystal. At this time, the doped impurity element can be lowered into R _on by being taken into and activated by something like this crystal (this word is generally called a filament in academic fields and patent fields). .

〔Example〕

Embodiment 1: FIG. 1 is a structural explanatory view by a schematic sectional view of a semiconductor device showing an embodiment of the present invention. 101 is, for example, a silicon single crystal semiconductor substrate, 102 is an n ⁺ type or p ⁺ type impurity diffusion layer (lower electrode), 103 and 103a are interlayer insulating films, 104 is a wiring electrode such as Al, 105 is amorphous silicon, 106 Is an upper electrode of Al or the like, 107 is a silicon insulating film formed of SiO ₂ or Si ₃ N ₄ , and 108 is a contact hole. Upper electrode 106, amorphous silicon 105, silicon insulating film 107, and lower electrode 10
2 and 4 form a four-layer structure electrode, which is the main component of the anti-fuse. The above structure is characterized in that a silicon insulating film 107 is interposed between the lower electrode 102 made of an impurity diffusion layer and the amorphous silicon 105, as compared with the conventional example shown in FIG.

As in the embodiment of FIG. 1, a silicon insulating film 107 is provided between the amorphous silicon 105 and the lower electrode (impurity diffusion layer) 102.
In the case of interposing, a silicon insulating film is formed on the surface in contact with the silicon substrate during the growth of amorphous silicon, and since this insulating film is amorphous, homogeneous amorphous silicon can be formed. Therefore, the stability and reproducibility of the program voltage / current are improved. This point is significantly larger than that in the case of growing amorphous silicon on a substrate as in the conventional example of FIG. 2, abnormal growth according to silicon crystals is likely to grow, and it is difficult to form homogeneous amorphous silicon. It can be said that it showed a significant improvement. The amorphous silicon 105 is the impurity diffusion layer 102.
It may be doped with an impurity element of Group III or Group V of the same conductivity type as above, and in this case, R _on can be lowered as compared with the case where no impurity is doped, as described above.

Embodiment 2 FIG. 3 is a structural explanatory view by a schematic sectional view showing another embodiment of the semiconductor device according to the present invention. The same or corresponding parts as those of the embodiment of FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In the embodiment of FIG. 3, amorphous silicon 105
The silicon insulating film 107 is interposed between the upper electrode 106 and the upper electrode 106. Also in this case, similar to the first embodiment, the amorphous silicon 105 may be doped with a group III or group V impurity element to reduce R _on .

When the silicon insulating film 107 is provided between the amorphous silicon 105 and the upper electrode 106 as in the embodiment shown in FIG. 3, a barrier metal such as TiN is used under the upper electrode 106, for example. In the unlikely event that a pinhole occurs and Al invades,
Since the reaction between Al and the silicon insulating film 107 is small, there is an advantage that a trouble such as a decrease in yield does not occur. This point is
Since the reaction of amorphous silicon with Al is remarkable, for example, when the above-mentioned barrier metal is not used, the reaction proceeds even at about 300 ° C. Therefore, a short circuit may occur during manufacturing of the device, resulting in a defect. Further, the present invention overcomes the problem that has occurred in the conventional example as shown in FIG. 2 in that pinholes and the like are generated even if a barrier metal is used and the yield is reduced.

Embodiment 3: FIG. 4 is a structural explanatory view by a schematic sectional view showing another embodiment of the semiconductor device according to the present invention.

In this embodiment, 404 polycrystalline silicon is used as the lower electrode, and a four-layer structure of a silicon oxide film 408, amorphous silicon 405, and an upper electrode 407 is formed on the polycrystalline silicon. It is programmed by Joule heat generated when a voltage is applied between the electrodes and a current is applied, but by using polycrystalline silicon for the lower electrode and enclosing the periphery with a silicon oxide film as in this example. The thermal conductivity can be reduced, and the temperature rise due to Joule heat can be accelerated, and a highly efficient program can be performed.

Further, the silicon oxide film 408 may be present between the polycrystalline silicon 404 and the amorphous silicon 405, or may be present between the amorphous silicon 405 and the upper electrode 407 in addition to the present embodiment. However, it may exist on both sides of the amorphous silicon 405.

Example 4 An example of a method of manufacturing a semiconductor device according to the present invention will be described with reference to the semiconductor device shown in the example of FIG.
The manufacturing process of (f) will be described in order. The step (c2) is an additional step in the case of doping the amorphous silicon with an impurity element. However, this step is omitted if it is not necessary to dope.

Step (a): An impurity diffusion layer 102 is formed on a semiconductor substrate 101 made of silicon (Si), and an interlayer insulating film made of SiO ₂ or Si ₃ N ₄ is formed on the entire surface.
After forming 103, a contact hole 108 is formed by photolithography at a predetermined location above the impurity diffusion layer 102 where amorphous silicon is to be deposited. Step (b): SiO ₂ is deposited by 100 Å or less by CVD, for example, 50 Å to form a silicon insulating film 107 on the bottom of the contact hole 108.

(C) step ... Amorphous silicon by CVD method at 560 ° C
105 is formed to a thickness of about 1500Å, and is also embedded in the contact hole 108.

Step (c2): This step is performed when doping the amorphous silicon 105 with an impurity element. For example, in the case of P (group V element) as an n-type impurity, P ⁺ is 60 Kev, 1 × 10 ¹⁵ to 1
Ion implantation is performed under the condition of × 10 ¹⁶ cm ^-3 to dope P into the amorphous silicon 105. In the case of B (group III element) as a p-type impurity, BF ₂ ⁺ is 80 Kev, 1 × 10 ¹⁵
Ion implantation is performed under the condition of 1 × 10 ¹⁶ cm ^-3 to dope B.

Step (d): Amorphous silicon 105 is photo-etched and patterned to form electrode-shaped amorphous silicon 105.

Step (e): After depositing an interlayer insulating film 103a on the entire surface, contact holes 108a and 109 for connecting lead wires are formed. Contact hole 108a is amorphous silicon
The contact hole 109 is formed in the impurity diffusion layer 10 up to the upper surface of 105.
It is formed so as to reach the upper surface of 2.

(F) Step ... First, a barrier metal of, for example, Ti—TiN, and then Al—Si is deposited by a sputtering method, and a patterning process is performed to form the wiring electrode 104 and the upper electrode 106.

This completes the formation of the basic structure of the embodiment element shown in FIG. In the step (b), the SiO ₂ film is formed, for example, by a thermal oxidation method at 900 ° C. for 30 minutes in an atmosphere having an O ₂ concentration of 2% in N ₂ gas even if a SiO ₂ film of 50 to 100 Å is grown. Good. As another _{method, H 2 SO 4 + H 2} O 2 SiO 2 in which several 10Å grown in
It may be a film, or may be a film obtained by annealing this SiO ₂ at 900 ° C.

Embodiment 5: Another embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to the semiconductor device shown in the embodiment of FIG.
The steps (E) will be described in this order. The step (B2) is an additional step in the case of doping the amorphous silicon with an impurity element, but since the contents thereof are the same as the step (C2) of Example 3, the description thereof will be omitted.

Step (A) ... Impurity diffusion layer 1 on silicon semiconductor substrate 101
After forming 02 and forming an interlayer insulating film 103 of SiO ₂ or SiN ₄ on the entire surface, a contact hole 108 is formed by photolithography at a predetermined position above the impurity diffusion layer 102 where the amorphous silicon 105 is to be formed.

Step (B): Amorphous silicon (film) 105 is formed to a thickness of about 1500 Å by a CVD method at 560 ° C, and is embedded in the contact hole 108 as well.

Step (B2): When doping Group III or Group V impurities into the amorphous silicon 105, P or B is doped by ion implantation in the same manner as in Step (C2) of Example 3.

Step (C) ... Amorphous silicon (film) 105 is etched by dry etching using CF ₄ to form electrode-shaped amorphous silicon 105.

Step (D) ... After depositing an interlayer insulating film 103a on the entire surface, contact holes 108a and 109 for connecting lead wires are formed.

Step (E): SiO ₂ (film) 107 is formed to a thickness of about 100 Å or less by a CVD method. SiO ₂ (film) 107 other than on the amorphous silicon (film) 105 is removed by photoetching.

Step (F) ... Thereafter, the wiring electrode 104 and the upper electrode 106 are formed in the same manner as the step (f) of Example 3, and the process up to this stage is completed.

The semiconductor element according to the present invention is not only effective for use as an anti-fuse, but also applicable to the PLA and a semiconductor device formed by being incorporated in a general memory device. Further, it can be directly used as a PROM element as described above, or can be used as a wiring connection switch for other devices. In other words, one of the applications of the wiring connection switch is that the user can create an arbitrary IC on the desktop by inserting it into the wiring connection location of an IC that has a macro cell such as a standard cell for a specific purpose. is there.

〔The invention's effect〕

As described above, according to the present invention, since the conventional amorphous silicon is used for the portion used as the anti-fuse of the semiconductor element, the program element is configured by disposing the insulating film on the upper side or the lower side thereof. High R
_Off is secured by a silicon insulating film, and reliability is secured by amorphous silicon. Therefore, due to the synergistic effect of the above two actions, the program current during operation
Voltage stability and reproducibility are enhanced. Therefore, a program element having high R _off and lower R _on characteristics than the conventional one can be obtained.

Further, according to this structure, even if the amorphous silicon is doped with impurities due to a decrease in R _on , R _off is not affected, and high R _off and low R _on characteristics can be realized. In particular, in the structure as shown in FIG. 3, the reaction between the upper electrode material itself or a part thereof, for example, a barrier metal or the like and amorphous silicon can be prevented, so that the manufacturing process becomes easy.

From the above, the formation of the anti-fuse and its application to the PLA and memory device incorporated as its application become easy and contribute to the reduction of the overall cost.

Further, in the present invention, the lower electrode is replaced with the diffusion region formed on the semiconductor substrate and polycrystalline silicon or the like formed on the semiconductor substrate is used, and the oxide film is formed between the polycrystalline silicon and the amorphous silicon or between the amorphous silicon and the upper portion. If provided between the electrodes or both of them, the following effects are obtained in addition to the above-mentioned effects.

In other words, when the oxide film is formed from a thermal oxide film, the thermal effect on the semiconductor substrate can be reduced, and this can suppress the redistribution of impurities in the diffusion region in the substrate that constitutes the semiconductor element, thus improving reliability. The advantage is that a high-performance semiconductor device can be obtained.

The following effects can be obtained by using polycrystalline silicon provided on the substrate with an insulating film in place of the impurity layer formed on the substrate as the lower electrode.

1. Since the oxidation rate on polycrystalline silicon is faster than that on single crystal silicon, it can be processed at low temperature for a short time, and the effect on the underlying transistor characteristics can be reduced.

2. The oxide film grown on polycrystalline silicon has a lower breakdown voltage than the film grown on single crystal silicon, and the increase in programming voltage can be reduced.

3. The oxide film grown on polycrystalline silicon has poorer crystallinity than the film grown on single crystal silicon and is effective for the amorphous silicon film. If the crystallinity is good, amorphous silicon may be polycrystallized at the interface with the oxide film.

[Brief description of drawings]

FIG. 1 is a sectional view showing an essential part of an embodiment of a semiconductor device according to the present invention, FIG. 2 is a sectional explanatory view showing the structure of a conventional semiconductor device, and FIG. 3 is a view showing another embodiment of the present invention. FIG. FIG. 4 is a cross-sectional view of essential parts showing another embodiment of the present invention. In the figure, 101, 102 ... Silicon semiconductor substrate 102, 202 ... Impurity diffusion layer 103, 103a ... Interlayer insulating film 104, 204 ... Wiring electrode 105, 205 ... Amorphous silicon 106, 206 ... Upper electrode 107 ...... Silicon insulation film 108, 108a …… Contact hole 109 …… Contact hole 401 …… Silicon substrate 402,403 …… Insulation film 408 …… Silicon oxide insulation film 405 …… Amorphous silicon 407 …… Upper electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/10 491 7210-4M

Claims (3)

[Claims] 1. An anti-phase transition from a high resistance state to a low resistance state by applying a voltage between a first conductive layer having a lower electrode and a second conductive layer having an upper electrode to flow a current. In the method of manufacturing a semiconductor element that functions as a fuse and is formed between the lower electrode and the upper electrode, a step of forming an interlayer insulating film on at least the lower electrode, the interlayer insulating film on the lower electrode. A step of forming a contact hole, a step of forming a silicon insulating film inside the contact hole, a step of forming an amorphous silicon layer above the silicon insulating film, and a step of forming the upper electrode above the amorphous silicon layer. A method for manufacturing a semiconductor device, which comprises at least a semiconductor device. 2. An anti-phase transition from a high resistance state to a low resistance state by applying a voltage between a first conductive layer having a lower electrode and a second conductive layer having an upper electrode to flow a current. In the method of manufacturing a semiconductor element that functions as a fuse and is formed between the lower electrode and the upper electrode, a step of forming an interlayer insulating film on at least the lower electrode, the interlayer insulating film on the lower electrode. A step of forming a contact hole, a step of forming an amorphous silicon layer at least inside the contact hole, a step of forming a silicon insulating film above the amorphous silicon layer, a step of forming the upper electrode above the silicon insulating film, A method for manufacturing a semiconductor device, comprising: 3. The thickness of the silicon insulating film is 50Å to 100Å
Claim 1 characterized in that it is formed to a thickness of
Item 2. A method for manufacturing a semiconductor element according to Item 2 or Item 2.