JPH0756911B2 - Method for manufacturing hybrid integrated circuit device - Google Patents
Method for manufacturing hybrid integrated circuit deviceInfo
- Publication number
- JPH0756911B2 JPH0756911B2 JP63239959A JP23995988A JPH0756911B2 JP H0756911 B2 JPH0756911 B2 JP H0756911B2 JP 63239959 A JP63239959 A JP 63239959A JP 23995988 A JP23995988 A JP 23995988A JP H0756911 B2 JPH0756911 B2 JP H0756911B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- circuit board
- lead
- soldering
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Lead Frames For Integrated Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【発明の詳細な説明】 [産業上の利用分野] 本発明は混成集積回路装置の製造方法に関し、さらに詳
しくは混成集積回路基板への外部接続用リードの半田付
け法に特別の改善を含む同回路装置の製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a hybrid integrated circuit device, and more particularly to a method for soldering an external connection lead to a hybrid integrated circuit board, which includes a special improvement. The present invention relates to a method for manufacturing a circuit device.
[従来の技術] 従来の混成集積回路装置の一般的製造方法を工程順に示
せば第6a〜6f図の如くであり下記の工程〜から成っ
ている。[Prior Art] A general method for manufacturing a conventional hybrid integrated circuit device is shown in the order of steps as shown in FIGS. 6a to 6f, and includes the following steps.
アルミナ基板1の一方または両方の主面にスクリー
ン印刷によりAg-Pd等の導体材料ペーストを塗布し焼き
付け処理して厚膜配線導体2および部品ランド3を形成
し、該アルミナ基板の少なくとも一方の縁辺部にそれぞ
れ前記厚膜配線導体に接続するように複数の外部接続用
リードのリードランド4を前記と同様に形成した後、前
記厚膜配線導体に接続するようにスクリーン印刷により
RuO2等の抵抗材料ペーストを塗布し焼き付け処理して厚
膜抵抗体5を形成する(第6a図)。A thick film wiring conductor 2 and a component land 3 are formed by applying a conductor material paste such as Ag-Pd on one or both main surfaces of the alumina substrate 1 by screen printing and baking it, and at least one edge of the alumina substrate 1 The lead lands 4 of the leads for external connection are formed in the same manner as described above so as to be connected to the thick film wiring conductors, respectively, and then screen printed so as to connect to the thick film wiring conductors
A resistive material paste such as RuO 2 is applied and baked to form a thick film resistor 5 (FIG. 6a).
こうして得られた厚膜回路基板主面上の前記部品ラ
ンド3およびリードランド4を除外した部分にスクリー
ン印刷により保護ガラスを印刷し焼き付け処理して保護
ガラス層6を形成する(第6b図)。Protective glass is printed by screen printing on a portion of the main surface of the thick film circuit board thus obtained excluding the component lands 3 and the lead lands 4 and baked to form a protective glass layer 6 (FIG. 6b).
上記により得られた厚膜回路基板の前記部品ランド
3上に半田ペーストを印刷した後、チップ状電子部品7,
8,9等を搭載し、リフロー半田付け炉で熱処理して部品
ランドにこれらの電子部品を半田付け(S)により導電
固着する(第6c図)。After printing the solder paste on the component land 3 of the thick film circuit board obtained as described above, the chip-shaped electronic component 7,
8 and 9 etc. are mounted and heat treated in a reflow soldering furnace to electrically conductively fix these electronic components to the component land by soldering (S) (Fig. 6c).
上記の電子部品を実装した厚膜回路基板上に形成し
たそれぞれの厚膜抵抗体5にレーザートリミング装置に
より切り溝10を形成して抵抗値の調整を行う(第6d
図)。A laser trimming device is used to form a kerf 10 in each thick film resistor 5 formed on the thick film circuit board on which the above electronic components are mounted to adjust the resistance value (6d).
Figure).
上記により得られた混成集積回路基板上に設けられ
ている前記複数のリードランドにそれぞれ外部接続用リ
ード11のクリップ部11aを嵌合させる(第6e図)。The clip portions 11a of the external connection leads 11 are fitted into the plurality of lead lands provided on the hybrid integrated circuit board obtained as described above (Fig. 6e).
これらのリード嵌合部が半田12中に没するように回
路基板を半田中に浸漬して、各リードランドに前記リー
ドのクリップ部11aを半田付けする(第6f図)。The circuit board is dipped in the solder so that the lead fitting portions are immersed in the solder 12, and the lead clip portions 11a are soldered to the lead lands (FIG. 6f).
上記により得られた混成集積回路基板を、前記外部
接続用リード11のリード部11bとタイバー部11cの部分を
除いて、他の全部分をエポキシ樹脂あるいはフェノール
樹脂等の耐湿性を有する絶縁塗料にディップした後、熱
処理により該絶縁性樹脂塗料を硬化させて保護被膜を形
成する。The hybrid integrated circuit board obtained as described above, except for the lead portion 11b and the tie bar portion 11c of the external connection lead 11, all the other parts to an insulating coating having a moisture resistance such as epoxy resin or phenol resin. After dipping, the insulating resin coating material is cured by heat treatment to form a protective film.
上記により保護被膜を形成した混成集積回路の一部
を成している複数の外部接続用リードから、それらを連
結しているタイバー部11cを切り離して混成集積回路装
置を得る。From the plurality of external connection leads forming part of the hybrid integrated circuit on which the protective film is formed as described above, the tie bar portion 11c connecting them is cut off to obtain the hybrid integrated circuit device.
[発明が解決しようとする課題] しかしながら、上記従来の製造方法により混成集積回路
装置をつくる場合には、第5図に示すように、混成集積
回路基板cの縁辺部に設けたリードランドにクリップリ
ード(外部接続用リード)bを半田付けする工程におい
て、リードランドに嵌合させたクリップリードの嵌合部
が半田aの液面下に没するようにするため回路基板の縁
辺部を半田中に半田液面よりある寸法dだけ浸漬させる
必要がある。このため回路基板縁辺部はリードランドで
ない部分eも半田の液面下に沈められることになるの
で、このeの部分は当然電子部品等を搭載できないデッ
ドスペースとなる。そればかりでなく、前記クリップ嵌
合部の近くに電子部品が実装されている場合は、電子部
品の半田付け部分が溶融半田の液面に極めて接近するこ
とになるため、その半田付け部分が再加熱され、その部
分の半田が溶融して電子部品が落下してしまうというこ
とが起こり得た。したがって、従来の方法による場合
は、たとえば電子部品gの搭載はその半田付け部分が回
路基板c上のデッドスペースeの部分にかからないよう
に搭載しなければならないばかりでなく、電子部品の半
田付け部分はデッドスペースの境界線(すなわち半田の
液面が回路基板cの面に接してつくる線)hにあまり接
近しないような位置に搭載しなければならなかった。[Problems to be Solved by the Invention] However, when a hybrid integrated circuit device is manufactured by the conventional manufacturing method described above, as shown in FIG. 5, a clip is formed on a lead land provided on an edge portion of the hybrid integrated circuit board c. In the process of soldering the lead (external connection lead) b, the edge portion of the circuit board is being soldered so that the fitting portion of the clip lead fitted to the lead land is submerged below the liquid surface of the solder a. It is necessary to immerse the solder in a certain distance d from the solder liquid surface. Therefore, in the edge portion of the circuit board, the portion e which is not the lead land is also submerged below the liquid surface of the solder, and this portion e naturally becomes a dead space in which electronic parts and the like cannot be mounted. Not only that, when electronic parts are mounted near the clip fitting part, the soldered part of the electronic part comes very close to the liquid surface of the molten solder, so that the soldered part is re-attached. It may happen that the solder in the portion is heated and the electronic component falls down. Therefore, in the case of the conventional method, for example, when mounting the electronic component g, not only the soldering portion must be mounted so as not to reach the dead space e on the circuit board c, but also the soldering portion of the electronic component is mounted. Had to be mounted at a position that did not come too close to the boundary line of the dead space (that is, the line formed by the liquid surface of the solder in contact with the surface of the circuit board c).
何故なら、半田の熱で再加熱されてその部分の半田が溶
融して半田付けの一部または全部が部品ランドから離れ
てしまう恐れがあるからである。したがって従来法によ
る場合は、第5図に例示するように、たとえば電子部品
gを、デッドスペースの境界線hからある程度離せれた
位置に搭載しなければならなかった。すなわち、第5図
にeで示すデッドスペースとなる部分およびこれに極く
近い部分には電子部品を実装することはできなかった。
したがって、特に高密度実装を必要とする場合などに
は、電子部品を実装した回路基板に作業者が半田鏝を用
いて前記複数の外部接続用リードをそれぞれ手作業によ
り別の工程で半田付けしなければならず、生産性が著し
く低かった。This is because there is a risk that the solder will be reheated by the heat of the solder and the solder in that portion will melt and part or all of the soldering will separate from the component land. Therefore, in the case of the conventional method, as illustrated in FIG. 5, for example, the electronic component g had to be mounted at a position separated from the boundary h of the dead space to some extent. That is, electronic parts could not be mounted on the dead space shown in FIG. 5e and the part very close thereto.
Therefore, especially when high-density mounting is required, an operator manually solders the plurality of external connection leads to a circuit board on which electronic components are mounted by using a soldering iron in separate steps. It had to be done and productivity was extremely low.
本発明の目的は、上記従来の問題点を解決して、従来は
デッドスペースとならざるを得なかった部分にまで電子
部品を実装できるばかりでなく、リードランドの近傍や
半田の液面に近い部分に実装された電子部品を落下させ
ることなく、効率良く、外部接続用リードを回路基板に
半田付けすることが可能な混成集積回路装置の製造方法
を提供することにある。An object of the present invention is to solve the above-mentioned conventional problems and not only to mount an electronic component in a portion that has conventionally been forced to become a dead space, but also to be near a lead land or a liquid surface of solder. An object of the present invention is to provide a method for manufacturing a hybrid integrated circuit device capable of efficiently soldering an external connection lead to a circuit board without dropping an electronic component mounted on a part thereof.
[課題を解決するための手段] 回路基板の少なくとも一方の縁辺部に通常設けられるリ
ードランドに外部接続用リードを半田付けするに際し、
半田付け作業時において回路基板の外部接続用リードの
クリップ嵌合部に隣接する水平方向の延長部分となるク
リップ嵌合部でない縁辺部(すなわち第1図、第2図お
よび第3図等のeで示す部分)を、特殊の材質と構造を
持つカバー(被覆用治具)fで覆ってこの部分が直接溶
融半田に接触しないようにすると共に、表面張力の作用
による該カバーの使用効果によって溶融半田の熱が回路
基板上の搭載部品の半田付け部分に伝達されにくくなる
ように工夫し、これによって、前述の課題を解決するこ
とができた。上記eの部分は、従来の方法では、電子部
品を搭載できないデッドスペースとなっていたが、本発
明の方法に基づきカバーの形状および構造を工夫して実
装電子部品を保護すれば、このeの部分に電子部品が搭
載されていても流れ作業工程で外部接続用リードの半田
付けができるという利益も加わることになる。[Means for Solving the Problem] When soldering the external connection lead to the lead land usually provided on at least one edge portion of the circuit board,
An edge portion (that is, e in FIGS. 1, 2, and 3) that is a horizontal extension portion adjacent to the clip fitting portion of the external connection lead of the circuit board during the soldering work and is not the clip fitting portion. Is covered with a cover (coating jig) f having a special material and structure so that this part does not come into direct contact with the molten solder, and melting is performed by the effect of using the cover due to the action of surface tension. The heat of the solder has been devised so that it is less likely to be transferred to the soldering portion of the mounted component on the circuit board, and by doing so, the above-mentioned problems can be solved. The above-mentioned part e is a dead space in which electronic parts cannot be mounted by the conventional method, but if the shape and structure of the cover is devised based on the method of the present invention to protect the mounted electronic parts, this e Even if an electronic component is mounted on the portion, there is an added benefit that the lead for external connection can be soldered in a flow work process.
上に述べた本発明の方法は、次のように要約することが
できる。The method of the present invention described above can be summarized as follows.
回路基板の少なくとも一方の縁辺部に設けられているリ
ードランドに、外部接続用リードのクリップ部を嵌合さ
せた後、該クリップ嵌合部が充分に半田中に没する位置
まで回路基板を半田中に浸漬して前記リードの回路基板
への半田付けを行なう工程を含む混成集積回路装置の製
造方法において、半田付け作業時に回路基板の前記クリ
ップ嵌合部の隣接水平方向延長部分となるクリップ嵌合
部でない前記延長部分または少なくとも前記延長部分を
含むより広い部分を、少なくとも外周面が半田に濡れに
くい耐半田性の材料で構成されていて前記回路基板の主
面方向に対し垂直方向に突出した鍔部を有する横断面が
略コ字型の被覆用治具で覆って回路基板の縁辺部を半田
槽内に浸漬することによって回路基板上に設けたリード
ランドに外部接続用リードを半田付けすることを特徴と
する混成集積回路の製造方法。After fitting the clip part of the lead for external connection to the lead land provided on at least one edge of the circuit board, solder the circuit board to a position where the clip fitting part is sufficiently immersed in the solder. In a method of manufacturing a hybrid integrated circuit device, which comprises a step of immersing the leads in a circuit board and soldering the leads to the circuit board, a clip fitting to be an adjacent horizontal extension portion of the clip fitting portion of the circuit board during soldering work. The extended portion that is not a joint portion or a wider portion including at least the extended portion is formed in a direction perpendicular to the main surface direction of the circuit board, at least the outer peripheral surface of which is made of a solder-resistant material that is difficult to wet with solder. Externally connected to a lead land provided on the circuit board by covering the edge of the circuit board in a solder bath with a covering jig having a U-shaped cross section with a flange. Method for manufacturing a hybrid integrated circuit, characterized by soldering the leads.
また、上記製造方法において使用される被覆用治具は次
のように要約することができる。The coating jig used in the above manufacturing method can be summarized as follows.
半田付け作業時に回路基板の任意の部分を被覆するため
に、外周面が半田に濡れにくい耐半田性の材料で構成さ
れていて断面が略コ字型であり、前記回路基板の主面方
向に対し垂直方向に突出した鍔部を有していることを特
徴とするディップ半田付け用の被覆用治具。In order to cover any part of the circuit board during soldering work, the outer peripheral surface is made of a solder-resistant material that does not easily get wet with solder, and its cross section is approximately U-shaped. On the other hand, a covering jig for dip soldering is characterized in that it has a flange portion that protrudes vertically.
本発明の方法に使用する被覆用治具をつくるための半田
に濡れにくい耐半田性の材料としては、エポキシ−ガラ
スファイバー、ベークライト等の耐熱性樹脂などを用い
ることができる。また、アルミニウム、ステンレス等の
比較的半田に濡れにくい金属を用いることや、金属の外
周面に誘電体ガラスペーストを塗布し、焼き付け処理し
て半田レジスト層を形成し、半田に濡れにくくすること
もできる。As the solder-resistant material which is hard to be wetted by the solder for forming the coating jig used in the method of the present invention, epoxy-glass fiber, heat-resistant resin such as Bakelite, or the like can be used. It is also possible to use a metal such as aluminum or stainless steel which is relatively hard to wet with solder, or to apply a dielectric glass paste on the outer peripheral surface of the metal and form a solder resist layer by baking to make it hard to get wet with solder. it can.
被覆用治具として用いる断面が略コ字型の構造体として
は、回路基板の縁辺部に取り付け取りはずし容易に嵌合
可能な断面が略コ字型のものであり、かつ、フロー(噴
流)半田槽に浸漬した際に半田のはじきを良くするため
に、第7図(ロ)および(ハ)などに示すように、半田
の噴流を側面方向に導く鍔部が設けてあるのが特徴であ
る。本発明の実施に好都合に使用できる被覆用治具の幾
つかの例を第7図(イ)〜(ロ)に示した。The structure having a substantially U-shaped cross section used as a covering jig has a substantially U-shaped cross section that can be easily attached to and detached from an edge portion of a circuit board and has a flow (jet) solder. In order to improve the repulsion of the solder when immersed in the bath, as shown in FIGS. 7B and 7C, it is characterized in that a flange portion for guiding the jet of the solder in the lateral direction is provided. . Some examples of coating jigs that can be conveniently used for carrying out the present invention are shown in FIGS. 7 (a) to 7 (b).
被覆用治具は回路基板の縁辺部に容易に取り付けること
ができ、しかも作業中安定に保持されているよう、弾性
材料でできていることが好ましい。この目的に好都合に
使用できる弾性体としては、回路基板の縁辺部に嵌合可
能な弾性を有する耐半田性のものであれば何でもよい
が、上に挙げた樹脂や金属を単独で使用できるほか、回
路基板と接触する部分にシリコーンゴムを配して基板と
の密着性を向上させることも可能であり好ましい。The covering jig is preferably made of an elastic material so that it can be easily attached to the edge of the circuit board and is stably held during the work. Any elastic body that can be conveniently used for this purpose may be used as long as it is solder-resistant and has elasticity that can be fitted to the edge portion of the circuit board. It is also possible and preferable to arrange a silicone rubber in a portion that comes into contact with the circuit board to improve the adhesion to the board.
[作用] 本発明に従って混成集積回路基板縁辺部に設けたリード
ランドに外部接続用リードを半田付けする場合は、基板
縁辺部のリードランドでない部分を、少なくとも外表面
が半田に濡れにくい耐半田性の材料でつくった前述のよ
うな鍔部を有する略コ字型横断面のの被覆用治具で覆っ
て半田付けを行なうので、従来はデッドラインとなって
いたこの被覆されている部分にも、搭載電子部品または
その半田付け部分が存在していても一向に差しつかえな
い。溶融半田との接触は起らず、半田の熱も被覆用治具
でさえぎられるので半田付け部分が再溶融して部品が脱
落するようなことは起らないからである。治具の少なく
とも外表面は半田に濡れにくい材料でつくられているの
で、半田の表面張力によって半田が治具の外表面からは
じかれ、鍔部があることによって、半田の液面はたとえ
ば第4a図に示すような形となり、半田の持つ熱は基板上
に搭載された電子部品に伝わりにくくなる。したがっ
て、たとえば第4b図に示すように、電子部品gの搭載可
能の範囲が極めて縁辺部に近い位置まで広がり、実装密
度を高めることができる。[Operation] When soldering the external connection lead to the lead land provided on the edge portion of the hybrid integrated circuit board according to the present invention, at least the outer surface of the edge portion of the board edge which is not the lead land is resistant to soldering. Since soldering is performed by covering with a jig for covering with a substantially U-shaped cross section having the above-mentioned brim section made of the above material, soldering is also performed on this covered part which was a dead line in the past. , Even if there is a mounted electronic component or its soldering part, it does not matter. This is because contact with the molten solder does not occur, and the heat of the solder is also blocked by the coating jig, so that the soldered portion does not remelt and the component does not drop off. At least the outer surface of the jig is made of a material that does not easily get wet with the solder, so the solder is repelled from the outer surface of the jig by the surface tension of the solder, and there is a collar, so that the liquid surface of the solder is As shown in the figure, the heat of the solder is less likely to be transferred to the electronic components mounted on the substrate. Therefore, for example, as shown in FIG. 4b, the mountable range of the electronic component g is expanded to a position extremely close to the edge portion, and the mounting density can be increased.
実施例 第6a図に示すようなアルミナ基板1の表面にスクリ
ーン印刷によりAg-Pdペーストを塗布し、150℃で10分間
乾燥した後850℃で10分間焼き付け処理して厚膜配線導
体2、部品ランド3、およびリードランド4を形成し、
さらに前記厚膜配線導体に接続するようにスクリーン印
刷によりRuO2系抵抗ペーストを塗布し、150℃で10分間
乾燥した後850℃で10分間焼き付け処理して厚膜抵抗体
5を形成した。Example An Ag-Pd paste was applied to the surface of an alumina substrate 1 as shown in FIG. 6a by screen printing, dried at 150 ° C. for 10 minutes, and then baked at 850 ° C. for 10 minutes to form a thick film wiring conductor 2 and components. The land 3 and the lead land 4 are formed,
Further, a RuO 2 series resistance paste was applied by screen printing so as to be connected to the thick film wiring conductor, dried at 150 ° C. for 10 minutes, and then baked at 850 ° C. for 10 minutes to form a thick film resistor 5.
こうして得られた厚膜回路基板の表面の部品ランド
3およびリードランド4以外の部分にスクリーン印刷に
より保護ガラスを印刷し、150℃で10分間乾燥した後530
℃で2分間焼き付け処理して保護ガラス層6を形成し
た。A protective glass is printed on the surface of the thick film circuit board thus obtained other than the component land 3 and the lead land 4 by screen printing and dried at 150 ° C. for 10 minutes, and then 530
The protective glass layer 6 was formed by baking at 2 ° C. for 2 minutes.
上記で得られた厚膜回路基板の前記部品ランド3上
に半田ペーストを印刷した後、モールド型半導体7、チ
ップコンデンサ8、トランジスタ9などのチップ状電子
部品を搭載し、リフロー半田付け炉で230℃で熱処理し
て前記部品ランド3に電子部品7,8,9などを半田付けし
た。After printing the solder paste on the component land 3 of the thick film circuit board obtained above, chip-shaped electronic components such as the mold type semiconductor 7, the chip capacitor 8 and the transistor 9 are mounted, and the reflow soldering furnace The electronic components 7, 8 and 9 were soldered to the component land 3 by heat treatment at ° C.
上記電子部品を実装した厚膜回路基板の前記それぞ
れの厚膜抵抗体5について、レーザートリミング装置に
より抵抗値の調整を行った。The resistance value of each of the thick film resistors 5 of the thick film circuit board on which the electronic component is mounted was adjusted by a laser trimming device.
上記で得られた混成集積回路基板上の複数のリード
ランド4にそれぞれ外部接続用リードのクリップ部を嵌
合させた。Clip portions of leads for external connection were fitted to the lead lands 4 on the hybrid integrated circuit board obtained above.
上記混成集積回路基板の外部接続用リードのクリッ
プ部が嵌合された縁辺部の前記リード嵌合部以外の部分
に、エポキシ−ガラスファイバーを鍔部を有する断面が
コ字型に加工してなる治具を嵌合させた状態で、前記回
路基板の縁辺部を235℃のフロー(噴流)半田槽内に浸
漬して回路基板のリードランドに外部接続用リードを半
田付けした。An epoxy-glass fiber is processed to have a U-shaped cross section having a collar portion at a portion other than the lead fitting portion of the edge portion where the clip portion of the lead for external connection of the hybrid integrated circuit board is fitted. With the jig fitted, the edge portion of the circuit board was immersed in a flow (jet) solder bath at 235 ° C. to solder the lead for external connection to the lead land of the circuit board.
上記混成集積回路基板の縁辺部より、前記治具を取
り外した。The jig was removed from the edge of the hybrid integrated circuit board.
上記の半田付けにおいては、被覆用治具を使用しなけれ
ば半田への浸漬時に電子部品が半田液面と接する筈の位
置にも電子部品が搭載されていたが、電子部品の半田付
け部分の再溶融による離脱などの不都合は全く起らず、
外部接続用リードのリードランドへの接続は極めて良好
に行なうことができた。In the above soldering, the electronic component was also mounted at a position where the electronic component should come into contact with the solder liquid surface when immersed in the solder unless a coating jig is used. Inconvenience such as separation due to remelting does not occur at all,
The connection of the lead for external connection to the lead land could be performed extremely well.
[発明の効果] 本発明によれば、混成集積回路基板の縁辺部に外部接続
用リードのクリップ部を嵌合させ、該縁辺部を半田槽に
浸漬して前記リードを回路基板のリードランドに半田付
けする際に、前記リード嵌合部の周辺に実装された電子
部品の半田付け部分の温度上昇が防がれるので、実装部
品を落下させることなく外部接続用リードを効率よく半
田付けすることが可能となる。[Effects of the Invention] According to the present invention, the clip portion of the lead for external connection is fitted to the edge portion of the hybrid integrated circuit board, and the edge portion is immersed in the solder bath so that the lead becomes a lead land of the circuit board. When soldering, since the temperature rise of the soldering part of the electronic component mounted around the lead fitting part is prevented, it is possible to efficiently solder the external connection lead without dropping the mounted component. Is possible.
また、従来はデッドスペースとなっていた部分に分子部
品が搭載されていても、その部品を保護するための被覆
用治具を取り付けることによって、リードランドへの外
部接続用リードの半田付けを流れ作業で支障なく行なう
ことができるので、作業効率を低下させることなく実装
密度を高めることができる。In addition, even if molecular parts are mounted in the parts that used to be dead spaces in the past, soldering the external connection leads to the lead lands can be performed by attaching a coating jig to protect the parts. Since the work can be performed without any trouble, the mounting density can be increased without lowering the work efficiency.
第1図および第2図は、本発明に従って、混成集積回路
基板縁辺部のリードランド以外の部分を被覆用治具で覆
って、前記縁辺部を半田中に浸漬して外部接続用リード
をリードランドに接続する場合の基板と半田との接触の
状態を示す概念図である。 第3図は回路基板の縁辺部に鍔つきの被覆用治具をつけ
て該縁辺部を半田中に浸漬した状態を立体的に示す斜視
図である。 第4a図は電子部品を搭載した回路基板の一方の縁辺部の
リードランド以外の部分を鍔つきの治具で覆って回路基
板を半田中に浸漬した状態を示す側面図である。 第4b図は第4a図の場合についての正面図である。 第5図は従来の方法に従って、回路基板の縁辺部を治具
で覆うことなく基板を半田中に浸漬した状態を示す正面
図である。 第6a図〜第6f図は、典型的な従来の混成集積回路装置の
製造方法を工程順に示したものである。 第7図は本発明の実施に好都合に使用できる被覆用治具
の数例についての斜視図である。 図中の記号は次のものをそれぞれ表わす。 a……半田、b……クリップリード c……回路基板、d……半田浸漬寸法 e……デッドスペース、f……被覆用治具 g……電子部品 h……デッドスペースの境界線 1……アルミナ基板、2……厚膜配線導体 3……部品ランド、4……リードランド 5……厚膜抵抗体、6……保護ガラス層 7……モールド型半導体、8……チップコンデンサ 9……トランジスタ 10……レーザートリミングによる切り溝 11……外部接続用リード、11a……クリップ部 11b……リード部、11c……タイバー部 12……半田1 and 2 show, according to the present invention, a portion of a hybrid integrated circuit board edge portion other than a lead land is covered with a coating jig, and the edge portion is dipped in solder to lead an external connection lead. It is a conceptual diagram which shows the contact state of the board | substrate and solder when connecting to a land. FIG. 3 is a three-dimensional perspective view showing a state in which a bridging jig is attached to the edge of the circuit board and the edge is immersed in solder. FIG. 4a is a side view showing a state in which one edge portion of the circuit board on which the electronic component is mounted, other than the lead lands, is covered with a jig having a collar and the circuit board is immersed in solder. FIG. 4b is a front view of the case of FIG. 4a. FIG. 5 is a front view showing a state in which the board is immersed in solder without covering the edge portion of the circuit board with a jig according to the conventional method. 6a to 6f show a typical conventional method for manufacturing a hybrid integrated circuit device in the order of steps. FIG. 7 is a perspective view of several examples of coating jigs that can be conveniently used for implementing the present invention. The symbols in the figure represent the following respectively. a ... Solder, b ... Clip lead c ... Circuit board, d ... Solder immersion dimension e ... Dead space, f ... Coating jig g ... Electronic parts h ... Boundary of dead space 1 ... ... Alumina substrate, 2 ... Thick film wiring conductor 3 ... Part land, 4 ... Lead land 5 ... Thick film resistor, 6 ... Protective glass layer 7 ... Mold type semiconductor, 8 ... Chip capacitor 9 ... … Transistor 10 …… Cutting groove by laser trimming 11 …… External connection lead, 11a …… Clip part 11b …… Lead part, 11c …… Tie bar part 12 …… Solder
Claims (2)
されているリードランドに、外部接続用のリードのクリ
ップ部を嵌合させた後、該クリップ嵌合部が充分に半田
中に没する位置まで回転基板を半田中に浸漬して前記リ
ードを回路基板に半田付けする工程を含む混成集積回路
装置の製造方法において、半田付け作業時に回路基板の
少なくとも前記クリップ嵌合部の隣接水平方向延長部分
を、外周面が半田に濡れにくい耐半田性の材料で構成さ
れ、前記外周面に前記回路基板の主面方向に対し垂直方
向に突出した鍔部を有し、かつ横断面が略コ字型の被覆
用治具で覆って回路基板を半田面に垂直に半田槽内に浸
漬することによりリードランドに外部接続用リードを半
田付けすることを特徴とする混成集積回路装置の製造方
法。1. After fitting a clip portion of a lead for external connection to a lead land formed on at least one edge portion of a circuit board, the clip fitting portion is sufficiently immersed in solder. In a method for manufacturing a hybrid integrated circuit device including a step of immersing a rotating substrate in solder to a position and soldering the leads to a circuit board, at least a horizontal extension of the circuit board adjacent to the clip fitting portion in the circuit board during soldering work. The outer peripheral surface of the portion is made of a solder-resistant material that is hard to be wetted by solder, and the outer peripheral surface has a flange portion that projects in a direction perpendicular to the main surface direction of the circuit board, and has a substantially U-shaped cross section. A method for manufacturing a hybrid integrated circuit device, comprising: soldering an external connection lead to a lead land by covering the circuit board with a die coating jig and immersing the circuit board in a solder bath perpendicularly to the solder surface.
部分を被覆して回路基板を半田面に垂直に半田中に浸漬
するためのディップ半田付け用の被覆用治具であって、
少なくとも外周面が半田に濡れにくい耐半田性の材料で
構成され横断面が略コ字型であり、該外周面に前記回路
基板の主面方向に対し、垂直方向に突出した鍔部を有し
ていることを特徴とするディップ半田付け用の被覆用治
具。2. A dip soldering coating jig for coating an arbitrary edge portion of a circuit board during a soldering operation to immerse the circuit board in the solder perpendicularly to the solder surface,
At least the outer peripheral surface is made of a solder-resistant material that is hard to be wetted by solder, and has a substantially U-shaped cross section, and the outer peripheral surface has a collar portion protruding in a direction perpendicular to the main surface direction of the circuit board. A coating jig for dip soldering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63239959A JPH0756911B2 (en) | 1988-09-26 | 1988-09-26 | Method for manufacturing hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63239959A JPH0756911B2 (en) | 1988-09-26 | 1988-09-26 | Method for manufacturing hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0287594A JPH0287594A (en) | 1990-03-28 |
| JPH0756911B2 true JPH0756911B2 (en) | 1995-06-14 |
Family
ID=17052377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63239959A Expired - Lifetime JPH0756911B2 (en) | 1988-09-26 | 1988-09-26 | Method for manufacturing hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0756911B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2857490B2 (en) * | 1990-11-21 | 1999-02-17 | 株式会社日立製作所 | Map system with learning function |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0225276Y2 (en) * | 1984-11-20 | 1990-07-11 |
-
1988
- 1988-09-26 JP JP63239959A patent/JPH0756911B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0287594A (en) | 1990-03-28 |
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