JPH0758321B2 - Counting circuit test method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counting circuit, and more particularly to a method of testing a counting circuit in which a carry signal generation period from the most significant bit is shortened. It is a thing.

2. Description of the Related Art An integrated circuit that incorporates a microcomputer that performs a predetermined logical operation based on a fixed time interval (reference clock) and a communication control circuit that generates a transmission / reception clock from a reference input signal counts the reference clock and reference input signal It is equipped with a counting circuit. Such an integrated circuit executes a predetermined logical operation based on the carry signal output from the built-in counting circuit.

In the integrated circuit, it is necessary to test at the time of manufacture whether or not the built-in counting circuit and the circuit that operates based on the carry signal output by the counting circuit operate normally. As shown in FIG. 3, the conventional n-bit counting circuit is composed of n counting stages Q _{1 to} Q _n connected in cascade.
Therefore, as is apparent from the operation timing chart of FIG. 3, the carry signal generation period of the 1-bit counting circuit is the period from the rising of the counting input signal to the next rising, that is, the counting input signal period (rising From the next fall)). Similarly, the carry signal generation period of the n-bit counting circuit is 2 ⁿ × count input signal period.

Problems to be Solved by the Invention As described above, the integrated circuit operates logically based on the carry signal output from the built-in counting circuit. On the other hand, the carry signal generation interval of the conventional n-bit counting circuit is relatively long as 2 ⁿ × count input signal period. Therefore, in order to test all the logical operations, there is a problem that the number of test patterns stored in the test device and the test time increase, and the test device cannot be effectively used.

Therefore, the present invention is to provide a test method of a counting circuit in which a carry signal generation period from the most significant bit is shortened.

Means for Solving the Problems In the test method according to the present invention, a plurality of counting small circuits each consisting of a bits are connected in cascade, and the output of each counting small circuit is input to the next counting small circuit as a carry signal. In the counting circuit configured as described above, the output of the preceding counting small circuit is provided to the first input between the output of each counting small circuit except the final stage and the input of the counting small circuit of the next stage. The second input receives the input of the counting subcircuit of the first stage, and selects the first input in the first state and the second input in the second state to select the next stage. To a counting circuit each provided with a selection circuit for transmitting to the input of the counting small circuit, a count pulse signal is applied to the input of the count signal of the first stage in a state where each of the selection circuits is in the second state, each selection when applying the counting pulse signal 2 ^a th It is characterized in that the selection circuit is changed to the first state and then changed to the second state again to apply the ^2a + 1th counting pulse signals and thereafter.

Operation As described above, the counting circuit of the present invention is configured by further cascade-connecting a plurality of counting small circuits each including a plurality of cascade-connected counting stages. The counting circuit of the present invention comprises means for commonly connecting the count input signal to the input of the first stage of each of the counting subcircuits in response to the test signal.

Therefore, during the test, the counting input signal is commonly input to the first stage of each counting small circuit by the above means. In this way, since each counting small circuit operates in parallel, all the counting stages of each counting small circuit have a logical value of 1 during the time 2 ^a × count input signal period (where a is the number of bits of each counting small circuit). Will be taken. That is, the carry signal propagates through all the counting stages during the time 2 ^a × count input signal period.

At the time of non-test, the output of the final stage of the counting small circuit of the previous stage is connected to the input of the first stage of the counting small circuit of the next stage. That is, the circuit of the present invention operates as a counting circuit of a × b bits (b is the number of counting small circuits).

Thus, during the test, the carry period can be shortened to the time 2 ^a × count input signal period. On the other hand, in the case of the conventional counting circuit, the carry signal generation period of the most significant bit, that is, a × b bits is 2 ^{a × b} × count input signal period. The period can be shortened.

Embodiment An embodiment of the counting circuit of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing the configuration of one embodiment of the counting circuit of the present invention. The circuit shown comprises four cascaded counting stages Q _{01 to} Q ₀₄ . A counting input signal is connected to the input of the first counting stage Q ₀₁ . The output C ₀ of the uppermost or fourth counting stage Q ₀₄ is connected to one input of the first AND gate G ₁₁ . The counting input signal is the second
It is connected to one input of G ₁₂ of AND gate. AND
The outputs of gates G ₁₁ and G ₁₂ are connected to the inputs of OR gate G ₁₃ .

The circuit shown further comprises a test flip-flop 100. Set input S of test flip-flop 100
The test signal 1 to the reset input R and the test signal 2 to the reset input R
Are connected. The positive logic output terminal Q of the test flip-flop 100 is connected to the other input of the second AND gate G ₁₂ and the negative logic output terminal is connected to the other input of the first AND gate G ₁₁ .

The output of the above-mentioned OR gate G ₁₃ is a second cascade connected in four stages.
Are connected to the inputs of the first counting stage Q ₁₁ of the counting stage group Q _{11 to} Q ₁₄ (where Q ₁₄ is not shown). The output of the uppermost stage, ie, the fourth counting stage Q ₁₄ , is the above three logic gates.
It has the same configuration as the combinational logic circuit composed of G ₁₁ , G ₁₂ , and G _{13, and is connected} to a second combinational logic circuit composed of three logic gates G ₂₁ , G ₂₂ , and G ₂₃ (not shown). The output of the test flip-flop 100 is connected to the second combinational logic circuit in the same manner as the first combinational logic circuit.

The output of the second combinational logic circuit is further connected to a third counting stage group which is cascade-connected to the next four stages. Thereafter, the output of the third counting stage group is connected to the input of the third combinational logic circuit, and this is repeated until the nth counting stage group. That is, in the circuit shown in the drawing, (n + 1) sets of counting stage groups cascaded in four stages and n sets of combinational logic circuits each including three logic gates are alternately cascaded. The outputs of the test flip-flops 100 common to the respective sets are connected to the n sets of combinational logic circuits in the same manner.

The counting circuit of the present invention configured as described above operates as follows.

The test flip-flop 100 is set by the test signal 1 and reset by the test signal 2. When the test flip-flop 100 is set by the test signal 1, the positive logic output TQ and the negative logic output ▲ ▼ become 1 and 0, respectively. The output of the AND gates G ₁₁ , G ₂₁ , ..., G _{n1 having} the negative logic output ▲ ▼ (0 in this case) as one input is fixed to the logic value 0. Therefore, the AND gate that uses the output TQ (1 in this case) of the positive logic circuit as one input and the count input signal to the least significant bit as the other input
G _12, G _22, ..., the output of the G _n2 is, OR gate G _13, G _23, ..., in counting stage via the _{G n3 Q R1, Q R2,} Q R3, Q R4 (R = 1~n) It becomes the count input of each counting circuit of the next stage to be constructed. That is, when the test flip-flop 100 is set, the count input signal of the least significant bit is commonly connected to the input of each counting circuit.

The counting stage _{Q R1, Q R2, Q R3} , Q R4 state transition of (R = 0~n), shown in operation timing chart of FIG. 2. The output signal of the counting stage Q _R1 for receiving the count input signal is rising in response to the rising of the input signal, operation is repeated down up in response to the next rising. Therefore, the output signal period of Q _R1 is twice the count input signal period. That is, the operation of rising at time 1 and falling at the next time 2 is repeated thereafter.

Then, the output signal of the counting stage Q _R2 which receives the output of the counting stage Q _R1 is rising in response to a falling edge of the output signal of Q _R1, operation is repeated down up in response to the next falling .
Therefore, the output signal period of the Q _R2 is twice the output signal period of Q _R1, is four times the count input signal period. That is, the operation of rising at time 3 and falling at time 5 is repeated.

The same operation is repeated for the counting stages _QR3 and _QR4 which _receive the output of the preceding counting stage. For example, the output signal of the uppermost Q _R4 is rising at time 9, down standing at time 17. As a result of the above operation, at time 16, _QR1 , _QR2 , _QR3 ,
All output Q _R4 (R = 0~n) is a logic value 1.

Test flip-flop 10 with test signal 2 at time 16
Reset to 0. As a result, test flip-flop 1
The positive logic output TQ and negative logic output ▲ ▼ of 00 have logic values 0 and 1, respectively. The outputs of the AND gates G ₁₂ , G ₂₂ , ..., G _n2 whose positive logic output TQ (0 in this case) is one input are
It is fixed at logical 0. Therefore, negative logic output
AND gates G ₁₁ , G ₂₁ , ..., G having ▼ (1 in this case) as one input and carry signal C _m (m = 0 to n−1) from the preceding counting circuit as the other input The output of _n1 is the OR gate G ₁₃ , G
₂₃ , ..., G _n3 to be the count input of the count circuit of the next stage.
That is, at time 16, the operation of the carry signal propagating through all counting stages Q ₀₁ , Q ₀₂ , ..., Q _n3 , Q _n4 can be tested.

The test signal 1 causes the test flip-flop 100 described above.
If is set, the operation from time 1 to time 15 is repeated again.

As described above, according to the counting circuit of the present invention, the carry signal generation period can be shortened. As a result, it is possible to reduce the number of test patterns stored in the test device and the test time, so that the test device can be effectively used.

[Brief description of drawings]

1 is a circuit diagram showing a configuration of one embodiment of a counting circuit of the present invention, FIG. 2 is an operation timing diagram showing the operation of the circuit of FIG. 1 with time as a parameter, and FIG. The figure is a diagram showing a circuit diagram showing a configuration of a conventional counting circuit together with an operation timing diagram. (Main reference numbers) 100 …… Test flip-flops G ₁₁ , G ₂₁ ,…, G _n1 , G ₁₂ , G ₂₂ ,…, G _n2 …… AND gates G ₁₃ , G ₂₃ ,…, G _n3 …… OR gate _{Q 1 ~Q n, Q 01,} Q 02, ..., Q n3, Q n4 ...... counting stage

Claims (1)

[Claims] 1. A counting circuit configured to cascade-connect a plurality of counting small circuits each having a bits, and to input the output of each counting small circuit as a carry signal to the counting small circuit of the next stage. , Between the output of each counting small circuit except the last stage and the input of the counting small circuit of the next stage, the output of the preceding counting small circuit is input to the first input, and the output of the counting small circuit of the first stage is input to the second input. A selection circuit that receives the inputs of the respective circuits and selects the first input when in the first state and the second input when in the second state and transmits the selection to the input of the counting small circuit of the next stage. the relative count circuits respectively, by applying a counting pulse signal the input of the count signal of the first stage in a state where the respective selection circuits, each in the second state, applying a 2 ^a th counting pulse signal Changing each of the selection circuits to the first state, and Test method of counting circuit, characterized in that the second state is changed again applies a count pulse signal 2 ^a +1 -th since.