JPH0758599B2 - Semiconductor memory device having redundant cells - Google Patents

Description

The present invention relates to a semiconductor memory device having redundant cells.

[Conventional technology]

FIG. 5 is a partial circuit diagram of a conventional example of this type of semiconductor memory device. In this conventional example, a normal memory cell array 14 and
Redundant memory cell array 15 and X and Y decoders 12, 13
An AND gate 11 for directly driving the redundant memory cell array 15, program circuits 8a-8m provided corresponding to the input address signals Ao-Am, and a redundant memory drive circuit 9. The redundant memory drive circuit 9 is composed of a flip-flop 22, a polysilicon, a fuse F having a width of several μm, a resistor R and a capacitor C. The flip-flop 22 is a source-grounded NMOS transistor M15.
And a CMOS inverter composed of a PMOS transistor M16 and an NMOS transistor M17. The program circuits 8a to 8m also have substantially the same configuration as the redundant memory drive circuit 9.

Next, the circuit operation of this conventional example will be described.

When the presence of a defective memory cell in the normal memory cell array 14 is detected by the memory test system (not shown),
A fuse (not shown) in the program circuits 8a to 8m and a fuse F in the redundant memory drive circuit 9 are appropriately cut by a laser beam to fix their respective outputs to a high level. For example, in the redundant memory drive circuit 9, when the fuse F is cut off, the current supply from the power source Vcc through this fuse F is cut off, the electric charge accumulated in the capacitor C is discharged through the resistor R, and the contact N ₃ Becomes a low level, the output of the CMOS inverter is inverted, the node N ₄ becomes a high level, and the NMOS transistor M15 is turned on to stabilize the flip-flop. Program circuit 8a ~
When each output of 8 m and the redundant memory cell 9 becomes high level, the output of the AND gate 11 becomes high level, and the memory cell array for one row (one word line) of the redundant memory cell array 15 is selected. At the same time, AND Gate 11
Is input to the input decoder 12, and the X decoder electrically disconnects the word line to which the defective memory cell is connected.
As a result, all the memory cells connected to this word line are replaced with the memory cells in the redundant memory cell array 15.

[Problems to be solved by the invention]

In the conventional semiconductor memory device described above, since the program for redundant cell replacement can be performed only when the fuse can be completely cut by the laser beam, foreign matter such as dust is generated in the IC manufacturing process. When the fuse adheres to the fuse and the foreign substance acts as a kind of cover and the fuse cannot be completely cut even by irradiation with a laser beam, there is a drawback that the redundant cell replacement cannot be performed.

[Means for solving problems]

According to the present invention, in a semiconductor memory device, one end is connected to a connection point between a flip-flop and a fuse in a program circuit and a redundant memory drive circuit, and if the fuse is incompletely cut, it is supplied through the fuse, or It has a pull-down or pull-up circuit capable of flowing or supplying a current larger than the amount of flowing current, and a one-shot signal generation circuit for generating a one-shot signal for driving the pull-up or pull-down circuit.

[Work]

Therefore, even if the fuse is incompletely blown, the one-shot signal is generated to turn on the pull-down or pull-up circuit, so that the current that is supplied or flows out through the incompletely blown fuse is not affected. The flip-flop can be triggered, which allows the desired program output to be sent out and redundant cell replacement to be performed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of a semiconductor memory device of the present invention,
FIG. 2 and FIG. 3 are timing charts showing signal waveforms of various parts of this embodiment.

The semiconductor memory device according to the present embodiment has a source ground pull-down NMOS transistor for triggering the flip-flops 20 and 21 in the program circuits 8a to 8m and the redundant memory drive circuit 9 provided corresponding to the address signals Ao to Am. M ₆ and
M14 is added, and one shot signal generation circuit 16,17
The OR gate 6 and the delay circuit 1 are added, and the capacitors C and the resistors R are removed from the program circuits 8a to 8m and the redundant memory drive circuit 9. Note that FIG. 1 shows a specific circuit configuration of the address buffer 10 and the program circuits 8a to 8m, which are omitted in the description of the conventional example of FIG.

The drive clock signal generation circuit 16 uses the chip select signal CS
Is input by a signal delayed by a delay circuit 1 for a predetermined period and a one-shot signal is generated when the chip select signal CS changes from a high level to a low level. The three-stage inverters 2, 3, 4 and the NOR gate 5 It consists of The one-shot signal generation circuit 17 receives the chip select signal CS described above and generates a one-shot signal when the current Vcc is applied in the low level state of the chip select signal CS. ₁ , M
₂ and NMOS transistors M _{3 to} M ₅ whose transistor size is much larger than those of the PMOS transistors M ₁ and M ₂ . Any program circuit 8a~8m is the same configuration, the fuse F _0: and (F ₁ ~Fm not shown), a flip-flop 20, NMOS transistors M _10, M ₁₂ and the PMOS transistor M _SB, M ₁₃ Are combined with each other to form transfer gates 22 and 23 to which the address signal from the address buffer 10 is input. Further, the address buffer 10 receives the address signals A _{0 to} Am and outputs the complementary address signals a ₀ , a ₀ to am, am to the buffer gate 18 _0.
It consists of ~ 18m.

Next, the redundant cell replacement operation of this embodiment will be described.

When it is detected that the defective memory cell exists in the normal memory cell array 14, the address of the memory cell is input from the address buffer 10. Next, the fuses Fn, F ₀ to F of the redundant memory drive circuit 9 and the program circuits 8a to 8m
m is appropriately cut so that the output of each circuit becomes high level. In the program circuit 8a-8m, the inverted signal a _0-Am of the transfer gate 22 when the fuse is turned on address complementary signal is output, in-phase signal transfer gate 23 is turned on unless the fuse a ₀
~ Am is output. As a result, all the inputs of the AND gate 11 become high level, the output becomes high level, the word line of the redundant memory cell array 15 is selected, and the corresponding word line of the normal memory cell array 14 is electrically disconnected. . The redundant cell replacement is completed as described above. However, even if the fuse is not completely cut, the redundant circuit replacement is automatically achieved by the following circuit operation.

That is, when the semiconductor memory circuit is actually used and the chip select signal CS changes from high level to low level and becomes active, the contact N ₁ becomes low level at time t ₁ as shown in FIG. A one-shot signal that becomes high level for the delay time of the inverters ₂ to 4 is output from N ₂ . The one-shot signal is inputted to the gate of the pull-down NMOS transistor M _6, M ₁₄ of the program circuits 8a~8m and redundant memory drive circuit 9, momentarily to turn it on. In the circuit where the fuse is not blown, since sufficient current is supplied from the power supply Vcc through the fuse, the potential of the contact N ₀ is maintained at a high level even if the pull-down NMOS transistors M ₆ and M are turned on. If the fuse was not intended to be cut even though it was intended to be cut, the current supply is small, so contact N
_When the pull-down NMOS transistors M ₆ and M ₁₄ are turned on, ₁₃ becomes low level, the contact N ₄ becomes high level, the NMOS transistors M ₇ and M ₁₅ are turned on, and the flip-flop is stabilized. In this way, by inputting the one-shot signal, even if the fuse cut is incomplete,
The outputs of the flip-flops 20 and 21 are automatically inverted to the desired level to obtain the desired program output.

Similarly, as shown in FIG. 3, when the chip select signal CS is at a low level (that is, in the active state) and the power supply Vcc is turned on at time t ₂ , the PMOS transistor M _{2 of the} one-shot signal generation circuit 17 is turned on. Is turned on, current is supplied from the power supply Vcc, and the contact N ₂ becomes high level. afterwards,
When the large size NMOS transistors M ₃ and M ₅ are turned on with a delay, the contact N ₂ falls to a low level, and as a result, a one-shot signal is generated. Then, by the circuit operation described above, in the circuit having the incomplete disconnection fuse, the contact N ₃ changes to the low level and the contact N ₄ changes to the high level, and the flip-flops 20 to 21 become stable. In this way, the one-shot signal is always output at the initial stage of actual use of the IC, which causes the flip-flops to be inverted in the program circuits 8 to 8m and the redundant memory drive circuit 9 having incomplete cut fuses. A desired program output can be surely obtained, and redundant cell replacement can be surely performed.

FIG. 4 is a circuit diagram of the redundant memory drive circuit 9 in the embodiment of the present invention.

The difference between this embodiment and the above-described embodiments is that the fuse Fn is provided on the ground side and the PMOS transistors M ₂₁ and M ₂₂ are provided instead of the NMOS transistors M ₁₄ and M ₁₅ . P
The MOS transistor M ₂₁ is a pull-up transistor driven by a one-shot signal. The operation is similar to that of the above embodiment.

〔The invention's effect〕

As described above, according to the present invention, by providing the pull-down or pull-up circuit and the one-shot signal generation circuit, a desired program output can be obtained even when the fuse is not completely cut, and the redundant cell replacement is surely performed. There is an effect that can be performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a semiconductor memory device of the present invention,
2 and 3 are timing charts showing the signal waveforms of the respective parts of FIG. 1, FIG. 4 is a circuit diagram of the essential parts in another embodiment of the present invention, and FIG. 5 is a circuit diagram of a conventional example. . 1 ... Delay circuit, 2,3,4,7 ... Inverter, 5 ... NOR gate, 6 ... OR gate, 8a-8m ... Program circuit, 9 ... Redundant memory drive circuit, 10 ... Address buffer, 11 ...... AND gate, 12 …… X decoder, 13 …… Y decoder, 14 …… Normal memory cell array, 15 …… Redundant memory cell array, 16 …… One-shot signal generation circuit, 17 …… One-shot signal generation circuit, 18 _{0 to} 18m …… buffer gate, M _{1 to} M ₂₄ …… MOS transistor (M ₆ and M ₁₄ are pull-down NMOS
Transistor, M ₂₁ is a pull-up PNOS transistor) N _{1 to} N ₄ ... contacts, Vcc ... power supply, A _{0 to} Am ... address signal, a ₀ , a ₀ to am, am ... complementary address signal, F ₀ ~ Fn …… Fuse,

Claims (1)

[Claims] 1. A normal memory cell and a plurality of program circuits used to perform cell replacement to a redundant memory cell to be used in place of the normal memory cell when a defect occurs in the normal memory cell. These program circuits each have a flip-flop and a fuse whose one end is fixed to a constant potential and whose other end is connected to a part of the positive feedback loop of the flip-flop. In a semiconductor device having a redundant cell, in which the output of a flip-flop is fixed to a high level or a low level by uncutting for programming, one end is connected to a connection point between the flip-flop and the fuse, and the other end is grounded or A pull-down or pull-up circuit connected to the power supply voltage and a drive for driving the pull-down or pull-up circuit. The semiconductor memory device having a redundant cell; and a one-shot signal generating circuit that generates a shot signal.