JPH0758729B2 - Semiconductor test system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial field of application> The present invention relates to a semiconductor test device through each transmission line of a connecting device having a large number of transmission lines and having a plurality of contact points in each transmission line. The present invention relates to a semiconductor test system for individually performing a functional test and an electrical characteristic test of a semiconductor device by individually connecting a large number of test pins and a large number of pin terminals of a semiconductor device, respectively. The present invention relates to a technique for finding an open portion due to poor contact or disconnection in each transmission line prior to conducting an electrical characteristic test.

<Prior Art> FIG. 5 schematically shows a conventional semiconductor test system in which a semiconductor test device and a semiconductor device to be tested are connected via a physical and electrical connection device. is there.

The semiconductor test apparatus A ₀ includes a controller 2, a waveform generator 4,
A waveform detector 6, a DC measuring device 8 and a signal generating circuit 10 are provided. A plurality of waveform generators 4, waveform detectors 6 and direct current measuring devices 8 are provided respectively, and a signal generating circuit is provided.
Tens are equipped with hundreds.

The waveform generator 4, the waveform detector 6 and the signal generating circuit 10 are
This is for performing a functional test of the semiconductor device C. The waveform generator 4 generates various voltage and current waveforms as test data to generate a signal generation circuit 10 and a physical and electrical connection device B (for this, Output to each corresponding pin terminal 38a in the semiconductor device C via
Output data output from the respective pin terminals 38a of the semiconductor device C corresponding to the voltage / current waveforms and input via the connection device B and the signal generation circuit 10 are detected by the waveform detector 6. There is.

In this case, the control device 2 specifies the test data to be generated for each waveform generator 4 according to the test program of the built-in microcomputer, and the semiconductor device C of the semiconductor device C input from each waveform detector 6 is specified. A functional test of the semiconductor device C is performed by analyzing the output data.

The signal generating circuit 10 distributes and supplies the test data from each waveform generator 4 to a large number of pin terminals 38a in the semiconductor device C, and outputs the output data from the large number of pin terminals 38a to each waveform detector 6. Distribute.

The direct current measuring device 8 is for performing an electrical characteristic test of the semiconductor device C, and uses the direct current signal designated by the control device 2 as test data through the relay in the signal generating circuit 10 and the connection device B. The connection device B outputs to the corresponding pin terminal 38a in C and is output from the pin terminal 38a of the semiconductor device C in response to the DC signal.
The output data input via the relay of the signal generation circuit 10 is input and sent to the control device 2. The control device 2 analyzes the output data to perform an electrical characteristic test of the semiconductor device C.

When the functional test and the electrical characteristic test are executed, the semiconductor device C is set on the external device 40 such as a prober or a handler. A prober is used when the semiconductor device C is formed on a wafer, and a handler is used when the semiconductor device C is packaged.

The connection device B that physically and electrically connects the semiconductor test device A ₀ and the semiconductor device C is configured as follows (when using a prober).

The connection device B includes the first to third connection boards 30, 32, 34.
And a probe card 36.

A large number of lands 30a, 30b are formed on the upper and lower surfaces of the first connection board 30 by pattern wiring. On the upper and lower surfaces of the second connection board 32, a large number of pogo pins 32a, 32b are provided that can freely move in and out and are biased to project. A large number of lands 34a are provided on the upper surface of the third connection board 34, and a large number of pogo pins 34b are provided on the lower surface thereof. A large number of lands 36a are provided on the upper surface of the probe card 36, and a large number of probes 36b are provided on the lower surface thereof.

A plurality of test pins 10a, each made up of a plurality of pogo pins, are connected to the output lines of each of a large number of signal generation circuits 10 in the semiconductor test device A ₀ , and these test pins 10a are provided in the semiconductor test device A ₀ . The test pin 10a and the land 30a of the first connection board 30 form a first contact P1, and the land 30b of the first connection board 30 and the pogo pin 32a of the second connection board 32 form a second contact P2. And the pogo pin 32b of the second connection board 32 and the land 34a of the third connection board 34 form a third contact P3, and the pogo pin 34b of the third connection board 34 and the land 36a of the probe card 36 The fourth contact point P4 is formed, and the needle tip of the probe 36b of the probe card 36 and the pin terminal 38a of the semiconductor device C form the fifth contact point P5.

A transmission line having such first to fifth contacts P1 to P5 one by one has a large number of pin terminals 38a in the semiconductor device C.
There are as many as.

If at least one of the contact groups of these many transmission lines has a poor contact, or at least one of the connection boards 30, 32, 34 and the probe card 36 has a disconnection point, the semiconductor device C by the semiconductor test apparatus A ₀ It will interfere with the functional test and the electrical characteristic test of.

Therefore, before performing the test, test pins of the semiconductor test equipment A ₀
The connection confirmation inspection of the transmission line from 10a to the pin terminal 38a of the semiconductor device C is performed.

The method of this connection confirmation inspection will be described below with reference to FIG.

FIG. 6 shows an equivalent circuit of the transmission line D for one line in the connection device B for one pin terminal 38a.

The first to third connection boards 30, 32 and 34 and the probe card 36 are equivalent to the first to fourth line portions 30 respectively.
It is represented as l, 32l, 34l, 36l. DC measuring device 8
It is represented as a constant current source 8a and a voltmeter 8b.

The DC measuring device 8 is connected to the first contact P1 via a relay in the signal generating circuit 10, but the signal generating circuit 10 is omitted here.

Since this is a connection confirmation test, an aluminum solid wafer C ₀ is used instead of the semiconductor device C, and the probe 36b is brought into contact with it. A closed loop is formed by grounding the voltmeter 8b and the aluminum solid wafer C ₀ , respectively.

The closed loop inspection system E including the DC measuring device 8, the transmission line D and the aluminum solid wafer C ₀ is formed by the number of the pin terminals 38a.

The connection confirmation inspection is sequentially executed for each of the inspection systems E according to the inspection program in the control device 2.

That is, first, the constant current source 8a in the direct current measuring device 8 supplies a current to the inspection system E, and the detected voltage obtained by the voltmeter 8b is sent to the control device 2. If the detected voltage is zero, the control device 2 determines that the inspection system E does not have an open state (contact failure or disconnection), and proceeds to the inspection of the next inspection system E.

If the detected voltage is equal to or higher than a certain value or is infinite, it is determined that the inspection system E has an open state. In this case, a part in the open state is found and repaired, and when the repair is completed, the next inspection system E is inspected.

For all the inspection systems E, after it is confirmed that there is no open state, the functional test and the electrical characteristic test are executed.

<Problems to be Solved by the Invention> In the conventional semiconductor test system, the transmission line D
Since the connection confirmation inspection is performed as described above, when the open state (contact failure or disconnection) of the inspection system E is detected, the contact failure causes the first to fifth contact failures.
It is not possible to directly determine which of the contact points P1 to P5 of No. 1 and the disconnection of any one of the first to fourth line portions 30l, 32l, 34l, and 36l, so contact failure is not always made. Or there was the trouble of having to find the open part of the disconnection.

In recent years, the number of pin terminals 38a of the semiconductor device C has tended to increase, and some semiconductor devices have more than 500 pins. In such a connection confirmation inspection before the test of the semiconductor device, 500
Since the above transmission lines D exist and the number of the transmission lines D that cause poor contact or disconnection increases, there is a problem that a great deal of labor and time must be spent to find an open portion.

The present invention was devised to solve the above problems, and an object thereof is to obtain a semiconductor test system that can easily and accurately find an open portion in a short time in a connection confirmation inspection. .

<Means for Solving the Problem> A semiconductor test system according to the present invention is a semiconductor test apparatus, which includes a plurality of transmission lines and each of the transmission lines of a connection device having a plurality of contact points in each transmission line. A signal input to each transmission line in a semiconductor test system in which each of a large number of test pins in the semiconductor device and a plurality of pin terminals in a semiconductor device are individually connected to perform a functional test and an electrical characteristic test of the semiconductor device. Is provided with an open position detection device for identifying the open position of each transmission line based on the waveform state of each reflected signal reflected at the open position and returning through the same transmission line.

<Operation> The semiconductor test system according to the present invention utilizes that the degree of distortion of the waveform of the reflected signal changes in accordance with the distance from the incident end of the inspection input signal to the open portion,
The open location detecting device automatically identifies the open location based on the degree of distortion of the reflected signal.

<Embodiment> An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 schematically shows a semiconductor test system according to an embodiment of the present invention in which a semiconductor test device and a semiconductor device to be tested are connected via a physical and electrical connection device. is there.

The semiconductor test apparatus A ₁ of this embodiment, like the semiconductor test apparatus A ₀ of the conventional example, has a control device 2 for controlling the entire apparatus A _1.
A plurality of waveform generators 4, a waveform detector 6 and a large number of signal generating circuits 10 for controlling a function test of the semiconductor device C, and an electrical characteristic test and a connection confirmation test for the semiconductor device C. A plurality of direct current measuring devices 8 are provided, and as a new component, when an open state (contact failure or disconnection) occurs in the target transmission line D in the connection confirmation inspection, the open position is detected. An open position detection device 12 is provided.

The relationship between the waveform generator 4, the waveform detector 6, the DC measuring device 8, the control device 2 and the signal generating circuit 10 and the relationship between the signal generating circuit 10 and the connection device B are the same as those in the conventional example. The description is omitted. Since the specific structure of the connection device B is also similar to that of the conventional example, only the block is shown.

The open position detecting device 12 is bidirectionally connected to the control device 2, and the signal generating circuit 10 is connected to the connecting device B.
Is bidirectionally connected via a relay in.

In the connection confirmation inspection for all transmission lines D, when it is determined that the control device 2 has an open state (contact failure or disconnection) on the transmission line D based on the detection result from the open position detection device 12, control is performed. The device 2 connects the open position detecting device 12 to the open transmission line D via a relay in the signal generating circuit 10.

FIG. 2 is a block diagram of the open position detection device 12,
The connection state between the open position detecting device 12 and the transmission line D in the connection confirmation inspection is shown.

The transmission line D is connected to the connection device B in the same manner as described in FIG.
In the first to third connection boards 30, 32, 34 and the first to fourth line portions 30l equivalent to the probe card 36,
It consists of 32l, 34l and 36l.

Re-explaining P1 to P5 with reference to FIG. 5,
P1 is the first contact the test pin 10a of the semiconductor testing device A ₁ and the land 30a of the first connecting board 30 is formed, P2 is the first and second connecting board 30, 32 lands 30b and pogo pin 32a
The second contact point between (the first and second line portions 30l, 32
L3), P3 is a third contact point (between the second and third line portions 32l and 34l) formed by the pogo pin 32b and the land 34a of the second and third connection boards 32 and 34, and P4 is the third contact point. 3 connection boards 34
And a fourth contact point between the pogo pin 34b of the probe card 36 and the land 36a (between the third and fourth line portions 34l and 36l), P
Reference numeral 5 represents a fifth contact point formed by the needle tip of the probe 36b and the solid aluminum wafer C ₀ .

The open position detection device 12 includes a waveform generation register 14, a waveform generation variable voltage generation circuit (drive circuit) 16, a waveform detection register 18, and a waveform detection waveform voltage comparison circuit (comparator circuit) 20. .

The waveform generating register 14 receives the step-like input waveform signal S sent from the control device 2 as shown in FIG.
The input waveform data for generating _IN is stored. The variable voltage generation circuit 16 for waveform generation generates a corresponding input waveform signal S _IN based on the input waveform data from the waveform generation register 14 and outputs it to the transmission line D.

The input waveform signal S _IN output from the variable voltage generating circuit 16 for waveform generation propagates through the transmission line D, and the aluminum solid wafer C ₀
(There is no grounding) Or it returns with reflection from an open area where there is poor contact or a broken wire.

When the impedance of the variable voltage generating circuit 16 for waveform generation and the impedance of the transmission line D are set equal, the waveform of the reflected signal is at a level of 1/2 of the peak value as shown in FIG. It becomes a staircase waveform with a flat part.

The time width of the flat portion is proportional to the round trip of the signal, that is, twice the distance from the output terminal of the variable voltage generating circuit 16 for waveform generation to the reflection point.

Therefore, the data of the reflected waveforms in the normal state where the open state does not occur and the data of the reflected waveforms when the first to fifth contacts P1 to P5 are individually opened are made by an experiment in advance. These waveform data are measured and stored in advance in the waveform detection register 18 through the control device 2.

3 (b) shows a normal waveform signal S _NOM, and FIGS. 3 (c) to (g) respectively show the first to fifth contacts P1 to P5.
Open waveform signal S _{ABN1 to} S when P5 is open
_ABN5 is shown. The data of the normal waveform signal S _{NOM and} the data of the open waveform signals S _{ABN1 to} S _ABN5 are stored in the waveform detection register 18 in advance as reference data.

The waveform detection waveform voltage comparison circuit 20 compares the waveform of the reflected signal returned in the actual connection confirmation inspection with the waveform of the reference data stored in the waveform detection register 18,
If it matches the normal waveform signal S _NOM , a normal signal is sent to the control device 2, and if it matches any of the open waveform signals S _{ABN1 to} S _ABN5 , which one matches? The open position instruction signal shown is sent to the control device 2, and when it is different from any of the above, the abnormal signal and the waveform data of the reflected signal are sent to the control device 2.

Operation Next, the operation of the connection confirmation inspection by the semiconductor test system according to this embodiment will be described with reference to the flowchart of FIG.

In step S2, the DC measuring device 8 is controlled to inspect all the transmission lines D for the open state or the short state. In step S4, it is determined whether or not there is an open transmission line D, and if all the transmission lines D are in a normal state, the operation of the connection confirmation inspection is ended, and a functional test of the semiconductor device C is performed. Proceed to electrical characteristic test.

When it is determined in step S4 that the transmission line D in the open state exists, the process proceeds to step S6, the transmission line D in the open state is extracted, and the step
At S8, the open position detecting device 12 is connected to the open transmission line D via the relay in the signal generating circuit 10.

Next, in step S10, the open portion detection device 12 is driven to detect the open portion. That is, based on the waveform signal data from the waveform generating register 14, the variable waveform generating circuit 16 for waveform generation inputs the input waveform signal shown in FIG.
S _IN is generated, this is output to the transmission line D in the open state, and the reflected signal from the open portion is detected by the waveform detection waveform voltage comparison circuit 20.

In the next steps S12 to S20, the waveform data of the open waveform signals S _{ABN1 to} S _ABN5 stored in the waveform detection register 18 in the waveform detection waveform voltage comparison circuit 20 are sequentially compared with the waveform data of the detected waveform signal.

In step S12, the detected waveform data and the open waveform data (S _ABN1 ) at the first contact P1 are compared. If they match, the process proceeds to step S22 and the open point is the first contact P.
A message saying 1 is output, and if they do not match,
Go to step S14.

In step S14, the detected waveform data is compared with the open waveform data (S _ABN2 ) at the second contact P2, and if they match, the process proceeds to step S24 and the open point is the second contact P.
A message saying 2 is output, and if they do not match,
Go to step S16.

In step S16, the detected waveform data is compared with the open waveform data (S _ABN3 ) at the third contact P3. If they match, the process proceeds to step S26 and the open point is the third contact P.
A message saying that it is 3 is output, and if they do not match,
Go to step S18.

In step S18, the detected waveform data is compared with the open waveform data (S _ABN4 ) at the fourth contact P4, and if they match, the process proceeds to step S28 and the open point is the fourth contact P.
A message saying that it is 4 is output, and if they do not match,
Go to step S20.

In step S20, the detected waveform data is compared with the open waveform data (S _ABN5 ) at the fifth contact P5, and if they match, the process proceeds to step S30 and the open point is the fifth contact P.
A message saying that it is 5 is output, and if they do not match,
It proceeds to step S32.

Detected waveform data is open waveform data (S _{ABN1 to} S _ABN5 )
If it does not match any of the above, it is not the open state (contact failure) at the contacts P1 to P5, but the line parts 30l, 32l, 34l, 36
It means that it is an open state (disconnection) in l,
In this case, in step S32, the normal waveform signal S _NOM
The distance to the open portion is calculated from the difference between the flat portions of the waveform data and the detected waveform data, and the length to the open portion is output as a message in step S34.

Then, after steps S22 to S30 or step S34, the process proceeds to step S36 to enter the idling state. In this state, the worker repairs the open part based on the message output, and when the repair is completed, restarts.

If it is determined in step S38 that the restart has been instructed, the process returns to step S2 to determine whether or not the open portion has been repaired correctly. If the repair is correct, the transmission line D in the next open state is described above. After the same open location is specified, repair is performed, it is confirmed that the repair is correctly performed, and the same processing is repeated for the next transmission line D in the open state.

When all the transmission lines D are no longer in the open state, all the operations are completed, and the functional test and electrical characteristic test of the next process are performed.

As described above, even if the number of transmission lines D is very large and there are a plurality of or unspecified numbers of places in each transmission line D, the open places can be easily identified in a short time. I can inform you.

<Effects of the Invention> As described above, according to the present invention, it is utilized that the degree of distortion of the waveform of the reflected signal from the open portion changes according to the distance from the incident end of the inspection input signal to the open portion. Since an open position detection device that automatically specifies an open position based on the degree of distortion of the reflected signal is provided, each of the many test pins in the semiconductor test device and each of the many pin terminals in the semiconductor device are Even if there are a large number of individually connected transmission lines, it is possible to easily and accurately identify an open portion in a short time in the connection confirmation inspection of them.

[Brief description of drawings]

1 to 4 relate to an embodiment of the present invention.
FIG. 2 is a schematic configuration diagram of a semiconductor test system in which a semiconductor test device and a semiconductor device are connected via a connection device,
The figure is a circuit diagram showing the open position detection device and the transmission line,
FIG. 3 is a waveform diagram for explaining the operation, and FIG. 4 is a flowchart for explaining the operation. FIG. 5 is a schematic configuration diagram of a semiconductor test system according to a conventional example, and FIG. 6 is an explanatory diagram of a connection confirmation inspection in the conventional example. A ₁ is a semiconductor test device, B is a connection device, C is a semiconductor device,
D is a transmission line, 2 is a control device, 4 is a waveform generator, 6 is a waveform detector, 8 is a direct current measuring device, 10 is a signal generating circuit, 10a is a test pin in a semiconductor testing device, 12 is an open position detecting device, 14 is a waveform generation register, 16 is a variable voltage generation circuit for waveform generation, 18 is a waveform detection register, 20 is a waveform voltage comparison circuit for waveform detection, 30l to 36l are line portions, P1 to P5 are contacts,
36b is a probe and 38a is a pin terminal in a semiconductor device. In the drawings, the same reference numerals indicate the same or corresponding parts.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/04 H04L 1/14 9371-5K

Claims (1)

[Claims] 1. A plurality of test pins in a semiconductor test device and a large number of semiconductor devices in a semiconductor test device are connected through each of the transmission lines of a connecting device having a plurality of transmission lines and having a plurality of contact points in each transmission line. In a semiconductor test system in which each of the pin terminals is individually connected to perform a functional test and electrical characteristic test of a semiconductor device, the signal input to each transmission line is reflected at an open point and returned to the same transmission line. A semiconductor test system comprising an open portion detection device for identifying an open portion of each transmission line based on the waveform state of each reflected signal.