JPH0758738B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor device, the present invention relates to an input protection circuit in Japanese.

[0002]

2. Description of the Related Art Since the destruction phenomenon of MOSIC due to excessive surges such as static electricity has been a problem from the beginning of its development,
So far, various measures have been proposed and improvements have been made.

As shown in FIG. 1, a typical destruction protection circuit at an input / output terminal of a conventional complementary insulated gate semiconductor integrated device (hereinafter abbreviated as C-MOSIC) is a bonding circuit.
Pas Tsu sheet 1 Entered signal, protection resistance 2, after giving a potential to the clamp protection diode 3 has become the circuitry are transmitted to the input gate 4 C-MOSIC, the protecting resistor 2, FIG. 2 ( As shown in a), it is provided in the N-type semiconductor 101. The semiconductor substrate 101 is formed of a conductivity type different from that of the semiconductor substrate 101, that is, a P-type diffusion layer 102, or
As shown in (b), an insulating oxide film (hereinafter referred to as a field oxide film) 103 other than the gate oxide film is formed on the surface of the semiconductor substrate 101, and then the field oxide film 10 is formed.
The protection resistor 2 is obtained by providing the polycrystalline silicon layer 105 on the surface of No. 3.

[0004]

However, when the integration density of MOSIC is further increased as in the present situation, it is possible to use the conventional measures as they are for the MOSIC as described above, because electrostatic breakdown of the field oxide film of the MOS field effect transistor,
Turn-on phenomenon of the parasitic thyristor that is inevitably present in the MOSIC (hereinafter referred to as the latch-up phenomenon)
Will result in.

[0005] In other words, as although breakdown voltage such as static electricity has been enhanced by such a structure, it was also described in the above, especially
When the MOSIC is highly integrated, the formation of the protection resistor 2 by the P-type diffusion layer 102 has a drawback that the latch-up phenomenon peculiar to the C-MOSIC is easily caused. By the way, this latch-up phenomenon occurs in a conventional semiconductor device, for example, in a structure in which a high-concentration diffusion layer is provided in a semiconductor substrate as shown in the specification of Japanese Patent Publication No. 55-29139, the potential gradient of the semiconductor substrate. And MOS
By changing the layout on the mask of the field effect transistor, the parasitic thyristor characteristics are degraded,
It is possible to make it difficult to generate, but high integration MOS
In the IC, instead of the P + diffusion layer 102,
It is desirable to adopt the polycrystalline silicon layer 105 as the protection resistance. However, if a protective resistor having a high resistance value due to the polycrystalline silicon layer, that is, having a large value of the polycrystalline silicon length L / the polycrystalline silicon width W is provided, the bonding pad 1
Overvoltage due to static electricity or the like has Tsu pressurized sum is, the time required to be neutralized through the protection resistor 2 becomes longer, has a problem that leads to destruction of the field oxide film 103.
That is, the protective resistance is the static resistance applied to the bonding pad 1.
Excessive surge voltage due to electricity etc. gradually increases MOS field effect
On the side of the internal circuit that has a transistor and a destruction prevention element
By releasing it, the MOS type field effect transistor is broken.
It has a role to prevent destruction. Focus only on this point
Therefore, the higher the resistance value of the protection resistor, the better the protection performance.
Yes. However, if the resistance value of the protective resistor is high,
However, excessive surge voltage is applied near the bonding pad.
Continuing on, the field insulating film of the semiconductor device
It becomes easy to cause the breakdown of the insulating film.

Therefore, the present invention solves such a problem, and an object thereof is to provide a length L and a length of a polycrystalline silicon layer of a resistor connecting an input / output terminal of a semiconductor device and a destruction prevention element. The ratio of the width W is improved. Immediately <br/> Chi, and Bon loading pads breakdown preventing element is for signal input and output terminals are electrically connected with the protective resistor having a polysilicon layer, a signal of polycrystalline silicon layer The ratio L / W of the length L in the propagation direction and the width W orthogonal to each other is set to 5 or less to improve the withstand voltage against static electricity and destruction of the semiconductor device due to high voltage higher than the rated value. Further, the present invention provides a semiconductor device capable of high integration by effectively utilizing the circuit space.

[0007]

The semiconductor device of the present invention comprises :
Input terminals provided on the semi-conductor substrate above, the ratio of the electrical signal propagation direction length orthogonal to the width, resistors having a polycrystalline silicon layer is 5 or less, the electrical and the resistor and the input terminal And a second conductive wiring for electrically connecting the resistor and the destruction prevention element, and a potential supply section on the semiconductor substrate adjacent to the destruction prevention element. Is characterized by.

[0008]

EXAMPLE An example of the present invention will be described with reference to FIG.

According to the present invention, as shown in FIG.
The bonding pad 1 is provided on 01, and this is used as an input terminal. Aluminum wiring 104 allows polycrystalline silicon 105
And are connected adjacent to each other. This polycrystalline silicon 105 serves as a resistor of this input protection circuit. The ratio L / W of the length L to the width W of the polycrystalline silicon 105 is set to 5 or less, and the width of the polycrystalline silicon 105 is made smaller than the width of the input terminal 1. This avoids the latch-up phenomenon and eliminates the defect that the field oxide film is destroyed by an excessive input voltage. In addition, the bonding pad 1 that serves as an input terminal
By making the width of the polycrystalline silicon 105 serving as a resistor smaller than the width, the amount of current input to the polycrystalline silicon can be controlled on the side of the bonding pad, which can contribute to protection of the insulating film from excessive voltage. Further, even if the bonding pad 1 becomes smaller, the width of the resistor becomes smaller accordingly, so that higher integration can be achieved. Further, the polycrystalline silicon 105 and the clamp protection diode 3 are connected so as to be adjacent to each other by aluminum wiring, and further connected to a terminal connected to the input gate of the MOSIC by aluminum wiring. At this time, an input gate is provided adjacent to the clamp protection diode 3. That is, the clamp protection diodes 3 and MOS bonding pad 1 serving as the input terminal is a breakdown preventing element and the polycrystalline silicon 105
By disposing the input gate of the IC so as to be adjacent to the input protection circuit, it is not necessary to make the aluminum wiring redundant and an extra wiring area is not required. Therefore,
Can effective use of circuit space, as a result, it is possible to highly integrated. A protection circuit using polycrystalline silicon such that L 1 / W = 5 or less as in this embodiment, and L / W as in the conventional case.
Compared with a large W, for example, when the L / W of polycrystalline silicon is 10, a voltage of 400 to 500 V is instantaneously applied between the input terminal and the semiconductor substrate, and the bonding pad 1 107 for connecting the aluminum wiring 104 for connection with the polycrystalline silicon 105
, The field oxide film was easily destroyed, whereas under the same condition with L / W = 5, the field oxide film was not destroyed at all, and the latch-up withstand capacity was L / W = 1.
It was at the same level as that of 0. It should be noted that many of the resistors of this embodiment are
The thickness of the crystalline silicon 105 is 4500Å ,
The resistance is 10Ω / □.

2 to 3, 106 is a field oxide film and 108 is a contact hole.

[0011]

As above mentioned base according to the present invention, the length along the electrical signal propagation direction of the polycrystalline silicon layer which acts as a resistor
The ratio of the width orthogonal to the electrical signal propagation direction to
By making it lower, it has a sufficient effect to prevent the breakdown of the field oxide film due to high voltage outside the rating and static electricity, which are encountered when thinning the field oxide film in promoting miniaturization. Further, even when elements are miniaturized due to high integration, it is not necessary to make the wiring redundant, so that circuit space can be effectively used, and high density and high reliability can be achieved. .

[Brief description of drawings]

FIG. 1 is a circuit diagram showing destruction protection at an input terminal of a conventional C-MOS IC.

FIG. 2 is a cross-sectional view for explaining the structure of a conventional protection resistor.

FIG. 3 is a pattern diagram showing a destruction protection mechanism according to the present invention.

[Explanation of symbols]

 101 semiconductor substrate 103 field oxide film 105 polycrystalline silicon

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 27/092 29/78 8832-4M H01L 27/04 P 8832-4MH

Claims (1)

[Claims] 1. A input terminal provided on a semi-conductor substrate above, the ratio of the electrical signal propagation direction length orthogonal to the width, less than 5
A resistor having a certain polycrystalline silicon layer, a first conductive wiring electrically connecting the input terminal and the resistor, and a second conductive wiring electrically connecting the resistor and the destruction prevention element. A semiconductor device having a potential supply section on the semiconductor substrate adjacent to the destruction prevention element.