JPH0758780B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a semiconductor device using a semiconductor made of a III-V group compound or a mixed crystal and having interfaces with different energy gaps, layers of semiconductors made of the same substance and having different surface crystal plane orientations are laminated. This simplifies the formation of the multi-layer structure semiconductor used for the semiconductor device and the manufacture of the semiconductor device.

[Industrial application field]

The present invention relates to a structure of a semiconductor device which uses a semiconductor made of a III-V group compound or a mixed crystal and has interfaces having different energy gaps.

A semiconductor device using a semiconductor made of a III-V group compound or a mixed crystal is prized for high-speed operation.

Recently, to further increase the speed, semiconductor devices such as a high electron mobility transistor (HEMT) and a hetero bipolar transistor (HEMT) or a hetero bipolar transistor (a heterojunction of III-V group semiconductors, or a superlattice structure in which heterojunctions are stacked every several lattices) HB
Research such as (T) has become popular.

The heterojunction is a junction of different kinds of semiconductors to form an interface having a different energy gap. The joining of the different kinds of semiconductors has a drawback that it complicates the manufacture of the semiconductor device, and it is desired to eliminate this point.

[Conventional technology]

 FIG. 4 is a schematic side sectional view of a conventional HEMT.

In the figure, 11 is a substrate of gallium arsenide (GaAs), 12 is a channel layer of undoped GaAs, 13 is an electron supply layer of n-type aluminum gallium arsenide (AlGaAs), 14 is a contact layer of n ⁺ -type GaAs, and 15 and 16 Are metal gate electrodes and source / drain electrodes, respectively.

In this HEMT, since the energy gap of the electron supply layer 13 is larger than that of the channel layer 12, the electron supply layer 13 of the channel layer 12 is
A two-dimensional electron gas (2DEG) layer serving as a channel is formed in the lower region of the gate electrode 15 at the interface with and, and a high-speed field effect transistor (FET) is formed.

Further, FIG. 5 is a schematic side sectional view of a conventional HBT.

In the figure, 21 is a GaAs substrate, 22 is an n-type GaAs collector layer, 23 is a p-type GaAs base layer, 24 is an n-type AlGaAs emitter layer, 25 is an n ⁺ -type GaAs contact layer, and 26 and 27. Reference numerals 28 and 28 denote a metal collector electrode, a base electrode, and an emitter electrode, respectively.

In this HBT, the energy gap of the emitter layer 24 is larger than that of the base layer 23, and the HBT becomes a high speed bipolar transistor.

In the production of the HEMT or HBT, the crystal growth of the semiconductor layer forming the multilayer structure on the substrate 11 or 12 is performed by, for example, the molecular beam formation growth (MBE) method, the processing is performed by wet etching or dry etching, and the electrode The formation is performed by a vapor deposition method.

[Problems to be solved by the invention]

However, in the above-mentioned crystal growth, there is a problem that composition control is difficult due to different materials between layers, and in processing, there is a problem that different etching solutions are used during wet etching.

As described above, the semiconductor device having the heterojunction or the conventional superlattice structure has a problem in manufacturing.

[Means for solving problems]

The problem is that the same material has different crystallographic orientations on the surface.
At least one or more heterojunctions formed by stacking two or more layers of a semiconductor made of a IV group compound or a mixed crystal, and forming an energy gap in the crystal plane orientation at the interface between the two or more layers. A semiconductor device characterized by including the semiconductor device, wherein the two layers forming the heterojunction are a channel layer and an electron supply layer forming a HEMT, or the two layers forming the heterojunction form an HBT. It is solved by a semiconductor device which is a base layer and an emitter layer constituting the semiconductor device, or a semiconductor device in which the two or more layers form at least one superlattice structure.

[Action]

In general, in the case of a semiconductor composed of a III-V group compound or a mixed crystal, the band gap is different even if the same substance has different crystal plane orientations on the surface.

The present invention utilizes this point, and by stacking layers having the same material but different surface crystal plane orientations, the stacking interface becomes a junction of semiconductors having different energy gaps,
It operates similarly to the operation of the heterojunction used in the semiconductor device.

The stacking can be performed by using a superlattice structure, and the layers can be formed into n-type or p-type by using atomic planar doping.

Moreover, since the semiconductor having the multilayer structure is composed of the same material, it is simple to form and simplifies the manufacturing of the semiconductor device.

〔Example〕

1 and 2 are schematic side sectional views of the first and second embodiments of the present invention, respectively, and FIG. 3 is an explanatory view of an example of a method of laminating layers having different crystal plane orientations on the surface. The same reference numerals denote the same objects throughout the drawings.

The first embodiment shown in FIG. 1 is a semiconductor device corresponding to the HEMT shown in FIG.

In FIG. 1, 31 is a GaAs substrate whose surface crystal plane orientation is (100), 32 is a non-doped GaAs channel layer whose surface crystal plane orientation is (100), and 33 is a surface crystal plane orientation ( 111) is an n-type GaAs electron supply layer, 34 is an n ⁺ -type GaAs contact layer, and 35 and 36 are metal gate electrodes and source / drain electrodes, respectively.

Substrate 31, channel layer 32, electron supply layer 33, contact layer 34
The electrodes 35 and 36 are the substrate 11 and the channel layer shown in FIG.
12, the electron supply layer 13, the contact layer 14, and the electrodes 15 and 16, respectively.

Since the electron supply layer 33 has a larger energy gap than the channel layer 32 having a surface crystal plane orientation of (111) and a surface crystal plane orientation of (100), a gap between the channel layer 32 and the electron supply layer 33 is formed. Has the same relationship between the channel layer 12 of GaAs and the electron supply layer 13 of AlGaAs, and this semiconductor device operates similarly to the HEMT shown in FIG.

By the way, the energy gap of GaAs whose surface crystal plane orientation is (100) is about 1.4 eV, and that of GaAs whose surface crystal plane orientation is (111) is about 1.9 eV.

The second embodiment shown in FIG. 2 is a semiconductor device corresponding to the HBT shown in FIG.

In FIG. 2, 41 is a GaAs substrate whose surface crystal plane orientation is (100), 42 is an n-type GaAs collector layer whose surface crystal plane orientation is (100), and 43 is a crystal plane orientation (100). ) Is a p-type GaAs base layer, 44 is an n-type GaAs emitter layer having a crystal plane orientation of (111), 45 is an n ⁺ -type GaAs contact layer, and 46, 47 and 48 are metal collector electrodes, respectively. A base electrode and an emitter electrode.

The substrate 41, the collector layer 42, the base layer 43, the emitter layer 44, the contact layer 45 and the electrodes 46, 47 and 48 are the substrate 21, collector layer 22, base layer 23, emitter layer 24 and contact layer 45 shown in FIG. And electrodes 46, 47 and 48, respectively.

Since the crystal plane orientations of the surfaces of the base layer 43 and the emitter layer 44 are (100) and (111), respectively, this semiconductor device operates similarly to the HBT shown in FIG.

Both the electron supply layer 33 and the emitter layer 44 in the above two embodiments are GaAs whose surface crystal plane orientation is (100).
N-type GaAs whose surface crystal plane orientation is (111)
It is a layer.

This stacking can be performed by using a superlattice structure forming technique, for example, as shown in FIG.

That is, one atomic layer 52 of gallium (Ga) and one atomic layer 53 of arsenic (As) are alternately deposited on the GaAs layer 51 whose surface crystal plane orientation is (100). This deposition can be performed, for example, by the MBE method. By the way, since the element on the crystal plane orientation (111) of GaAs is only one of Ga and As, the above alternate deposition causes the crystal orientation of the surface to be (911), ( 811), ..., (211), (111) and the crystal plane orientation of the rear surface after passing through the transient interface 54 is (111).
A GaAs layer 55 is stacked.

At this time, if the impurity such as silicon (Si) is doped by atomic planar doping in the atomic layer 53 of As only, the stacked GaAs layer 55 can be made n-type.
When the GaAs layer 55 to be laminated is of p-type, the above-mentioned doping may be limited to the Ga atomic layer 52.

Incidentally, the channel layer 32 in the first embodiment and the collector layer 42 and the base layer 43 in the second embodiment have the crystal plane orientation of the surface of (100) similarly to the substrates 31 and 41, and therefore, the usual method is used. Can be stacked. Further, since the contact layers 34 and 45 have arbitrary crystal plane orientations on the surfaces, they can be similarly laminated by a usual method.

The thus formed multi-layered semiconductor having interfaces with different energy gaps is composed of the same material, and thus is simple to form, and it is simple to manufacture a semiconductor device by simplifying processing such as etching. Turn into

Although the semiconductor of the embodiment is GaAs, if it is a compound of III-V group or a mixed crystal, it has the same properties, so that the structure of the present invention can be easily applied to other semiconductors. Can be analogized.

〔The invention's effect〕

As described above, according to the configuration of the present invention, in a semiconductor device including a semiconductor made of a III-V group compound or a mixed crystal and having an interface having a different energy gap, the interface can be formed by stacking the same substance. This has the effect of enabling the formation of a semiconductor having a multilayer structure and the simplification of semiconductor device manufacturing.

[Brief description of drawings]

FIG. 1 is a schematic side sectional view of a first embodiment of the present invention, FIG. 2 is a schematic side sectional view of a second embodiment of the present invention, and FIG. 3 is a method of laminating layers having different crystal plane orientations on the surface. An explanatory view of an example, FIG. 4 is a schematic side sectional view of a conventional HEMT, and FIG. 5 is a schematic side sectional view of a conventional HBT. In the figure, 11, 21, 31, and 41 are substrates, 12, 32 are channel layers, 13, 33 are electron supply layers, 22 and 42 are collector layers, 23 and 43 are base layers, 24 and 44 are emitter layers, 14 , 25, 34, and 45 are contact layers, 15, 16, 26 to 28, 35, 36, and 46 to 48 are electrodes, 51 is a GaAs layer whose surface crystal orientation is (100), and 52 is a monolayer of Ga. , 53 is a monolayer of As, 54 is a transient interface, and 55 is a GaAs layer whose surface crystal plane orientation is (111).

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/338 29/04 29/73 29/812

Claims (4)

[Claims] 1. The same substance but different crystallographic orientation of the surface III
At least one heterojunction formed by stacking two or more layers of a semiconductor made of a group-V compound or mixed crystal and forming a difference in the energy gap of the crystal plane orientation at the interface between the two or more layers A semiconductor device characterized by the above. 2. The two layers forming the heterojunction are HE
The semiconductor device according to claim 1, wherein the semiconductor device is a channel layer and an electron supply layer that form an MT. 3. The two layers forming the heterojunction are HB
The semiconductor device according to claim 1, wherein the semiconductor device comprises a base layer and an emitter layer that form T. 4. The semiconductor device according to claim 1, wherein the two or more layers form at least one superlattice structure.