JPH0758785B2 - Method for manufacturing vertical field effect transistor - Google Patents
Method for manufacturing vertical field effect transistorInfo
- Publication number
- JPH0758785B2 JPH0758785B2 JP61282721A JP28272186A JPH0758785B2 JP H0758785 B2 JPH0758785 B2 JP H0758785B2 JP 61282721 A JP61282721 A JP 61282721A JP 28272186 A JP28272186 A JP 28272186A JP H0758785 B2 JPH0758785 B2 JP H0758785B2
- Authority
- JP
- Japan
- Prior art keywords
- epitaxial layer
- type
- conductivity type
- region
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
- H10D62/156—Drain regions of DMOS transistors
- H10D62/157—Impurity concentrations or distributions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/662—Vertical DMOS [VDMOS] FETs having a drift region having a doping concentration that is higher between adjacent body regions relative to other parts of the drift region
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は縦型電界効果トランジスタの製造方法に関し、
特にイオン注入によらない縦型電界効果トランジスタの
製造方法に関する。The present invention relates to a method for manufacturing a vertical field effect transistor,
In particular, the present invention relates to a method for manufacturing a vertical field effect transistor that does not rely on ion implantation.
従来、縦型電界効果トランジスタの製造方法において
は、一導電型の半導体基板上にエピタキシャル層を成長
させ、次に、このエピタキシャル層の表面にイオンを注
入して表面の不純物濃度を上昇させる方法により、この
部分の抵抗を下げベース間のオン抵抗の低減をはかって
いた。Conventionally, in a method of manufacturing a vertical field effect transistor, an epitaxial layer is grown on a semiconductor substrate of one conductivity type, and then ions are implanted into the surface of the epitaxial layer to increase the impurity concentration on the surface. , The resistance of this part was lowered to reduce the on-resistance between the bases.
第３図（ａ），（ｂ）は従来のかかる一例を説明するた
めの工程順に示した縦型電界効果トランジスタの断面図
である。ここではＮ型基板を例にとり説明する。3 (a) and 3 (b) are cross-sectional views of a vertical field effect transistor shown in the order of steps for explaining such a conventional example. Here, an N-type substrate will be described as an example.
第３図（ａ）に示すように、まづN+型半導体基板21上に
N-型エピタキシャル層22を形成し、次に、Ｎ型層24を形
成する。次に、このＮ型層24の上に酸化シリコン等の酸
化膜25を被覆する。更に、N+型半導体基板21の表面から
イオン32を注入してＮ型イオン注入層24を形成する。こ
のイオン注入により、Ｎ型イオン注入層24の抵抗を小さ
くしてオン抵抗の低減を計っている。As shown in FIG. 3 (a), first, on the N + type semiconductor substrate 21,
The N − type epitaxial layer 22 is formed, and then the N type layer 24 is formed. Next, the N-type layer 24 is covered with an oxide film 25 such as silicon oxide. Further, ions 32 are implanted from the surface of the N + type semiconductor substrate 21 to form the N type ion implantation layer 24. By this ion implantation, the resistance of the N-type ion implantation layer 24 is reduced to reduce the on-resistance.
次に、第３図（ｂ）に示すように、Ｎ型イオン注入層24
をゲート酸化膜25で覆い、その上に多結晶シリコン層を
つくりゲート電極26とする。次に、このゲート電極26を
マスクにして、ベース電極用のＰ型領域27をつくり、そ
の上にN+型ソース領域28を形成する。更に、ソース領域
28とゲート電極26を絶縁するために層間絶縁膜29で覆
い、その上に電極30を被覆する。最後に、ドレイン電極
31をN+型半導体基板21に被着して縦型電界効果トランジ
スタが形成される。Next, as shown in FIG. 3B, the N-type ion implantation layer 24
Is covered with a gate oxide film 25, and a polycrystalline silicon layer is formed thereon to form a gate electrode 26. Next, using this gate electrode 26 as a mask, a P-type region 27 for the base electrode is formed, and an N + -type source region 28 is formed thereon. In addition, the source area
An interlayer insulating film 29 is covered to insulate the gate electrode 26 from the gate electrode 26, and the electrode 30 is covered thereon. Finally, the drain electrode
The vertical field effect transistor is formed by depositing 31 on the N + type semiconductor substrate 21.
なお、かかる従来の製造方法については、特開昭57−42
164などに紹介されているので、その詳細については省
略する。The conventional manufacturing method is described in JP-A-57-42
Since it is introduced in 164 etc., its details are omitted.
上述のＮ型領域を形成するにあたり、従来はイオン注入
法を用いているため、イオン打込後のゲート電極部分に
悪影響が残るほか、ゲート酸化膜などの質が悪化すると
いう問題があった。In forming the above-mentioned N-type region, the ion implantation method has been conventionally used, so that there is a problem that the gate electrode portion after the ion implantation remains adversely affected and the quality of the gate oxide film and the like deteriorates.
本発明の目的は、上述のベース間のオン抵抗を低減する
にあたり、ゲート電極やゲート酸化膜などに悪影響を与
えない縦型電界効果トランジスタの製造方法を提供する
ことにある。An object of the present invention is to provide a method for manufacturing a vertical field effect transistor that does not adversely affect the gate electrode, the gate oxide film and the like in reducing the on-resistance between the bases.
本発明の縦型電界効果トランジスタの製造方法は、一主
面上にソース電極とゲート電極を形成し、且つ一主面と
は反対側にドレイン電極を形成する縦型電界効果トラン
ジスタの製造方法において、前記基板上に一導電型の第
一のエピタキシャル層を成長させる工程と、前記エピタ
キシャル層の上にこのエピタキシャル層の濃度よりも高
い濃度を有する一導電型領域を形成する工程と、前記一
導電型領域の上に一導電型の第二のエピタキシャル層を
成長させる工程と、前記第二のエピタキシャル層の上に
酸化膜を介してゲート電極を形成する工程と、前記ゲー
ト電極をマスクにして逆導電型のベース領域を形成する
工程と、このベース領域の上から一導電型のソース領域
を形成する工程と、前記ゲート電極と前記ソース領域と
の上に層間絶縁膜を形成する工程と、前記ソース領域の
上にソース電極を被着する工程と、前記基板の一主面と
は反対側にドレイン電極を形成する工程とを含み、前記
一導電型領域を前記第一のエピタキシャル層と前記第二
のエピタキシャル層との間の埋込層として形成するよう
に構成される。A method of manufacturing a vertical field effect transistor according to the present invention is a method of manufacturing a vertical field effect transistor, wherein a source electrode and a gate electrode are formed on one main surface and a drain electrode is formed on a side opposite to one main surface. Growing a first conductivity type first epitaxial layer on the substrate, forming a first conductivity type region having a concentration higher than the concentration of the epitaxial layer on the epitaxial layer, A step of growing a second epitaxial layer of one conductivity type on the type region, a step of forming a gate electrode on the second epitaxial layer via an oxide film, and a step of reversely using the gate electrode as a mask. Forming a conductive type base region; forming a one conductive type source region from above the base region; and an interlayer insulating film on the gate electrode and the source region. A step of forming a source electrode on the source region, and a step of forming a drain electrode on the side opposite to the one main surface of the substrate; Is formed as a buried layer between the epitaxial layer and the second epitaxial layer.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ），（ｂ）は本発明の第一の実施例を説明す
るための工程順に示した縦型電界効果トランジスタの平
面図である。1 (a) and 1 (b) are plan views of a vertical field effect transistor shown in the order of steps for explaining the first embodiment of the present invention.
第１図（ａ）に示すように、N+型半導体基板の一主面上
にN-型の第一のエピタキシャル層２を成長させ、その上
にN+型領域３を選択的に形成する。次に、N+型領域３の
上からN-型の第二のエピタキシャル層４を形成し、この
第二のエピタキシャル層４と前記第一のエピタキシャル
層２との間で前記N+型領域が埋込み層となるようにす
る。As shown in FIG. 1A, an N − -type first epitaxial layer 2 is grown on one main surface of an N + -type semiconductor substrate, and an N + -type region 3 is selectively formed thereon. . Then, N + -type region N from the top of the 3 - a second epitaxial layer 4 of the mold form, said N + -type region between the second epitaxial layer 4 and the first epitaxial layer 2 To be a buried layer.
次に、第１図（ｂ）に示すように、第二のエピタキシャ
ル層４の上にゲート酸化膜５を介してゲート電極６を多
結晶シリコンにより形成し、ついでこのゲート電極６を
マスクにしてＰ型ベース領域７を、またそのＰ型ベース
領域７の上からN+型ソース領域８を拡散形成する。その
際、二つのＰ型ベース領域７の間に前記埋込み層となる
N+領域３が位置するようにする。更に、ゲート電極６と
なる多結晶シリコン層とN+型ソース領域８との上にCVD
法などにより層間絶縁膜９を形成したのち、N+型ソース
領域８にソース電極10を被着する。最後に、N+型半導体
基板１の一主面とは反対側の面にはドレイン電極11を被
着し、縦型電界効果トランジスタとして仕上げる。Next, as shown in FIG. 1 (b), a gate electrode 6 is formed of polycrystalline silicon on the second epitaxial layer 4 with a gate oxide film 5 interposed therebetween, and the gate electrode 6 is used as a mask. A P-type base region 7 and an N + -type source region 8 are formed by diffusion from above the P-type base region 7. At that time, the buried layer is formed between the two P-type base regions 7.
The N + region 3 is located. Further, CVD is performed on the polycrystalline silicon layer which will be the gate electrode 6 and the N + type source region 8.
After the interlayer insulating film 9 is formed by the method or the like, the source electrode 10 is deposited on the N + type source region 8. Finally, a drain electrode 11 is deposited on the surface opposite to the one main surface of the N + type semiconductor substrate 1 to complete the vertical field effect transistor.
かかる製造工程によって埋込み層を形成することによ
り、二つのＰ型ベース領域７間のオン抵抗を低くし、ゲ
ート電極となる多結晶シリコン層やゲート酸化膜の質を
保護することができる。By forming the buried layer by such a manufacturing process, it is possible to reduce the on-resistance between the two P-type base regions 7 and protect the quality of the polycrystalline silicon layer that will be the gate electrode and the gate oxide film.
第２図（ａ），（ｂ）は本発明の第二の実施例を説明す
るための工程順に示した縦型電界効果トランジスタの断
面図である。2A and 2B are cross-sectional views of a vertical field effect transistor shown in the order of steps for explaining the second embodiment of the present invention.
第２図（ａ），（ｂ）に示すように、前記第一の実施例
と異なる点はN-型第二のエピタキシャル層４をＮ型層
４′にした点である。かかる濃度の変更を行っても第一
の実施例同様の効果をはたすことができる。その他の点
については、第一の実施例と同様であるので詳細につい
ては省略する。As shown in FIGS. 2A and 2B, the point different from the first embodiment is that the N − -type second epitaxial layer 4 is an N-type layer 4 ′. Even if the concentration is changed, the same effect as in the first embodiment can be obtained. The other points are similar to those of the first embodiment, and thus the detailed description is omitted.
また、前記埋込み層は厚さ、面積等を変えることによ
り、濃度を自由に変更することができ、更に、エピタキ
シャル層を２重に成長させているため、一層目と二層目
の濃度を変更することにより、素子特性を改善すること
もできる。Moreover, the concentration of the buried layer can be freely changed by changing the thickness, area, etc. Further, since the epitaxial layer is grown double, the concentration of the first layer and the second layer can be changed. By doing so, the device characteristics can be improved.
上述の実施例についてはＮ型半導体基板を例にとり説明
したが、Ｐ型半導体基板に替えても同様に本発明を実施
することができる。Although the above embodiment has been described by taking the N-type semiconductor substrate as an example, the present invention can be implemented in the same manner even when the P-type semiconductor substrate is used.
〔発明の効果〕 以上説明したように本発明によれば、二つのエピタキシ
ャル層の間に半導体基板と同じ導電型の埋込み層を形成
することにより、二つのベース間のオン抵抗を低減し、
ゲート電極およびゲート酸化膜への悪影響を排除した縦
型電界効果トランジスタの製造方法を得られる効果があ
る。As described above, according to the present invention, by forming a buried layer of the same conductivity type as the semiconductor substrate between the two epitaxial layers, to reduce the on-resistance between the two bases,
There is an effect that a method for manufacturing a vertical field effect transistor can be obtained in which adverse effects on the gate electrode and the gate oxide film are eliminated.
第１図（ａ），（ｂ）は本発明の第一の実施例を説明す
るために工程順にしたトランジスタの断面図、第２図
（ａ），（ｂ）は本発明の第二の実施例を説明するため
の工程順に示したトランジスタの断面図、第３図
（ａ），（ｂ）は従来の一例を説明するための工程順に
示したトランジスタの断面図である。 １……N+型半導体基板、２……N-型第一のエピタキシャ
ル層、３……N+型埋込み層、4,4′……N-型,N型第二の
エピタキシャル層、５……ゲート酸化膜、６……多結晶
シリコン層（ゲート領域）、７……Ｐ型領域、８……N+
型ソース領域、９……層間絶縁膜、10……ソース電極
（アルミ層）、11……ドレイン電極。1 (a) and 1 (b) are cross-sectional views of a transistor taken in the order of steps for explaining the first embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are second embodiment of the present invention. 3A and 3B are cross-sectional views of the transistor shown in the order of steps for explaining the example, and FIGS. 3A and 3B are cross-sectional views of the transistor shown in the order of steps for explaining the conventional example. 1 ... N + type semiconductor substrate, 2 ... N - type first epitaxial layer, 3 ... N + type buried layer, 4,4 '... N - type, N type second epitaxial layer, 5 ... ... Gate oxide film, 6 ... Polycrystalline silicon layer (gate region), 7 ... P-type region, 8 ... N +
Type source region, 9 ... interlayer insulating film, 10 ... source electrode (aluminum layer), 11 ... drain electrode.
Claims (1)
極とゲート電極を形成し，且つ一主面とは反対側にドレ
イン電極を形成する縦型電界効果トランジスタの製造方
法において、一導電型の前記基板上に一導電型の第一の
エピタキシャル層を成長させる工程と、前記エピタキシ
ャル層の上にこのエピタキシャル層の濃度よりも高い濃
度を有する一導電型領域を形成する工程と、前記一導電
型領域の上に一導電型の第二のエピタキシャル層を成長
させる工程と、前記第二のエピタキシャル層の上に酸化
膜を介してゲート電極を形成する工程と、前記ゲート電
極をマスクにして逆導電型のベース領域を形成する工程
と、このベース領域の上から一導電型のソース領域を形
成する工程と、前記ゲート電極と前記ソース領域との上
に層間絶縁膜を形成する工程と、前記ソース領域の上に
ソース電極を被着する工程と、前記基板の一主面とは反
対側にドレイン電極を形成する工程とを含み、前記一導
電型領域を前記第一のエピタキシャル層と前記第二のエ
ピタキシャル層との間の埋込層として形成することを特
徴とする縦型電界効果トランジスタの製造方法。1. A method of manufacturing a vertical field effect transistor, wherein a source electrode and a gate electrode are formed on one main surface of a one-conductivity type semiconductor substrate, and a drain electrode is formed on the side opposite to the one main surface. Growing a first conductivity type first epitaxial layer on the conductivity type substrate; forming a first conductivity type region having a concentration higher than the concentration of the epitaxial layer on the epitaxial layer; Growing a second epitaxial layer of one conductivity type on the one conductivity type region, forming a gate electrode on the second epitaxial layer via an oxide film, and using the gate electrode as a mask. To form a base region of opposite conductivity type, forming a source region of one conductivity type from above the base region, and forming an interlayer insulating film on the gate electrode and the source region. The step of depositing a source electrode on the source region, and the step of forming a drain electrode on the side opposite to the one main surface of the substrate. A method for manufacturing a vertical field effect transistor, which is formed as an embedded layer between an epitaxial layer and the second epitaxial layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61282721A JPH0758785B2 (en) | 1986-11-26 | 1986-11-26 | Method for manufacturing vertical field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61282721A JPH0758785B2 (en) | 1986-11-26 | 1986-11-26 | Method for manufacturing vertical field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63133678A JPS63133678A (en) | 1988-06-06 |
| JPH0758785B2 true JPH0758785B2 (en) | 1995-06-21 |
Family
ID=17656178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61282721A Expired - Lifetime JPH0758785B2 (en) | 1986-11-26 | 1986-11-26 | Method for manufacturing vertical field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758785B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2771172B2 (en) * | 1988-04-01 | 1998-07-02 | 日本電気株式会社 | Vertical field-effect transistor |
| US5674766A (en) * | 1994-12-30 | 1997-10-07 | Siliconix Incorporated | Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer |
| US5688725A (en) * | 1994-12-30 | 1997-11-18 | Siliconix Incorporated | Method of making a trench mosfet with heavily doped delta layer to provide low on-resistance |
| WO1997011497A1 (en) * | 1995-09-20 | 1997-03-27 | Hitachi, Ltd. | Fabrication method of vertical field effect transistor |
| US5939752A (en) * | 1995-12-12 | 1999-08-17 | Siliconix Incorporated | Low voltage MOSFET with low on-resistance and high breakdown voltage |
| JP4806852B2 (en) * | 2001-03-12 | 2011-11-02 | 株式会社デンソー | Silicon carbide semiconductor device and manufacturing method thereof |
| US7936007B2 (en) | 2009-04-16 | 2011-05-03 | Fairchild Semiconductor Corporation | LDMOS with self aligned vertical LDD backside drain |
| US9722041B2 (en) | 2012-09-19 | 2017-08-01 | Vishay-Siliconix | Breakdown voltage blocking device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5742164A (en) * | 1980-08-27 | 1982-03-09 | Hitachi Ltd | Semiconductor device |
-
1986
- 1986-11-26 JP JP61282721A patent/JPH0758785B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63133678A (en) | 1988-06-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6410959B2 (en) | Method of fabricating semiconductor device | |
| US3909320A (en) | Method for forming MOS structure using double diffusion | |
| JPH04266047A (en) | Soi type semiconductor device and preparation thereof equivalent to production of a buried layer | |
| JPH03114233A (en) | Vertical type mos fet and its manufacture | |
| JPH06104446A (en) | Semiconductor device | |
| JP2525630B2 (en) | Method for manufacturing thin film transistor | |
| JPH0758785B2 (en) | Method for manufacturing vertical field effect transistor | |
| JPS6152591B2 (en) | ||
| JPH02159070A (en) | Semiconductor device and manufacture thereof | |
| JPS6333868A (en) | Manufacture of mis field-effect transistor | |
| JPH06302826A (en) | Insulated gate field effect transistor and manufacturing method thereof | |
| US6756279B2 (en) | Method for manufacturing a bipolar transistor in a CMOS integrated circuit | |
| JPH04294585A (en) | Manufacture of vertical type mos semiconductor device | |
| JP2004022555A (en) | Insulated gate field effect transistor and method of manufacturing the same | |
| JPH0794721A (en) | Semiconductor device and manufacturing method thereof | |
| JPS6238869B2 (en) | ||
| JP2512084B2 (en) | Method for manufacturing semiconductor device | |
| JP2707436B2 (en) | Method for manufacturing field effect transistor | |
| JPS6038883A (en) | Manufacture of schottky gate type field effect transistor | |
| JPS6331938B2 (en) | ||
| JPH03201485A (en) | Manufacture of vertical type double diffusion mos transistor | |
| JPS61187273A (en) | Semiconductor device | |
| JPH0370126A (en) | Polycrystalline silicon electrode and its manufacture | |
| JPH0478009B2 (en) | ||
| JPS63193567A (en) | Semiconductor device |