JPH0758825B2 - Wiring board - Google Patents
Wiring boardInfo
- Publication number
- JPH0758825B2 JPH0758825B2 JP60241311A JP24131185A JPH0758825B2 JP H0758825 B2 JPH0758825 B2 JP H0758825B2 JP 60241311 A JP60241311 A JP 60241311A JP 24131185 A JP24131185 A JP 24131185A JP H0758825 B2 JPH0758825 B2 JP H0758825B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring pattern
- wiring board
- wiring
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体装置の組立に用いられる金属ベースの
配線基板に関するもので、特に外装の施されていない半
導体チップ(ベア・チップ)の組立に用いられる。Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a metal-based wiring board used for assembling a semiconductor device, and particularly used for assembling a semiconductor chip (bare chip) having no outer packaging. To be
金属ベースの配線基板で第3図に断面を示す構成のもの
がある。同図において、101は板厚が例えば2mmのアルミ
ニウム板で、この一方の主面に層厚が0.16mmの樹脂の電
気絶縁層102を介して、0.035mm厚で所望のパターンにエ
ッチング形成された導電薄層103a、および、この導電薄
層に金または銀の電解めっきを施して積層形成された一
例の数ミクロン厚のめっき金属層103bで配線パターン層
103が形成される。このように形成された金属ベースの
配線基板100は正面図で第4図aに示される。同図にお
いて、配線パターン層103bは基板面の内側で方形に拡幅
したパッド部が対向し、同図bに示す回路図にみられる
ように、回路部品104,104…が接続されて所望の回路を
構成する。There is a metal-based wiring board having a structure whose cross section is shown in FIG. In the figure, 101 is an aluminum plate having a plate thickness of, for example, 2 mm, and a layer having a layer thickness of 0.16 mm is formed on the one main surface through an electrically insulating layer 102 of a resin, and is formed into a desired pattern with a thickness of 0.035 mm by etching. A wiring pattern layer including a conductive thin layer 103a, and an example of a plated metal layer 103b having a thickness of several microns, which is formed by laminating electrolytic plating of gold or silver on the conductive thin layer.
103 is formed. The metal-based wiring board 100 thus formed is shown in front view in FIG. 4a. In the figure, the wiring pattern layer 103b has pad portions that are widened in a square shape face each other inside the substrate surface, and as shown in the circuit diagram shown in FIG. To do.
上記基板の形成にあたって、めっき金属層を形成するた
めの電解めっきに、相互に電気的に分離されている配線
パターンを一体の電極として導通させる必要から第2図
aに示すように、予め一まわり大型の基板200を用意
し、図中破線で示す内側の上記配線基板100の分離して
いる複数配線パターンをこの基板の外域に引き出して共
通に接続する導通用パターン210とめっき用電極211を形
成する。そして、電解めっきが完了すれば破線部で導通
用パターンとともに切断する。When forming the above-mentioned substrate, since it is necessary to electrically connect mutually electrically separated wiring patterns as an integral electrode to the electrolytic plating for forming the plated metal layer, as shown in FIG. A large-sized board 200 is prepared, and a plurality of separated wiring patterns of the wiring board 100 on the inner side indicated by broken lines in the drawing are drawn to the outer area of this board to form a conduction pattern 210 and a plating electrode 211 for common connection. To do. Then, when the electrolytic plating is completed, it is cut along with the conduction pattern at the broken line portion.
叙上の如く配線パターン層の形成に電解めっきを用いる
配線基板ではめっき電流を流すため、複数導電薄層(銅
箔)のパターンを共通接続させるため、所望の配線基板
よりも一まわり大型の配線基板を用意し、所望の基体の
配線パターンを外方へ引き出して共通に接続している
が、電解めっきが完了すれば配線基板外域と導通用パタ
ーンに切断を施すが、この切断は一般にプレス加工で打
抜かれる。この切断により基体の端面(第2図aに示さ
れる破線部)に「だれ」を生じ、該部の電気絶縁層厚が
不均一になる。これにより絶縁破壊を発生するという重
大な問題があった。As described above, a wiring board that uses electroplating to form a wiring pattern layer allows a plating current to flow, so that the patterns of multiple conductive thin layers (copper foils) are commonly connected, making the wiring one size larger than the desired wiring board. The board is prepared, and the wiring pattern of the desired substrate is pulled out to the common connection, but when the electrolytic plating is completed, the outer area of the wiring board and the conduction pattern are cut, but this cutting is generally performed by pressing. Punched out with. This cutting causes "drip" on the end surface (broken line portion shown in FIG. 2a) of the substrate, and the thickness of the electrically insulating layer at that portion becomes uneven. This has caused a serious problem of causing dielectric breakdown.
この発明は上記従来の問題点に鑑み、配線基板端面にお
ける絶縁破壊を解消する改良構造を提供する。In view of the above conventional problems, the present invention provides an improved structure for eliminating dielectric breakdown at the end surface of a wiring board.
この発明にかかる配線基板(10)は、導電性基体(10
1)上に電気絶縁層(102)を介して形成された導電薄層
(103a)とこれに積層被着されためっき金属層(103b)
からなる配線パターン層(103)に、この両層(103a,10
3b)を厚さ方向に連続して貫通する孔(11)を基板端面
部の配線パターンと分離させ、基板端面における絶縁破
壊を防止するようにしたものである。また、次の発明は
上記孔内に露出した配線パターン層をフォトレジストの
如き電気絶縁被覆層(12)を設けたもので、さらに絶縁
破壊に大なる耐力が得られる。A wiring board ( 10 ) according to the present invention is a conductive substrate ( 10 ).
1) A conductive thin layer (103a) formed on top of an electrically insulating layer (102) and a plated metal layer (103b) laminated and deposited thereon.
The wiring pattern layer (103) consisting of both layers (103a, 10
A hole (11) continuously penetrating through 3b) in the thickness direction is separated from the wiring pattern on the end face of the substrate to prevent dielectric breakdown at the end face of the substrate. Further, in the next invention, the wiring pattern layer exposed in the hole is provided with an electric insulation coating layer (12) such as a photoresist, and a large proof stress against dielectric breakdown can be obtained.
以下、この発明を一実施例につき第1図および第2図を
参照して説明する。なお、説明において従来と変わらな
い部分については図面に従来と同じ符号を付けて示し説
明を省略する。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In the description, parts that are the same as those in the related art are denoted by the same reference numerals as those in the related art and will not be described.
第1図aは配線基板10の正面図を示し、図中11,11…は
配線パターン層103を切断するために設けた孔で、この
孔は第1図bに図aの破線で囲んで示す部分の配線パタ
ーンに沿う断面を示すように、切断予定部の配線パター
ンを完全に切断するように配線パターン幅よりも若干大
径のドリル、例えば幅が0.5mmの配線パターンに対し径1
mmのドリルで少くとも電気絶縁層102に達するまで削除
したものである。なお、この孔は皿孔でもよいが基体ま
で貫通する透孔である必要はない。FIG. 1a is a front view of the wiring board 10 , in which 11,11 ... Are holes provided for cutting the wiring pattern layer 103, and these holes are surrounded by the broken line in FIG. 1a in FIG. 1b. As shown in the cross section along the wiring pattern of the part shown, a drill slightly larger than the wiring pattern width so that the wiring pattern of the planned cutting portion is completely cut, for example, a diameter of 1 for a wiring pattern with a width of 0.5 mm.
It was removed with a mm drill until it reaches at least the electrically insulating layer 102. This hole may be a countersink, but it does not have to be a through hole that penetrates to the base.
次に、第1図cに第2の発明の孔部を示す。図に見られ
るように、11は第1の発明に開示された孔と同じである
が、この孔の内面に電気絶縁被膜層12を被着して孔内に
露出した配線パターン層103の端面と基体101の間の電気
絶縁性の向上がはかれるものである。上記電気絶縁被覆
層にはソルダレジストが適し、孔の内面からその周縁上
面にかけて被着し乾燥,硬化して形成される。Next, FIG. 1c shows the hole of the second invention. As shown in the figure, 11 is the same as the hole disclosed in the first invention, but the end surface of the wiring pattern layer 103 exposed in the hole by coating the inner surface of the hole with the electric insulation coating layer 12 The electrical insulation between the substrate 101 and the substrate 101 is improved. Solder resist is suitable for the electric insulation coating layer, which is formed by depositing from the inner surface of the hole to the upper surface of the peripheral edge thereof, drying and curing.
次の第2図aないし同図cはこの配線基板の形成を概略
の工程順に示す。同図aは破線で囲み示される配線基板
10が、その外方にめっき金属層形成のための導通用パタ
ーン210を備えた大型の基板200に設けられる。この段階
では配線パターン,導通用パターンともに銅箔にエッチ
ング形成された導電薄層103aであり、複数の配線パター
ンをすべて外方に導出し導通用パターン210に接続しめ
っき用電極211に接続されている。Next, FIGS. 2A to 2C show the formation of this wiring board in a rough order of steps. FIG. 3A shows a wiring board surrounded by a broken line.
10 is provided on a large-sized substrate 200 having a conductive pattern 210 for forming a plated metal layer on the outside thereof. At this stage, both the wiring pattern and the conductive pattern are the conductive thin layer 103a formed by etching on the copper foil, and all the plural wiring patterns are led out to be connected to the conductive pattern 210 and connected to the plating electrode 211. There is.
ついで、電解めっきを施し配線パターンに一例の金めっ
き層を被着し第2図bの如くなる。なおこの場合、導通
用パターン210は金めっきの必要がないからめっき用電
極は避けてソルダレジストを塗着しておいて電解めっき
を施すとよい。その後叙上によるドリル加工を施して孔
11,11…を設ける。Then, electroplating is performed and a gold plating layer as an example is applied to the wiring pattern, as shown in FIG. 2B. In this case, since the conductive pattern 210 does not need to be plated with gold, it is advisable to avoid the plating electrode and apply a solder resist before electrolytic plating. After that, drill a hole to make a hole.
Provide 11,11 ...
次にプレス抜き加工によって上記図bの破線部分を切断
し第2図cに示される配線基板10(第1図に示されるも
のに一致する)が得られる。Next, the broken line portion of FIG. 2B is cut by press punching to obtain the wiring board 10 shown in FIG. 2C (corresponding to that shown in FIG. 1).
この発明によれば、回路として不要な回路パターン部分
(配線基板の周縁部)がプレス切断の際の「だれ」によ
って絶縁耐力を低下させていたものを、ドリル加工によ
って一部で切断し対策するようにしたので、配線パター
ンと金属基体間の絶縁耐圧が飛躍的に向上し、汚染,異
物付着等による短絡も防止できる顕著な効果がある。こ
れはプレス加工による打抜きは配線パターンが基体に向
かう大きな力が印加され「だれ」を生ずるのであるが、
この発明はドリルで切削する方式であり、配線パターン
に対しこれを基体の方向に印加する力が至って軽微であ
るから電気絶縁層の厚さが完全に保たれるからである。According to the present invention, a circuit pattern portion (peripheral edge portion of the wiring board) unnecessary as a circuit, whose dielectric strength is lowered due to "drip" at the time of press cutting, is partially cut by drilling to take measures. As a result, the withstand voltage between the wiring pattern and the metal substrate is dramatically improved, and there is a remarkable effect that a short circuit due to contamination, adhesion of foreign matter, etc. can be prevented. This is because punching by press work causes a "dag" when a large force is applied to the wiring pattern toward the substrate.
This is because the present invention is a method of cutting with a drill, and since the force for applying this to the wiring pattern in the direction of the substrate is extremely small, the thickness of the electrical insulating layer can be completely maintained.
また、基体表面のソルダレジスト被覆も合わせて用いれ
ば絶縁耐圧はソルダレジストの被覆厚さが約0.3mmの場
合において5kV以上になる。さらに、この発明は主にド
リル加工で達成でき、これにソルダレジスト被覆を付加
しても実施がきわめて簡易である利点もある。さらにこ
の発明によれば、回路パターンを形成したのちに該パタ
ーンが、配線基板にその端部に施されるプレス切断によ
って基体との間に短絡を生じても、回路パターンとの短
絡を防止でき、かつその実施が極めて簡易な、たとえば
ドリル加工で達成できる顕著な利点がある。If the solder resist coating on the surface of the substrate is also used, the withstand voltage becomes 5 kV or more when the solder resist coating thickness is about 0.3 mm. Furthermore, the present invention has the advantage that it can be achieved mainly by drilling, and even if a solder resist coating is added thereto, it is extremely simple to carry out. Further, according to the present invention, even after a circuit pattern is formed and the pattern causes a short circuit between the circuit board and the substrate due to press cutting applied to the end of the circuit board, a short circuit with the circuit pattern can be prevented. Moreover, there is a remarkable advantage that its implementation is extremely simple and can be achieved by drilling, for example.
第1図aはこの発明の一実施例の配線基板の正面図、同
図bは第1の発明の要部を示す一部断面で示す斜視図、
同図cは第2の発明の要部を示す一部断面で示す斜視
図、第2図a〜cはこの発明の配線基板の形成を工程順
に示すいずれも基板の正面図、第3図は配線基板の断面
図、第4図aは従来の配線基板の正面図、同図bはこの
配線基板による回路図、第5図は配線基板端面の切断部
の断面図である。10 ,100……配線基板 11……孔 12……電気絶縁被覆層 101……金属基体 102……電気絶縁層 103……配線パターン層 103a……導電薄層 103b……めっき金属層FIG. 1a is a front view of a wiring board according to an embodiment of the present invention, and FIG. 1b is a perspective view showing a main section of the first invention in a partial cross section.
FIG. 3C is a perspective view with a partial cross-section showing an essential part of the second invention, and FIGS. 2A to 2C are front views of the substrate, all of which show the formation of the wiring substrate of the invention in the order of steps. 4A is a front view of a conventional wiring board, FIG. 4B is a circuit diagram of this wiring board, and FIG. 5 is a cross-sectional view of a cut portion of the end surface of the wiring board. 10 , 100 ...... Wiring board 11 …… Hole 12 …… Electrical insulation coating layer 101 …… Metal substrate 102 …… Electrical insulation layer 103 …… Wiring pattern layer 103a …… Conductive thin layer 103b …… Plating metal layer
Claims (2)
れた導電薄層とこの薄層に積層被着されためっき金属層
からなる配線パターン層と、前記配線パターン層の一部
においてその両層の厚さ方向に連続しかつその全幅方向
に貫通して配線パターン層を電気的に切断する孔とを備
えた配線基板。1. A wiring pattern layer comprising a conductive thin layer formed on a conductive substrate with an electrically insulating layer interposed therebetween, a plated metal layer laminated and deposited on the thin layer, and a part of the wiring pattern layer. A wiring board provided with a hole that is continuous in the thickness direction of both layers and penetrates in the entire width direction to electrically cut the wiring pattern layer.
れた導電薄層とこの薄層に積層被着されためっき金属層
からなる配線パターン層と、前記配線パターン層の一部
においてその両層を厚さ方向に連続しかつその全幅方向
に貫通して配線パターン層を電気的に切断する孔と、前
記孔内に露出した前記配線パターン層を被覆する電気絶
縁被覆層とを備えた配線基板。2. A wiring pattern layer comprising a conductive thin layer formed on a conductive substrate via an electrically insulating layer, a plated metal layer laminated on the thin layer, and a part of the wiring pattern layer. A hole for electrically cutting the wiring pattern layer that penetrates both layers in the thickness direction and penetrates the entire width direction, and an electrically insulating coating layer that covers the wiring pattern layer exposed in the hole are provided. Wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60241311A JPH0758825B2 (en) | 1985-10-30 | 1985-10-30 | Wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60241311A JPH0758825B2 (en) | 1985-10-30 | 1985-10-30 | Wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62102587A JPS62102587A (en) | 1987-05-13 |
| JPH0758825B2 true JPH0758825B2 (en) | 1995-06-21 |
Family
ID=17072400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60241311A Expired - Fee Related JPH0758825B2 (en) | 1985-10-30 | 1985-10-30 | Wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758825B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54160526A (en) * | 1978-06-09 | 1979-12-19 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of printing distributing board embedded with metal core having contact plug |
| JPS5749159A (en) * | 1980-09-08 | 1982-03-20 | Hitachi Maxell Ltd | Manufacture of battery |
| JPS5880897A (en) * | 1981-11-09 | 1983-05-16 | アンリツ株式会社 | Method of producing metal core printed circuit board |
-
1985
- 1985-10-30 JP JP60241311A patent/JPH0758825B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62102587A (en) | 1987-05-13 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |