JPH0758891B2 - Pulse width modulator - Google Patents

Description

The present invention relates to a pulse width modulator (hereinafter referred to as PWM) using two counters with reload registers.

[Conventional technology]

Fig. 4 is the page of the '86 Mitsubishi Semiconductor Data Book, 8-bit one-chip microcomputer, page 2-180, M50753-XXXSP / FP.
FIG. 12 is a diagram summarizing a configuration of a PWM using the two counter circuits with a reload register shown in FIG. 11. In this figure, 1 is a counter with a reload register that controls the time length of “PWM output = 0”, 2 is a counter with a reload register that controls the time length of “PWM output = 1”, 3 is a counter with a reload register 1, Count pulse (clock) propagated to the counter of 2; 4 is a signal indicating that the counter of the counter with reload register 1 has reached the terminal count value; 5 is the counter of the counter with reload register 2 has reached the terminal count value Is an output control unit (RS flip-flop) controlled by signals 4 and 5, and 7 is a PWM output.

Further, FIG. 5 shows an internal configuration example of the counters 1 and 2 with reload registers. In this figure, 8 is a counter,
9 is a reload register that holds the value (= reload setting value) written in the counter 8 when the terminal count value is reached, and 10 is a reload register 9 depending on the signal 4 or signal 5 indicating that the terminal count value has been reached. Is a circuit for controlling the operation of writing the value of 8 to the counter 8 (so-called reload operation), and 11 is a switch circuit for controlling whether or not the count pulse 3 is propagated to the counter 8.

Next, the operation will be described. In the following description,
The counter 8 of the counters 1 and 2 with reload registers is a down counter, and its terminal count value is "1".

In FIG. 6, 12 shows the countdown operation of the counter 8 in the counter 1 with the reload register, and 13 shows the countdown operation of the counter 8 in the counter 2 with the reload register. First, the counter 8 of the counter 1 with a reload register counts down sequentially from the counter initial value (initial value = 4 in this figure), and when the counter content becomes 1, a signal 4 indicating that the terminal count value has been reached at the timing a. To occur. As a result, the PWM output 7 changes from "0" to "1", and the counter 8 of the counter 2 with the reload register starts counting down from the counter initial value (initial value = 5 in this figure). The counter 8 of the counter 2 with the reload register sequentially counts down, and when the content of the counter becomes 1, a signal 5 indicating that the terminal count value has been reached is generated at a timing b. As a result, the PWM output 7 becomes "1" →
It changes to “0” and at the same time counters 1 and 2 with reload register
Each reload setting value is written from the reload register as the next counter initial value (n, m in this figure) to complete the PWM operation for one cycle. Note that n = 4
When m = 5, the output waveform of "0" output time length: "1" output time length = 4: 5 is continuously output.

Further, although the terminal count value is "1" in the above description, even when a counter having a terminal count value of "0" is used, the execution time length is "l +
The same PWM operation as in the above case is performed except that it becomes 1 ".

[Problems to be solved by the invention]

Since the conventional PWM is configured as above, ・ When the terminal count value = 1, even if the counter initial value is "0", 0 → [full scale]
→ Performs a wraparound operation called [Full Scale-1 ...

-When terminal value = 0 Even if the initial value of the counter is "0", the execution time length is "0 + 1".

In any case, PW corresponding to time length = 0
M operation, ie DC output (continuously output "0",
Alternatively, there is a problem that it is difficult to realize "outputting" 1 "continuously".

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a pulse width modulator capable of performing DC output when the initial value of the counter is set to "0".

[Means for solving problems]

A pulse width modulator according to the present invention includes a first counter with a reload register that determines a time length when a PWM output is at a first voltage level, and a second counter that determines a time length when a PWM output is at a second voltage level. PWM output in response to a counter with a reload register and a first terminal count value reaching signal output from the counter of the first reload register and indicating that the content of the counter has reached a predetermined terminal count value. Is switched from the first voltage level to the second voltage level, the second counter indicating that the counter content output from the counter of the second reload register has reached a predetermined terminal count value. In response to the terminal count value reaching signal of, the PWM output is switched from the second voltage level to the first voltage level, and one cycle And an output control circuit for completing the PWM operation, wherein the first and second counters with a reload register are respectively connected to the first or second counter immediately after the first or second terminal count value reaching signal is generated. Based on the terminal count value arrival signal of 2,
A pulse width modulator configured to write the reload set value of the reload register to the counter as a counter initial value, wherein each counter of the first and second counters with a reload register is 1
Or, whether the reload setting value written as the counter initial value is "0" between the generation of the second terminal count value reaching signal and the start of the counting operation in the PWM operation of the next cycle. The output control circuit is configured to determine whether
Receiving the determination signal output from each of the counters with the first and second reload registers, the reload setting value of the counters with the first and second reload registers is "0". What was determined to be, hold the operation in the stopped state in the PWM operation of the next cycle,
It is characterized in that, when the reload setting value is judged not to be "0", it is controlled so as to hold the operation in the activated state in the PWM operation of the next cycle.

[Action]

In the present invention, a counter with a first reload register that determines the length of time that the PWM output is at the first voltage level,
And a prediction that each counter of the second counter with a reload register that determines the length of time that the PWM output is at the second voltage level indicates whether the counter initial value in the PWM operation of the next cycle is "0". A signal is generated, and by this signal, in the PWM operation in the next cycle, the first and second signals are generated.
Of the counters with reload registers of the above, those with an initial value of "0" are held in the stopped state, and those with an initial value other than "0" are held in the activated state. PWM in which length = 0 can be realized and one cycle of PWM operation is fixed to the first or second voltage level
DC output can be obtained.

〔Example〕

FIG. 1 shows the structure of a PWM according to an embodiment of the present invention. In this figure, 15 is a counter with a reload register that controls the time length of "PWM output = 0", and 16 is "PWM output =
Counter with reload register to control 1 "time length, 3
Is a count pulse (clock) propagated to the counters with reload registers 15 and 16, 4 is a signal indicating that the counter of the counter with reload register 15 has reached the terminal count value, 17 is a counter of the counter with reload register 15 A signal indicating whether the initial value of the counter in the PWM operation in the next cycle of is 0 or not, 5 is a signal indicating that the counter of the counter 16 with a reload register has reached the terminal count value, 18 is a reload register A signal indicating whether the initial value of the counter in the PWM operation in the next cycle of the counter of the counter 16 is “0”, 19 is the signal 4,
Output controller for receiving 5,17,18 and controlling PWM output, 7 is PW
M output.

Further, FIG. 2 shows the internal configuration of the counters 15 and 16 with reload registers. In this figure, 20 is a counter (the difference from the counter 8 shown in FIG. 5 is that a signal 17 (18) indicating whether the next counter initial value is "0" is output). 9 is a reload register that holds the value written to the counter 20 when the terminal count value is reached, and 30 is the value of the reload register 9 (= reload setting value) due to the signal 4 (5) indicating that the terminal count value has been reached The circuit for controlling the operation of writing (to be referred to as preload hereinafter) into the counter 20 before the counting operation of the next PWM operation cycle starts (the difference from the circuit 10 shown in FIG. 5 is
11 is the count pulse 3), which is the difference in write timing.
Is a switch circuit for controlling whether or not to propagate to the counter 20.

The operation will be described below. The counter 20 of the counters 15 and 16 with reload registers is a down counter, and its terminal count value is "1". Further, in order to show an example of DC output, the counter initial value of the counter 20 of the reload register-equipped counter 15 = 2, the reload set value of the reload register 9 of the counter 15 with reload register = 0, the counter of the counter 16 with reload register
20 counter initial value = 3, counter with reload register 16
The reload setting value of the reload register 9 is set to 4.

In FIG. 3, reference numeral 21 is a signal indicating the countdown operation of the counter 15 with a reload register, and 22 is a signal indicating whether the next counter initial value of the counter 15 with a reload register is "0". Further, 23 is a signal indicating the countdown operation in the counter 16 with a reload register,
Reference numeral 24 is a signal indicating whether or not the next counter initial value of the counter 16 with a reload register is "0". First, the reload register counter 15 sequentially counts down from the counter initial value (= 2) of the counter 20. During this time,
The PWM output 7 is “0”. Counter 1 with reload register
When the counter 20 of 5 reaches the terminal count, the PWM
The output 7 changes from "0" to "1", and the counter 16 with a reload register starts counting down from the counter initial value (= 3) of the counter 20. The counter 20 of the counter 16 with the reload register sequentially counts down and generates the signal 5 indicating that the terminal count value has been reached at the timing c. As a result, the counter 20 is immediately preloaded with the next counter initial value and the reload set value of the reload register 9, and it is determined whether or not this is "0". By recognizing this result by the timing d (= the timing at which the counting operation of the next PWM operation cycle starts), it becomes possible to control the next PWM operation cycle to be the DC output.

That is, at the timing d shown in FIG. 3, (a) the signal 22 is significant → the next counter initial value of the counter 15 is “0”. (B) The signal 24 is not significant → the next counter initial value of the counter 16. Since it is known that is not “0”, the output control unit 19 (1) normally sets the PWM output 7 to “1” → “0” ”.
However, "Keep it at" 1 "" (2) If the switch 11 is operated, the "Counter"
The DC output (“1”) can be realized by performing the operation of “restarting the counter 16 while keeping the counter 15 stopped” instead of “stop 16 and start the counter 15”.

In the above embodiment, the example in which it is determined whether the next counter initial value is “0” by preloading the next reload set value from the reload register 9 to the counter 20 at the timing c has been described. A circuit for directly determining the reload set value of the reload register 9 is added to the reload register 9 between the timing c and the timing d, and signals 17, 1
A signal corresponding to 8 may be generated, and the same effect as in the above embodiment can be obtained.

〔The invention's effect〕

As described above, according to the pulse width modulator of the present invention, the first counter with a reload register for determining the time length of the PWM output being the first voltage level and the second PWM output are provided.
A second counter with a reload register that determines a time length that is a voltage level, and a first counter that indicates that the content of the counter output from the counter with the reload register has reached a predetermined terminal count value. When the PWM output is switched from the first voltage level to the second voltage level in response to the terminal count value reaching signal of 1, the content of the counter output from the counter of the second reload register counter is Upon receiving the second terminal count value reaching signal indicating that the predetermined terminal count value has been reached, the PWM output is switched from the second voltage level to the first voltage level, and the PW for one cycle is
And an output control circuit for completing the M operation, wherein the first, fifth and second counters with a reload register respectively immediately after the first or second terminal count value reaching signal is generated, A pulse width modulator configured to write the reload set value of the reload register to the counter as a counter initial value in response to a second terminal count value arrival signal.
And each counter of the second counter with the reload register, after the counter generates the first or second terminal count value reaching signal and before the counting operation in the PWM operation of the next cycle is started, It is assumed that the reload setting value written as the initial value is "0" and a determination signal is output, and the output control circuit is configured to operate the counters with the first and second reload registers. In response to the determination signals output from the respective counters, the one determined to have the reload setting value of the first and second counters with the reload register is "0" Hold the operation in the stop state in the PWM operation of, and hold the operation in the start state in the PWM operation of the next cycle when it is determined that the reload setting value is not "0" Since the control is performed as described above, the execution time length = 0 is realized, and there is an effect that a DC output can be output. It also has the effect of significantly reducing the load on the PWM control software.

[Brief description of drawings]

FIG. 1 is a block diagram showing a PWM using two counter circuits with a reload register according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of an internal configuration of a counter with a reload register according to the present invention. FIG. 4 is a timing chart showing an example of the PWM operation according to the present invention, FIG. 4 is a block diagram showing a PWM using two conventional counter circuits with reload registers, and FIG. 5 is an internal configuration of a conventional counter with reload registers. FIG. 6 is a timing chart showing an example of a conventional PWM operation. 4,5 are signals indicating that the terminal count value has been reached, 7 is PWM output, 15 and 16 are counter circuits with reload register, 17 and 18 are signals indicating that the next set value is "0", 19 Is the output control unit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first counter with a reload register for determining a time length for which a pulse width modulation (hereinafter, also referred to as PWM) output is a first voltage level, and a time length for which a PWM output is a second voltage level. Second to decide
And a first terminal count value reaching signal indicating that the content of the counter has reached a predetermined terminal count value output from the counter of the reload register and the counter of the first reload register. After the PWM output is switched from the first voltage level to the second voltage level, it indicates that the content of the counter output from the counter of the second reload register has reached a predetermined terminal count value. An output control circuit that receives the second terminal count value reaching signal and switches the PWM output from the second voltage level to the first voltage level to complete the PWM operation for one cycle; , And a second counter with a reload register, immediately after generation of the first or second terminal count value reaching signal, respectively. A pulse width modulator configured to write the reload set value of the reload register to the counter as a counter initial value based on the first or second terminal count value arrival signal. , And each counter of the second counter with a reload register, after the counter generates the first or second terminal kinetic value reaching signal, until the counting operation in the PWM operation of the next cycle is started, The output control circuit determines whether or not the reload setting value written as the counter initial value is “0” and outputs a determination signal. The output control circuit includes the first and second reload registers. Receiving the judgment signal output from each of the counters with a built-in counter, the reload setting of the first and second counters with a reload register Although the value is judged to be “0”, the operation is held in the stopped state in the PWM operation of the next cycle and the reload setting value is judged not to be “0”. A pulse width modulator which is controlled so as to hold the operation in the starting state in the PWM operation of the period.