JPH0758901B2 - Bus driver circuit - Google Patents

Description

The present invention relates to a bus driver circuit used when data is transferred between a plurality of functional blocks, and in particular, it is possible to prevent a large current from flowing when switching a bus source. The present invention relates to a possible bus driver circuit.

[Conventional technology]

Conventionally, this type of bus driver has been constructed by the tri-state circuit shown in FIG. In FIG. 3, 2 is a signal input terminal, 3 is a selection signal input terminal, 6 is a tri-state circuit, and 7 is a signal output terminal.

When the selection signal input terminal 3 is at "L" level, the tri-state circuit 6 is enabled and outputs the contents of the signal input terminal 2 to the signal output terminal 7. When used in a bus circuit, the bus driver shown in FIG. 3 is used for the output of the functional block, and the outputs of a plurality of functional blocks are commonly connected to form a bus.

To switch the bus source, the selection signal input of the required functional block is set to the "L" level and is enabled, and the selection signal inputs of the other functional blocks are set to the "H" level to be disabled.

FIG. 4 shows a time chart when the bus source is switched in the case of three functional blocks. When the function blocks are A, B, and C, the selection signal input of each function block is C _A , C _B , C _C , and the contents of the function block are D _A , D _B ,
Let's _call it D _C. In the figure, the shaded areas indicate that the respective functional blocks are enabled.

[Problems to be Solved by the Invention]

The conventional bus circuit described above has the drawbacks that a bus fight occurs at the time of switching the selection signal input to increase current consumption and, when integrated into an LSI, shortens the wiring life.

In FIG. 4, at the time indicated by an arrow, a through current flows between the bus drivers because the selection signal inputs are overlapped due to the difference in the number of logic stages of the selection signal inputs and the difference in load capacitance.

[Means for Solving the Problems]

In contrast to the conventional bus driver described above, the present invention uses the control input as a new input, and determines the output level of the tri-state circuit while the control input signal is at the "L" level.
AND circuit to enable the circuit and tristate circuit
And a circuit. As a result, all the output levels of the bus driver are fixed to the same logic level by the control input signal, and the through current between the bus drivers is eliminated.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. That is, the AND circuit 4 having the control input terminal 1 and the signal input terminal 2 as inputs, the AND circuit 5 having the control input terminal 1 and the selection signal input terminal 3 as the input, and the output of the AND circuit 4 as the signal input AN
A tri-state circuit 6 that receives the output of the D circuit 5 as a selection signal and a signal input terminal 7 that outputs the tri-state circuit 6
It is a circuit block diagram connected to.

When the control input terminal 1 is at "L" level, the outputs of the AND circuits 4 and 5 are at "L" level, and the output of the tristate circuit 6 is at "L". When the control input terminal 1 is at "H" level, the output level of the tri-state circuit 6 is determined by the logic levels of the signal input terminal 2 and the selection signal input terminal 3. When the selection signal input is at "H" level, the tri-state circuit 6 is disabled.

FIG. 5 shows a time chart when the bus source is switched in the case of three functional blocks. Signal name and symbol is 4th
This is the same as the conventional example in the figure. In FIG. 5, the content of the bus is "L" level while the control input signal is at "L" level, and the content of the functional block is output during the control input signal "H" level. In this way, the output of the tri-state circuit 6 is forcibly set to "L" level during the period until the selection signal input is stabilized by manipulating the control input signal when the selection signal input changes, and It is possible to prevent the through current.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

FIG. 2 is a diagram in which the AND circuit 4 in FIG. 1 is replaced with a NAND circuit 8. The inverted signal of the signal input terminal 2 is output to the signal output terminal 7. Therefore, the content of the bus is fixed to the "H" level while the control input signal is at the "L" level, and the inverted signal of each functional block is output while the control input signal is at the "H" level.

In this embodiment, the bus is precharged to the "H" level, so that the bus circuit can operate at high speed.

〔The invention's effect〕

As described above, the present invention has the effect of preventing shoot-through current between bus drivers by fixing the bus drivers of all functional block outputs to the same logic level at the change points of the selection signal input of the bus driver.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the present invention, FIG. 3 is a circuit diagram of a bus driver according to a conventional example, and FIG. 4 is a conventional example. FIG. 5 is a time chart showing an operation example when the bus driver according to the present invention is used, and FIG. 5 is a time chart showing an operation example when the bus driver according to the present invention is used. 1 ... Control input terminal, 2 ... Signal input terminal, 3 ... Selection signal input terminal, 4,5 ... AND circuit, 6 ... Tri-state circuit, 7 ... Signal output terminal, 8 ... NAND circuit

Claims (1)

[Claims] 1. A bus driver circuit, which is provided in each of a plurality of functional blocks commonly connected to a bus and selectively supplies data to the bus, and a signal input terminal for receiving output data of the functional block; A selection signal input terminal that receives a selection signal indicating that a functional block has been selected, and one of the plurality of functional blocks is switched from an enabled state to a disenabled state and one of the other functional blocks is enabled. A control input terminal that receives a control signal that is at a logic level for a predetermined time, and outputs the data having the control signal input to the signal input terminal and the control input terminal, the control signal having an inverse logic level, particularly data supplied to the signal input terminal. A first logic circuit, the selection signal input terminal and the control input terminal are input, and the control signal has one logic level. Of the first logic circuit and the second logic circuit which always outputs a signal of an inactivation level and outputs the selection signal supplied to the selection signal input terminal when the control signal has an inverse logic level. When an output terminal is an input and an output terminal of the second logic circuit is a control input terminal and a signal supplied to the control input terminal is at an activation level, an output signal corresponding to an output of the first logic circuit is output to the bus. And a tri-state circuit that supplies a signal of a constant level to the output terminal when the signal supplied to the output terminal connected to the control input terminal is at the inactivation level. .