JPH0758914B2 - PCM Dynasim Shimureta - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a PCM dynamic simulator used for a dynamic test of, for example, a digital circuit or a digital signal processing system.

[Technical background of the invention]

Conventionally, a PCM simulator is used as a test signal generator to test the dynamic function and performance of a digital signal processing system including a digital circuit or software. FIG. 4 is a dynamic test system diagram of a conventional digital signal processing system, and 11 in the figure is
It is a PCM simulator.

The PCM serial data 11a from the PCM simulator 11 is decoded by the PCM decoder 12 in the digital signal processing system 10 and processed by the digital signal processing device 13 such as a computer to perform a dynamic function test. .

The PCM simulator 11 may be a simple one that outputs only a fixed pattern or a complicated one that can change the output pattern so as to simulate a satellite telemetry signal.

[Problems of background technology]

However, while changing the pattern in the PCM simulator that can change these output patterns (data format,
Changes such as bit patterns) may cause the output to be interrupted. This is an obstacle to performing a dynamic functional test in the digital signal processing system 10, for example. Digital signal processing system due to input interruption
This is because the 10 PCM decoders 12 are locked off.

On the other hand, a PCM simulator that generates only a simple fixed pattern is useful when testing static characteristics, but cannot be used when changes are required over time.

In addition, there is no device that corresponds to the case where you want to dynamically change a part of general PCM serial data, not limited to the output of a test signal generator such as a PCM simulator.

[Object of the Invention] The present invention has been made in order to eliminate the above-mentioned conventional drawbacks, and is n-th (n is an arbitrary natural number) word data of a PCM serial data generated by a PCM generator from a synchronization signal. It is an object of the present invention to provide a PCM dynamic simulator capable of dynamically replacing (in real time) with an arbitrary bit pattern.

[Summary of the Invention] A PCM dynamic simulator according to the present invention detects a sync signal from PCM serial data by a sync signal detection circuit, initializes a counter circuit at the detection timing, and causes the counter circuit to start counting a word clock. , A control signal is output during a period in which the count value matches an arbitrary count value n set externally, and the bit pattern generating circuit is turned on by the control signal to set an arbitrary externally set value. The word data of the bit pattern is generated in synchronization with the bit clock, and the switching circuit that normally derives the PCM serial data is switched and controlled by the control signal output from the counter circuit to derive the output of the bit pattern generation circuit. It was done like this.

Embodiments of the Invention Embodiments of the PCM dynamic simulator of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the embodiment,
Reference numeral 21 in the figure is a PCM code generator such as a PCM simulator.

PCM serial data generated by this PCM code generator 21
21a is transferred to the PCM dynamic simulator 22 together with the word clock 32a and the bit clock 35 used for this data generation.

As is apparent from the data format shown in FIG. 2, the PCM serial data 21a has word W at regular intervals.
Sync signals S1, S2, ... Are added between 1, W2 ,.

The PCM dynamic simulator 22 decodes this synchronization signal, replaces the bit pattern of the n-th (n is an arbitrary natural number) word with a desired pattern with reference to it,
The data is transferred to the digital signal processing system 23.

FIG. 3 is a block diagram showing the internal configuration of the PCM dynamic simulator 22. The PCM serial data 21a is input to the sync signal detection circuit 31 and the switching circuit 34.

The synchronization signal detection circuit 31 detects a synchronization signal from the input PCM serial data 21a, generates a trigger signal 31a, and outputs the trigger signal 31a to the counter circuit 32.

This counter circuit 32 has a PC together with PCM serial data 21a.
The word clock 32a sent from the M code generator 21 is input. Also, this counter circuit
For 32, it is possible to set any count value from the operation panel.

That is, the counter circuit 32 uses the trigger signal 31a as a start control signal to reset the count value and start counting the word clock 32a. Then, the switching control signal 32b is supplied to the bit pattern generating circuit 33 and the switching circuit 34 during the period when the count value matches the set count value.
It is designed to output to.

The bit pattern generation circuit 33 and the switching circuit 34 have the above
A bit clock 35 sent from the PCM code generator 21 is input together with the PCM serial data 21a.

The bit pattern generation circuit 33 is turned on by the switching control signal 32b from the counter circuit 32 and generates word data of an arbitrary bit pattern set from the operation panel or the like in synchronization with the bit clock 35. The generated word data 33a is output to the switching circuit 34.

The switching circuit 34 receives the switching control signal 32b from the counter circuit 32.
Is supplied, the selected output of the PCM serial data 21a is switched to the selected output of the word data 33a from the bit pattern generation circuit 33 in synchronization with the bit clock 35.

Next, the operation of the PCM dynamic simulator of the present invention configured as above will be described.

In the PCM dynamic simulator 22 shown in FIG. 3, the PCM code generator 21 to the PC shown in the data format of FIG.
When the M serial data 21a is supplied, the PCM serial data 21a is input to the synchronization signal detection circuit 31 and the switching circuit 34.

The sync signal detection circuit 31 is a sync signal for the PCM serial data 21a.
Detects S1, S2, ..., and trigger signal 31a at each detection timing
Is generated and sent to the counter circuit 32. As a result, the counter circuit 32 starts counting the word clock 32a after resetting the count value using the trigger signal 31a as the start control signal.

Here, when it is desired to replace the nth word clock Wn from the synchronization signal with an arbitrary bit pattern, the count value n is set in the counter circuit 32 and the desired bit pattern is set in the bit pattern generation circuit 33 from the operation panel or the like. .

When this setting is made, the counter circuit 32 outputs the switching control signal 32b during the period when the count value of the word clock 32a matches the set count value.

When this switching control signal 32 is output, the bit pattern generation circuit 33 is turned on, and the word data 33 of the bit pattern set by the operator arbitrarily from the operation panel or the like.
a is generated in synchronization with the bit clock 35 and is output to the switching circuit 34.

On the other hand, the switching circuit 34 switches from the selective output state of the PCM serial data 21a to the word data selective output state from the bit pattern generation circuit 33 in synchronization with the bit clock during the period in which the switching control signal 32 is applied. That is, the nth word data Wn from the sync signal is replaced with the word data output from the bit pattern generation circuit 33.

In the data format of FIG. 2, word Wn
Of the bit pattern 25 is changed, the bit pattern shows that the second and m-th bits 2 and m have been changed, and the bit pattern 26 shows the example after the change.

By the way, in FIG. 3, the word clock 32a and the bit clock 35 are explained as being given from the PCM code generator 21, but this is because a general PCM simulator uses them as output signals. However, if these signals are not given, it is necessary to add a bit synchronizing circuit or the like to newly create the PCM serial data 21a.

As described above, according to the present invention, the sync signal in the PCM serial data is detected, and the bit pattern is input during the input period of the nth word data which is preset based on this sync signal. Since the word data of the bit pattern set in the generation circuit is generated and switched and output, the time-fixed PCM serial data in the digital signal processing system is not affected. Some word data can be dynamically replaced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the PCM dynamic simulator of the present invention, FIG. 2 is a diagram showing a data format of PCM serial data applied to the PCM dynamic simulator of the above, and FIG. FIG. 4 is a system diagram of an embodiment of the configuration, and FIG. 4 is a dynamic test system diagram of a conventional digital signal processing system. 21 …… PCM code generator, 22 …… PCM dynamic simulator, 23 …… Digital signal processing system.

Claims (1)

[Claims] 1. A synchronization signal detection circuit for inputting PCM serial data to which a synchronization signal is added between word data at regular intervals and detecting the synchronization signal from the data, and synchronizing with the word data of the PCM serial data. For counting the word clock to be started, the count value is initialized by the synchronization signal detection output of the synchronization signal detection circuit as a trigger to start counting, and the count value is set to an arbitrary count value set from the outside. A counter circuit that outputs a control signal during the specified period and the control signal output from this counter circuit turns on and synchronizes the word data of an arbitrary bit pattern set externally with the bit data of the PCM serial data. Bit pattern generation circuit that is generated in synchronization with the generated bit clock, and usually the PCM serial data Derived, the duration of the control signal from the counter circuit is applied, PCM dynamic simulator and a switching circuit for switching an output of the bit pattern generation circuit.