JPH0758945B2 - Multiple data separation / format conversion method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex data separation / format conversion system for performing separation and format conversion of multiplex signals in which digital signals are multiplexed.

(Prior Art) Conventionally, a multiplexed signal is converted to a digital signal (digital data).
An elastic store memory (hereinafter simply referred to as ES) is used for the separation and format conversion.

For example, when the multiplex input data (207) in FIG. 4 is separated / format-converted to generate the output data (208)-(210), the separation / format conversion circuit shown in FIG. 3 is used. This separation / format conversion circuit is ES31
.About.33, D flip-flops 34 to 36, and a control pulse generating circuit (PG) 37, the data input terminal 38 supplies the multiplex input data (207) to ES 31 to 33. Each ES31
Writing to ~ 33 and reading from each ES are controlled by a write signal and a read signal from the control pulse generation circuit 37. The ES31 to 33 output the output data (201) to (203) shown in FIG. 4 by the write signal and the read signal from the control pulse generating circuit 37, respectively.

The output clocks shown in FIG. 4 are given to the D flip-flops 34 to 36, and the D flip-flops 34 to 36 are thereby supplied.
36 outputs output data (208) to (210) to data output terminals 39 to 41, respectively.

In this way, in the past, multiplex signals were separated into digital signals.
In the case of format conversion, a plurality of ES are used, and the control pulse generation circuit controls the write and read signals to and from the ES to perform separation / format conversion.

(Problems to be Solved by the Invention) However, in the above-described multiplex data separation / format conversion method, there is a problem that the mounting area becomes large and the cost becomes high because a plurality of ESs must be used.

It is an object of the present invention to provide a multiplex data separation / format conversion method which has a small mounting area and can achieve cost reduction.

(Means for Solving the Problems) According to the present invention, N (N is an integer of 2 or more) digital data is time-division-multiplexed to separate and format multiplex data into the N digital data. Memory means for storing the multiplexed data, N delay means connected to the memory means and having different delay amounts, and N D means connected to the N delay means.
A flip-flop and a control means for controlling at least the memory means and the D flip-flop are provided, and the multiplexed data is read by the control means at a predetermined read speed and given to the N delay means. And outputting the delayed multiplexed data different from each other from each of the delay means to drive the D flip-flop at a speed of 1 / N of the predetermined read speed. A format conversion method is obtained.

(Examples) Next, the present invention will be described with reference to Examples.

Referring to FIG. 1, the multiplex data separation / format conversion circuit used in the present invention includes one ES11, two delay circuits 12 and 13, and three D flip-flops 14, 15 and 16.
And a control pulse generation circuit 17. The data input terminal 18 is connected to the data input terminal of ES11, and the output terminal of ES11 is connected to the delay circuits 12 and 13 and the D input terminal of the D flip-flop 16. The outputs of the delay circuits 12 and 13 are connected to the D input terminals of the D flip-flops 14 and 15, respectively, and the outputs of the D flip-flops 14, 15 and 16 are output to the data output terminals 19, 20 and 21 as converted outputs. Is output.

By the way, the delay circuit 12 delays the input data by 2 bits and outputs it, and the delay circuit 13 delays the input data by 1 bit and outputs it. On the other hand, the output terminal of ES11 has delay circuits 12 and 13
, And is directly connected to the D flip-flop 16, but may be connected to the D flip-flop 16 via a delay circuit of 0-bit delay.

Next, referring to FIG. 2 as well, the multiple data separation according to the present invention
The operation of the format conversion method will be described.

The control pulse generator (PG) 17 sends a control signal such as a write clock to the ES 11 in accordance with the speed of the multiplexed data input from the input terminal 18. Only the data portion of the multiplexed data is written in ES11 based on this write clock. The input data (multiplexed data) is assumed to be three-multiplexed data as shown by the input data (108) in FIG. That is, three pieces of digital data are time-division multiplexed.

Next, the control pulse generator 17 sends a control signal such as a read clock independent of the write clock to ES11.
Multiple data (data portion) is sequentially read from the ES11 based on this read clock. That is, the ES output data (a) shown in FIG. 2 is sent from ES11.

The control pulse generator 17 sends a delay clock (shown in FIG. 2) to the delay circuits 12 and 13, and the delay circuit 12 delays the ES output data (a) by 2 bits based on this delay clock. And output as a 2-bit delay circuit output (b) (shown in FIG. 2). Similarly, the delay circuit 13 delays the ES output data by 1 bit based on the delay clock and sends it as a 1-bit delay circuit output (not shown).

These 2-bit delay circuit output (b), 1-bit delay circuit output, and ES output data (a) are given to D flip-flops 14, 15, and 16, respectively. An output clock from the control pulse generator 17 to the D flip-flops 14, 15 and 16 at a speed 1/3 of the read clock (shown in FIG. 2).
Is given, and each D flip-flop 14, 15, and 16
Operates with this output clock. in this way,
Since each of the D flip-flops 14, 15 and 16 operates with the output clock having a speed of 1/3 of the read clock, the D flip-flop 14 to which the 2-bit delay circuit output (b) is given
Then, A, D and G of the 2-bit delay circuit output (b) are selected in this order. At this time, format conversion is also performed (because the output clock is 1/3 the speed of the read clock) and output as output data (109).

Similarly, the D flip-flop 15 outputs the output data (110).
And the D flip-flop 16 outputs the output data (111).

(Effects of the Invention) As described above, according to the present invention, since logic elements are used as a circuit configuration and multiple ES can be separated and format converted using one ES, multiple data using multiple ES as in the conventional case can be used. It is possible to reduce the mounting area and cost compared to the separation and format conversion of.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the multiplex data separation / format conversion system according to the present invention, and FIG. 2 is a time chart for explaining the operation of the multiplex data separation / format conversion system shown in FIG. FIG. 3 is a block diagram of a conventional multiplex data separation / format conversion system, and FIG. 4 is a time chart for explaining the operation of the multiplex data separation / format conversion system shown in FIG. 11 …… Elastic store memory (ES), 12 …… 2
Bit delay circuit, 13 …… 1 bit delay circuit, 14,15,16 ……
D flip-flop, 17 ... Control signal generation circuit (PG),
18 …… Data input terminal, 19,20,21 …… Data output terminal.

Claims (1)

[Claims] 1. A memory used for separating and format-converting multiplex data of N (N is an integer of 2 or more) time-division multiplexed into the N digital data, and storing the multiplex data. Means, N delay means connected to the memory means and having different delay amounts, and N D means connected to the N delay means
A flip-flop and a control means for controlling at least the memory means and the D flip-flop are provided, and the multiplexed data is read by the control means at a predetermined read speed and given to the N delay means. And outputting the delayed multiplexed data different from each other from each of the delay means to drive the D flip-flop at a speed of 1 / N of the predetermined read speed. Format conversion method.