JPH0758949B2 - Time division multiplexing - Google Patents

Description

TECHNICAL FIELD The present invention relates to a time division multiplexing system.

[Conventional technology]

In the conventional time division multiplexing system, the frame phase synchronizing circuit of the transmission line terminating device is switched to the clock of the same speed as the transmission line, and further the multiplexing device is switched to the clock of the higher order group.

[Problems to be Solved by the Invention]

In the above-mentioned conventional time-division multiplexing method, since clock switching is performed by both the terminating device and the multiplexing device, an elastic memory for switching to a clock of a higher order group is required in the multiplexing device according to the multiplicity. Become. In ISDN, n
It is necessary to save the order of time clots by a connection of × 64Kbps, and the elastic memory for clock transfer must be a frame phase synchronization circuit,
Increases the total data delay time (on one line) from the incoming line to the outgoing line.

[Means for Solving the Problems]

According to the time division multiplex system of the present invention, a counter for operating at the frequency of the multiplexing level of the higher order group and designating the read address of the double buffer memory is provided in the frame phase synchronizing circuit in the receiving side terminal device of the time division multiplex transmission line. The slip control of the double buffer memory and the speed conversion of the data transmission are performed by the above operation, and the clock changeover is not performed in the multiplexing device in the subsequent stage connected to the terminating device.

The frame phase synchronization circuit includes a comparison circuit that compares outputs of a counter that specifies a write address of the double buffer memory and a counter that specifies the read address, and the comparison circuit detects an approach between the write address and the read address. At this time, a configuration for instructing the counter for designating the read address to perform the slip control can be adopted.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing an embodiment of the present invention, in a frame phase synchronizing circuit 2 in a transmission line terminating device 1, input data from a transmission line 4 is sequentially written into a frame buffer (double buffer memory) 21. The write address counter 22 counts the write address from the received data on the transmission path 4 by the received clock and the received frame signal generated by the clock extraction circuit 11 and the frame synchronization circuit 12. On the other hand, the read address counter 23 is counted by the high-order group level clock (CLK) and the frame signal (FP) from the multiplexer 3, and the data is read. By this reading, transmission line 4
The data from is converted to the higher order data rate. The address comparison circuit 24 instructs the read address counter 23 to switch the surface of the frame buffer 21 to be read when the write address and the read address approach each other. This slip control performed by the frame phase synchronization circuit 2 of the transmission line terminating device 1 results in data duplication or data jump of one frame as in the conventional case. The multiplexer 3 is a multiplexing circuit 31 that accommodates the data transmission lines from the plurality of transmission line terminators 1.
And a selection circuit 32 for controlling the selection operation of the multiplexing circuit 31,
The clock (CLK) and the frame signal (F
Signal source 33 for transmitting P). With the above configuration, when inputting 1.544Mbps data from transmission line 4,
Signal source 33 to 8.448 Mbps high-order group level clock (CL
When K) is supplied to the read address counter 23, the data rate read from the frame buffer 21 is increased by about 6 times.

〔The invention's effect〕

As described above, according to the present invention, by providing the read address counter of the double buffer memory that operates at the frequency of the multiplexing level of the higher order group in the frame phase synchronizing circuit in the receiving side terminating device, slip control and speed conversion can be performed. Can be performed at the same time, and the clock transfer in the multiplexing device in the subsequent stage can be eliminated, thus avoiding the uneconomical situation of providing an elastic memory, and reducing the total data delay time on one line to n × 64 Kbps. Even if the order preservation of the connection is considered, it can be suppressed only by the delay time in the conventional terminating device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. 1 ... Transmission line terminating device, 2 ... Frame phase synchronization circuit,
3 ... Multiplexing device, 4 ... Transmission line, 21 ... Frame buffer (double buffer memory), 22 ... Write address counter, 23 ... Read address counter, 24 ... Address comparison circuit.

Claims (2)

[Claims] 1. A frame phase synchronizing circuit in a receiving side terminating device of a time division multiplex transmission line is provided with a counter which operates at a frequency of a multiplexing level of a higher order group and which designates a read address of a double buffer memory. A time division multiplexing system characterized in that slip control of the double buffer memory and speed conversion of data transmission are performed, and clock multiplexing is not performed in a multiplexing device in a subsequent stage connected to the terminating device. 2. The frame phase synchronization circuit comprises a comparison circuit for comparing outputs of a counter for designating a write address of the double buffer memory and a counter for designating the read address, the comparison circuit comprising a write address and a read address. 2. The time division multiplexing system according to claim 1, wherein a counter for designating the read address is instructed to perform the slip control when an approach to is detected.